JP3910843B2 - Semiconductor element separation method and semiconductor element separation apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element separation method and a semiconductor element separation apparatus, and more particularly to a semiconductor element separation method and a semiconductor element separation apparatus for separating a plurality of semiconductor elements formed on a wafer into individual semiconductor elements.
[0002]
As electronic devices become smaller and thinner, semiconductor devices used in electronic devices are required to be thinner. In addition, development of a stacked semiconductor device in which a plurality of semiconductor elements are stacked and accommodated in one package has been advanced, and a demand for thinning the semiconductor elements is increasing. A conventional semiconductor element has a thickness of about 200 to 250 μm, but recently, a semiconductor element having a thickness of about 50 μm has been created, and the thickness has been further reduced.
[0003]
In addition, applications where semiconductor elements are used are diversified, and many small-sized semiconductor elements such as logic elements and discrete elements composed only of circuits specialized for the user's application have been manufactured.
[0004]
[Prior art]
In general, a plurality of semiconductor elements are collectively formed on the surface (circuit formation surface) of a silicon wafer. A wafer having semiconductor elements formed on the circuit forming surface is first subjected to a back grinding process. In the back grinding process, the thickness of the wafer is reduced by polishing the side surface (back surface) opposite to the circuit formation surface formed on the wafer. After the thickness of the wafer is set to a predetermined thickness, the wafer is subjected to a dicing process and separated into semiconductor elements having a predetermined shape.
[0005]
In the dicing process, the wafer is cut along a dicing line by a dicing saw and separated into individual semiconductor elements. Generally, a dicing line is recognized by recognizing an image of a dicing mark provided on a circuit forming surface of a wafer. Therefore, dicing is generally performed with the surface of the wafer facing up.
[0006]
As another method, a wafer dicing line is cut in advance by a dicing saw from the wafer surface side by a predetermined depth to form a groove-shaped half cut (half-cut process), and then the surface side is bonded. There is a method in which a wafer is attached to a protective tape for a grinder and the back surface is back-ground (back-grinding step).
[0007]
In this method, by performing back grinding in the back grinding process, the thickness of the wafer gradually decreases, and when the back grinding progresses to the half-cut formation position, the semiconductor elements are individually separated. The
[0008]
[Problems to be solved by the invention]
However, when a wafer is mechanically cut using a dicing saw, fine cutting waste (silicon pieces in a silicon wafer) is inevitably generated. This cutting waste may enter between the above-mentioned grinder protective tape and the wafer, and when infiltrated, it causes non-uniformity in size and heat conduction, which reduces the separation yield of semiconductor elements. .
[0009]
Further, when the wafer is cut with a dicing saw, so-called kerfloss occurs. That is, a portion of the wafer corresponding to the thickness of the dicing saw is scraped away by the dicing saw, and thus this portion of the wafer cannot be used as a region for forming a semiconductor element. The thickness of the dicing saw currently used is about 80 to 100 μm. Therefore, a region having a width of about 100 μm on both sides of the dicing line cannot be used for forming a semiconductor element.
[0010]
In addition, dicing mechanically scrapes the wafer with a blade that rotates at high speed (dicing saw), and micro cracks or chipping occurs around the part scraped by the dicing saw, or excessive stress is generated. The wafer may be damaged. Therefore, a forbidden region having a predetermined width is provided in the peripheral portion of the semiconductor element. That is, a semiconductor element circuit cannot be formed in the prohibited region, and is an invalid region for circuit formation.
[0011]
The width of the forbidden region is generally about 50 to 100 μm. Therefore, when considering individual semiconductor elements, a circuit cannot be formed in a peripheral region having a width of about 100 μm, and the size of the entire semiconductor element increases accordingly. For this reason, when a semiconductor element having a small size is manufactured, the ratio of the area of the prohibited region to the entire area of the semiconductor element is increased, and the effective area for circuit formation is reduced.
[0012]
Further, when considering the entire wafer, an invalid area of about 300 μm at maximum is generated in combination with the width of the kerf loss and the width of the prohibited area for one dicing line. When the semiconductor element is large, since the number of dicing lines in one wafer is small, the ratio of the invalid area to the entire area of the wafer is small.
[0013]
However, as the semiconductor device becomes smaller, the number of dicing lines also increases. Therefore, the ratio of the invalid area to the entire wafer area increases, and the wafer cannot be used effectively. That is, the number of semiconductor elements that can be cut from one wafer is reduced.
[0014]
In addition, a fine crack is generated on the surface of the wafer ground before dicing, and if the crack is left as it is, the semiconductor element may be broken starting from the crack. It can happen. This problem becomes more prominent as the semiconductor element becomes thinner. For this reason, it is necessary to remove cracks generated on the back surface of the wafer after back grinding.
[0015]
The present invention has been made in view of the above points, and efficiently removes cracks in the wafer caused by backgrinding to greatly improve the reliability after mounting, and a wafer necessary for separation of semiconductor elements. It is an object of the present invention to greatly reduce the area of the ineffective region in the wafer and increase the region usable as a semiconductor element on the wafer.
[0016]
[Means for Solving the Problems]
The above problems can be solved by taking the following means.
[0017]
  The invention described in claim 1
  A semiconductor element separation method for separating a wafer on which a plurality of semiconductor elements are formed into individual semiconductor elements,
  By irradiating plasma from a nozzle that scans the wafer relatively in a grid pattern, from the surface side of the wafer on which a circuit is formed,Separation position for separating the semiconductor elementPartial plasma etchingAn etching process to form a half cut;
  After pasting the tape material on the front surface side of the wafer, a polishing step of mechanically polishing the back surface of the wafer by mechanically leaving a predetermined thickness so as not to communicate with the half cut;
  Separation process of separating the wafer into individual semiconductor elements by etching or chemical mechanical polishing from the back side of the waferAnd
When the wafer is half-cut into a lattice in the etching step, the partial plasma etching conditions are such that the half-cut depth at the lattice intersection and the half-cut depth at a position other than the lattice intersection are substantially the same depth. AdjustedIt is characterized by.
[0020]
Also,Claim 2The described invention
Claim 1A semiconductor element isolation method according to claim 1,
  In the etching step, a partial plasma etching nozzle performs half-cutting by scanning the wafer in a grid pattern, and at the intersection of the grids, the scanning scan speed is approximately double the scan speed at other positions. It is characterized by speed.
[0021]
  The invention according to claim 3
  The semiconductor element isolation method according to claim 1,
  In the etching step, a partial plasma etching nozzle isWaferHalf-cut by scanning in a grid,
  In addition, the partial plasma etching conditions are selected so that the intersections of the lattices have substantially the same depth as the half-cut depth at other positions.
[0022]
  Also,Claim 4The described invention
Claim 3A semiconductor element isolation method according to claim 1,
  The partial plasma etching condition at the intersection is selected so that the etching rate at the intersection is approximately half of the etching rate at the other position.
[0023]
  Also,Claim 5The described invention
Claims 1 to 4The semiconductor element isolation method according to any one of the above,
  In the separation step,
  Any one of plasma etching, wet etching, and partial plasma etching is used.
[0024]
As described above, even if any of plasma etching, wet etching, and partial plasma etching is used in the separation step, minute cracks and the like generated in the wafer in the polishing step can be reliably removed.
[0025]
  Also,Claim 6The described invention
Claims 1 to 5The semiconductor element isolation method according to any one of the above,
  Before carrying out the etching step, the method includes a resist step of disposing a resist covering the formation region of the semiconductor element on the surface of the wafer.
[0027]
  The invention described in claim 7
  Multiple semiconductor elements formedWaferA semiconductor element separation apparatus for separating the semiconductor element into individual semiconductor elements,
  By irradiating plasma from a nozzle that scans the wafer relatively in a grid pattern, the separation position for separating the semiconductor element from the surface side of the wafer on which the circuit is formed is subjected to partial plasma etching to perform a half cut. Means to form;
  Means for adjusting the partial plasma etching conditions so that the half-cut depth at the intersection of the lattice and the half-cut depth at a position other than the intersection of the lattice are substantially the same when forming the half-cut;
  SaidWaferAfter sticking the tape material on the surface side of theWaferThe back surface of the material is mechanically polished by a predetermined thickness so as not to communicate with the half cut.WaferThe
  Etching or chemical mechanical polishing from the back side of the waferImplementationByWaferAnd a means for separating the semiconductor device into individual semiconductor elements.
[0028]
  The invention according to claim 8
  The semiconductor element isolation device according to claim 7,
  SaidWaferA recognition device for recognizing the position of the upper intersection in advance;
  A driving device for doubling the scanning speed of partial plasma etching at the intersection position recognized by the recognition device is provided.
[0031]
  AboveClaims 1 and 7According to each of the described inventions, a half cut is performed by first etching the separation position for separating the semiconductor elements from the surface side of the wafer. Thus, by performing the half cut by etching, it is possible in the present invention to prevent the generation of wafer pieces that are inevitably generated when the half cut is mechanically formed. Therefore, unlike the conventional case, the wafer piece does not enter between the tape material (grinder protective tape) and the wafer, and the separation yield of the semiconductor elements can be improved.
[0032]
Further, by forming the half cut by etching, the width of the half cut can be made narrower than the case of performing the half cut by the dicing saw. In addition, since the half cut is formed by etching, the kerf loss that occurs when the half cut is formed by a dicing saw that is a machining process can be reduced, so that the number of semiconductor elements that can be taken from one wafer can be increased.
[0033]
Further, since the back surface of the wafer is mechanically polished with a predetermined thickness so as not to communicate with the half cut, the back surface of the wafer can be set to the predetermined thickness in a shorter time than etching. Note that, at the end of this polishing, there is a remaining part on the back surface of the wafer, so that the semiconductor element is not separated.
[0034]
In the separation process performed after the above polishing, the remaining part is removed by etching or chemical mechanical polishing from the back side of the wafer to separate the wafer into individual semiconductor elements. Therefore, by performing machining at the time of polishing, even if minute cracks, chipping, and stress are generated in the wafer, a layer (including the remaining portion) in which the minute cracks and the like are generated in the wafer is removed.
[0035]
At this time, since the layer in which micro cracks are generated is removed by etching or chemical mechanical polishing, cracks etc. remain in each semiconductor element separated at the time of this removal process unlike machining. There is no. Therefore, a highly reliable semiconductor element can be formed.
[0036]
Claims 2 to 4 and Claim 8According to the described invention, when performing the half cut by scanning the partial plasma etching nozzle in the etching process, the scanning speed at the intersection of the gratings is set to a scanning speed substantially double the scanning speed at other positions.Or the partial plasma etching conditions are selected so that the depth of the half cut at the other position is substantially the same as the depth of the half-cut at the other position, or the etching speed at the intersection is set to the approximate etching speed at the other position. Choose to halveThus, even if the nozzle is scanned twice at the intersection, the half-cut depth at the intersection can be the same as the half-cut depth at other positions.
[0037]
  Also,Claim 5According to this invention, it is possible to reliably remove minute cracks and the like generated in the wafer during polishing in the separation process (separation step).
[0038]
  Also,Claim 6According to the described invention, it is possible to prevent the circuit of the semiconductor element from being damaged in the etching process by covering the formation region of the semiconductor element with the resist before the etching process is performed.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0041]
FIG. 1 is a process diagram for explaining each process of a semiconductor element isolation method according to an embodiment of the present invention. In this figure, the thickness of the wafer 2 is shown thicker than the actual one for easy understanding.
[0042]
FIG. 1A shows the wafer 2 before performing the semiconductor element separation process. At this stage, a plurality of semiconductor elements are formed on the wafer 2. Further, the circuit surface constituting each semiconductor element is formed on the surface 2 a of the wafer 2.
[0043]
First, a resist layer 8 is disposed on the wafer 2. FIG. 1B shows a state where the resist layer 8 is formed.
[0044]
This resist layer 8 is provided as masking for etching described later, and is formed so as to cover at least the circuit surface of each semiconductor element. Further, the resist layer 8 is not formed at the separation position 7 (hereinafter, this separation position is referred to as a dicing line) where the semiconductor element 12 is separated after the wafer 2. Therefore, the dicing line 7 of the wafer 2 is exposed to the surface 2a of the wafer 2.
[0045]
After the resist layer 8 is formed, next, as shown in FIG. 1C, etching is performed on the wafer 2 (etching process). In the present invention, partial plasma etching is used as this etching.
[0046]
This is because, according to plasma etching, the surface formed by etching can be made substantially parallel to the direction of plasma. That is, the surface formed by etching can be made substantially perpendicular to the front surface (or back surface) of the wafer 2 to achieve separation by accurate processing.
[0047]
By the way, plasma etching includes batch plasma etching in which etching is performed by simultaneously irradiating plasma on the entire wafer 2 and partial plasma etching in which plasma density is partially increased for irradiation.
[0048]
In the partial plasma etching used here, only the vicinity of the dicing line 7 can be selectively etched with high-density plasma, so that the processing can be performed efficiently and the processing time can be shortened. In addition, it becomes easy to control the local etching depth and speed.
[0049]
Here, with reference to FIG. 3, the semiconductor element isolation | separation apparatus 20 which performs partial plasma etching is demonstrated. The semiconductor element separation apparatus 20 shown in the figure includes a chamber 22, a process gas introduction pipe 24, a magnetron 26, an XYZ table, and a drive unit 30.
[0050]
The chamber 22 is connected to an evacuation unit such as a vacuum pump so that the inside becomes a predetermined reduced pressure environment. An XYZ table 28 as a mounting table is provided in the chamber 22, and a wafer 2 that is an object to be processed is mounted thereon. The XYZ table 28 is configured to be movable in the X, Y, and Z directions by the drive unit 30.
[0051]
Above the XYZ table 28, a nozzle 24a extending from the gas introduction pipe 24 is disposed. The portion above the nozzle 24a is connected to a magnetron 26, and the processing gas flowing through the gas introduction pipe is irradiated with a high frequency from the magnetron 26 to generate plasma. The plasma is locally irradiated onto the wafer from the nozzle 24a, and the wafer 2 is partially etched by the action of the plasma.
[0052]
The portion irradiated with plasma can be changed by driving the XYZ table 28 in the XY direction (horizontal direction) by the drive unit 30 and moving the wafer relative to the nozzle 24a. Further, the distance between the nozzle 24a and the wafer can be adjusted by moving the XYZ table in the Z direction (vertical direction).
[0053]
The dicing line 7 of the wafer 2 can be etched by performing the etching process shown in FIG. 1C using the semiconductor element isolation device 20 having the above-described configuration. That is, by moving the XYZ table 28 by the drive unit 30 so that the plasma from the nozzle 24a is locally irradiated along the dicing line 7 of the wafer 2, the dicing line 7 is efficiently and accurately applied to the wafer 2. Can be done.
[0054]
At this time, since the resist layer 8 is formed except for the dicing line 7 as described above, the region of the wafer 2 where the semiconductor element 12 is formed is not etched. Therefore, it is possible to prevent the circuit of the semiconductor element 12 from being damaged.
[0055]
In the semiconductor element separation apparatus 20 according to the present embodiment, the wafer 2 is configured to move with respect to the nozzle 24a. However, the present invention is not limited to this. That is, the wafer 2 may be moved with respect to the nozzle 24a, or both may be moved.
[0056]
The etching process by the semiconductor element separation apparatus 20 is performed so that the etching depth from the surface 2a is about 20 μm to 150 μm when the wafer 2 is a 200 mm wafer and the thickness is 750 μm. That is, in the etching process according to the present embodiment, the wafer 2 is not completely separated, and a groove is formed up to a middle position of the wafer 2 (hereinafter, this groove is referred to as a half cut 3). In addition, the width | variety of the half cut 3 is about 10-20 micrometers.
[0057]
FIG. 2 shows the wafer 2 for explaining a scanning locus in which the nozzle 24a relatively scans on the wafer 2 (in the present embodiment, the wafer 2 actually moves) in the semiconductor element separation apparatus 20. It is a top view. In the figure, the area indicated by the satin area is an area where the resist layer 8 is formed, and the one-dot chain line in the figure indicates the dicing line 7 for separating the wafer 2. For convenience of illustration, only a part of the resist layer 8 is shown in FIG. 2, but the resist layer 8 is formed on the entire surface 2 a of the wafer 2.
[0058]
  When the nozzle 24a scans the wafer 2 relatively, as shown in FIG.scanningAs a whole, the nozzle 24a is in a grid pattern on the wafer 2.scanningTo do. Each lattice corresponds to a formation region of one semiconductor element 12. Further, the speed of the nozzle 24 a can be controlled by adjusting the moving speed of the XYZ table 28 by the driving unit 30.
[0059]
In the present embodiment, when the nozzle 24a scans the wafer 2 in a grid pattern as described above, the scanning scan speed is set to a scan speed that is substantially twice the scan speed at other positions at the grid intersections. ing. That is, the scanning speed of the nozzle 24a at the position where the dicing line 7 in the Y direction and the dicing line 7 in the X direction intersect (the position indicated by the arrow C in FIG. 2, this position is referred to as the grid intersection) is defined as the grid intersection. The scanning speed is approximately twice as high as the scanning speed at other positions.
[0060]
With this configuration, two etching processes of X-direction scanning and Y-direction scanning are performed at the grid intersection C, but the scanning speed of the nozzle 24a at the grid intersection C is substantially equal to the scanning speed at other positions. By setting the scanning speed twice, the depth of the half-cut 3 at the intersection C can be made the same as the depth of the half-cut 3 at other positions. As a result, the semiconductor element 12 can be reliably separated in the separation step described later.
[0061]
Further, the same effect can be obtained by adjusting the output of the magnetron 26 and the flow rate of the processing gas, and by making the etching rate by plasma substantially halved. At this time, a recognition device for recognizing the intersection C of the lattice may be provided, and the etching rate or the scanning speed may be varied based on the output of the recognition device. Note that the cross-sectional area in the XY direction of the plasma irradiated from the nozzle 24a needs to be smaller than the area of the wafer 2 serving as a substrate to be processed.
[0062]
Here, returning to FIG. 1 again, the description of the semiconductor element separation processing will be continued.
When the etching process for forming the half cut 3 is completed, ashing is performed using O 2 plasma or the like, and the resist layer 8 is removed. Thereafter, the wafer 2 is positioned upside down, and the wafer 2 is attached to the back grind tape 4. The wafer 2 is attached to the back grind tape 4 with an adhesive material (not shown). In the state of being affixed to the back grind tape 4, the front surface 2a of the wafer 2 is located at the lower part in the figure, and the rear surface 2b of the wafer 2 is located at the upper part in the figure.
[0063]
When the wafer 2 is mounted on the back grind tape 4 as described above, the wafer 2 is mounted on the back grind apparatus, and a mechanical polishing process is performed on the back surface 2b of the wafer 2 as shown in FIG. Is carried out (polishing step). As described above, the wafer 2 has a thickness of about 750 μm, and the thickness of the semiconductor element 12 formed from the wafer 2 is increased as it is.
[0064]
For this reason, the thickness of the wafer 2 is reduced by polishing the back surface 2b (the surface opposite to the circuit formation surface) of the wafer 2, thereby reducing the thickness of the semiconductor element 12. Such polishing is referred to as back grinding.
[0065]
In the polishing process in this embodiment, a polishing process of about 600 to 730 μm is performed. In this embodiment, the back surface 2b of the wafer 2 is mechanically polished. 2b can be polished to a predetermined thickness. In the polishing step, as shown in FIG. 1E, the wafer 2 is polished until it has a predetermined thickness (for example, about 20 to 150 μm). At this time, the back grind tape 4 functions to protect the circuit forming surface.
[0066]
Further, in the polishing step, the thickness of the wafer 2 is not polished to the thickness of the semiconductor element 12 but is kept at a thickness larger by a predetermined thickness. As a result, the half-cut 3 does not communicate with the back surface 2 b, and therefore the semiconductor element 12 is connected to the remaining portion 5. The thickness of the remaining portion 5 is set to 10 to 50 μm, for example.
[0067]
When the above polishing process is completed, a separation process for etching the semiconductor element 12 to a predetermined thickness is subsequently performed. By performing this separation step, the remaining portion 5 is removed, and thus the wafer 2 is separated into individual semiconductor elements 12 as shown in FIG.
[0068]
In this separation process, since the wafer 2 is separated into the semiconductor elements 12 by etching from the back surface 2b side of the wafer 2, minute cracks, chipping, and stress generated on the back surface 2b of the wafer 2 in the polishing process can be removed. .
That is, in the polishing process, since the mechanical polishing is performed as described above, the polishing rate can be improved, but the above-described minute cracks or the like may occur on the back surface 2b of the wafer 2. If the wafer 2 is separated into the semiconductor elements 12 while leaving them as they are, the semiconductor elements 12 may be damaged over time and a predetermined operation may not be performed.
[0069]
Therefore, in this embodiment, as described above, the thickness of the wafer 2 is not polished to the thickness of the semiconductor element 12 in the polishing step, but is kept large by a predetermined thickness, and the predetermined thickness of the semiconductor element 12 in the separation step. It is set as the structure etched to this extent. Thereby, the layer in which minute cracks or the like are generated is removed by the etching process. Unlike the machining process, the etching process does not cause cracks during the process. Therefore, no cracks or the like remain in the separated semiconductor element 12, and the highly reliable semiconductor element 12 can be formed.
[0070]
As an etching method used in the separation step, dry etching or wet etching may be used, but plasma etching is preferably used. Further, the plasma etching may be batch plasma etching or partial plasma etching. It is also possible to use chemical mechanical polishing (CMP). Even if any of these methods is used, the above-described minute cracks generated in the wafer 2 can be removed.
[0071]
As described above, according to the semiconductor element isolation method according to the present embodiment, since the half cut 3 is formed by etching, generation of a wafer piece that is inevitably generated when the conventional half cut is mechanically formed is generated. Can be prevented. Therefore, the wafer piece does not enter between the back grind tape 4 (the grinder protective tape) and the wafer 2 as in the conventional case, and the separation yield of the semiconductor elements 12 can be improved.
[0072]
Further, by forming the half cut 3 by etching, the width of the half cut 3 can be made narrower than when half cutting is performed by a conventional dicing saw. Specifically, since the dicing saw has a width of about 80 μm to 100 μm, a region having a width of about 100 μm along the dicing line is conventionally removed. On the other hand, in this embodiment, since the half cut 3 is formed by etching, the width is about 10 μm to 20 μm, which is the width that can be etched.
[0073]
Therefore, the area of the region used for separating the semiconductor element 12 (that is, the area of the region where the semiconductor element cannot be formed) is about 1/5 to 1/10 compared to the conventional dicing. The number of semiconductor elements made from one wafer can be increased by about 15%.
[0074]
Further, according to the separation of the semiconductor element 12 by etching, there is no need to provide a forbidden region that may cause chipping during dicing. That is, it is not necessary to provide a forbidden region around the semiconductor element 12 to be separated, and a circuit may be formed over the entire surface of the separated semiconductor element 12. Therefore, there is no need to provide a prohibited region as in the prior art, and the effective area of the semiconductor element 12 can be increased.
[0075]
【The invention's effect】
As described above, according to the present invention, it is possible to prevent the generation of a wafer piece by performing a half cut by etching, so that the wafer piece does not enter between the tape material and the wafer. The separation yield can be improved.
[0076]
Further, by forming a half cut by etching, the width of the half cut can be reduced and the kerf loss can be reduced, so that the number of semiconductor elements that can be taken from one wafer can be increased.
[0077]
In addition, a layer in which micro cracks generated by performing machining during polishing is removed by etching or chemical mechanical polishing, so that a highly reliable semiconductor element can be formed. it can.
[0078]
Further, even when the nozzle is scanned twice at the intersection, the half-cut depth at this intersection can be made the same as the half-cut depth at other positions.
[0079]
Furthermore, since the formation region of the semiconductor element is covered with a resist before the etching is performed, it is possible to prevent damage to the circuit of the semiconductor element.
[Brief description of the drawings]
FIG. 1 is a diagram showing a process for explaining a semiconductor element isolation method according to an embodiment of the present invention.
FIG. 2 is a plan view of a wafer separated by a semiconductor element separation method according to an embodiment of the present invention.
FIG. 3 is a configuration diagram of a semiconductor element isolation device used in a semiconductor element isolation method according to an embodiment of the present invention.
[Explanation of symbols]
2 wafers
2a Surface
2b Back side
3 groove
4 Back grinding tape
5 balance
7 Dicing line
8 resist layer
12 Semiconductor elements
20 Semiconductor device separation device
22 Chamber 22
24 Processing gas introduction pipe
24a nozzle
26 Magnetron
28 XYZ table
30 Drive unit

Claims (8)

A semiconductor element separation method for separating a wafer on which a plurality of semiconductor elements are formed into individual semiconductor elements,
By irradiating plasma from a nozzle that scans the wafer relatively in a grid pattern, the separation position for separating the semiconductor element from the surface side of the wafer on which the circuit is formed is subjected to partial plasma etching to perform a half cut. An etching process to be formed;
After pasting the tape material on the front surface side of the wafer, a polishing step of mechanically polishing the back surface of the wafer by mechanically leaving a predetermined thickness so as not to communicate with the half cut;
Separating the wafer into individual semiconductor elements by performing etching or chemical mechanical polishing from the back side of the wafer,
When the wafer is half-cut into a lattice in the etching step, the partial plasma etching conditions are such that the half-cut depth at the lattice intersection and the half-cut depth at a position other than the lattice intersection are substantially the same depth. A method for separating a semiconductor element, characterized in that The semiconductor element isolation method according to claim 1,
In the etching step, a partial plasma etching nozzle performs half-cutting by scanning the wafer in a grid pattern, and at the intersection of the grids, the scanning scan speed is approximately double the scan speed at other positions. A method for separating a semiconductor element, characterized in that the speed is set. The semiconductor element isolation method according to claim 1,
In the etching step, the partial plasma etching nozzle performs half-cut by scanning the wafer in a lattice pattern,
In addition, the partial plasma etching conditions are selected so that at the intersection of the lattices, the partial plasma etching conditions are selected so as to be substantially the same as the half-cut depth at other positions. A semiconductor element isolation method according to claim 3,
The partial plasma etching condition at the intersection is selected so that the etching rate at the intersection is approximately half of the etching rate at the other position. A semiconductor element isolation method according to any one of claims 1 to 4,
In the separation step,
Any one of plasma etching, wet etching, and partial plasma etching is used. A semiconductor element isolation method according to any one of claims 1 to 5,
A semiconductor element isolation method, comprising: a resist step of disposing a resist covering a formation region of the semiconductor element on the surface of the wafer before performing the etching step. A semiconductor element separation apparatus for separating a wafer on which a plurality of semiconductor elements are formed into individual semiconductor elements,
By irradiating plasma from a nozzle that scans the wafer relatively in a grid pattern, the separation position for separating the semiconductor element from the surface side of the wafer on which the circuit is formed is subjected to partial plasma etching to perform a half cut. Means to form;
Means for adjusting the partial plasma etching conditions so that the half-cut depth at the intersection of the lattice and the half-cut depth at a position other than the intersection of the lattice are substantially the same when forming the half-cut;
After adhering a tape on the surface of the wafer, the back surface of the wafer the half-cut and the communication so as not to leave the remainder by a predetermined thickness mechanically polished said wafer,
And a means for separating the wafer into individual semiconductor elements by performing etching or chemical mechanical polishing from the back side of the wafer . The semiconductor element isolation device according to claim 7,
A recognition device for previously recognizing the position of the intersection on the wafer ;
A semiconductor device separating apparatus comprising: a driving device for substantially doubling the scanning speed of partial plasma etching at the intersection position recognized by the recognition device.

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