FR3113775B1 - Puce électronique - Google Patents

Puce électronique Download PDF

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Publication number
FR3113775B1
FR3113775B1 FR2008948A FR2008948A FR3113775B1 FR 3113775 B1 FR3113775 B1 FR 3113775B1 FR 2008948 A FR2008948 A FR 2008948A FR 2008948 A FR2008948 A FR 2008948A FR 3113775 B1 FR3113775 B1 FR 3113775B1
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Prior art keywords
chip
face
pillars
microchip
fixing
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FR2008948A
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FR3113775A1 (fr
Inventor
Olivier Ory
Christophe Lebrere
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STMicroelectronics Tours SAS
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STMicroelectronics Tours SAS
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Priority to FR2008948A priority Critical patent/FR3113775B1/fr
Priority to US17/458,070 priority patent/US11824028B2/en
Publication of FR3113775A1 publication Critical patent/FR3113775A1/fr
Application granted granted Critical
Publication of FR3113775B1 publication Critical patent/FR3113775B1/fr
Priority to US18/497,691 priority patent/US20240063162A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Micromachines (AREA)

Abstract

Puce électronique La présente description concerne une puce électronique (11) comprenant au moins trois piliers (29) métalliques se prolongeant depuis une face de la puce, la hauteur (H) de chaque pilier étant supérieure à 20 µm, les piliers étant destinés à surélever la puce lors d'une fixation de la puce, par ladite face, au moyen d'un matériau de fixation (15) sur la paroi (13) d'un support. Figure pour l'abrégé : Fig. 1
FR2008948A 2020-09-03 2020-09-03 Puce électronique Active FR3113775B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR2008948A FR3113775B1 (fr) 2020-09-03 2020-09-03 Puce électronique
US17/458,070 US11824028B2 (en) 2020-09-03 2021-08-26 Die with metal pillars
US18/497,691 US20240063162A1 (en) 2020-09-03 2023-10-30 Die with metal pillars

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2008948 2020-09-03
FR2008948A FR3113775B1 (fr) 2020-09-03 2020-09-03 Puce électronique

Publications (2)

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FR3113775A1 FR3113775A1 (fr) 2022-03-04
FR3113775B1 true FR3113775B1 (fr) 2022-09-30

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FR2008948A Active FR3113775B1 (fr) 2020-09-03 2020-09-03 Puce électronique

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FR (1) FR3113775B1 (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080136004A1 (en) * 2006-12-08 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chip package structure and method of forming the same
DE102010027932A1 (de) * 2010-04-19 2011-10-20 Robert Bosch Gmbh Verbundbauteil und Verfahren zum Herstellen eines Verbundbauteils
US9123763B2 (en) * 2011-10-12 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure having at least one package comprising one die being disposed in a core material between first and second surfaces of the core material

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Publication number Publication date
US11824028B2 (en) 2023-11-21
US20240063162A1 (en) 2024-02-22
FR3113775A1 (fr) 2022-03-04
US20220068866A1 (en) 2022-03-03

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