FR3109838B1 - Transistors contraints et mémoire à changement de phase - Google Patents

Transistors contraints et mémoire à changement de phase Download PDF

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Publication number
FR3109838B1
FR3109838B1 FR2004330A FR2004330A FR3109838B1 FR 3109838 B1 FR3109838 B1 FR 3109838B1 FR 2004330 A FR2004330 A FR 2004330A FR 2004330 A FR2004330 A FR 2004330A FR 3109838 B1 FR3109838 B1 FR 3109838B1
Authority
FR
France
Prior art keywords
portions
transistors
semiconductor layer
change memory
phase change
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2004330A
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English (en)
Other versions
FR3109838A1 (fr
Inventor
Remy Berthelon
Olivier Weber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Original Assignee
STMicroelectronics Crolles 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Crolles 2 SAS filed Critical STMicroelectronics Crolles 2 SAS
Priority to FR2004330A priority Critical patent/FR3109838B1/fr
Priority to US17/244,514 priority patent/US11723220B2/en
Publication of FR3109838A1 publication Critical patent/FR3109838A1/fr
Application granted granted Critical
Publication of FR3109838B1 publication Critical patent/FR3109838B1/fr
Priority to US18/335,940 priority patent/US20230329008A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/32—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the bipolar type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

Landscapes

  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

Transistors contraints et mémoire à changement de phase La présente description concerne un procédé de fabrication d'une puce électronique, comprenant les étapes successives consistant à : prévoir une couche semiconductrice située sur un isolant (130) recouvrant un substrat semiconducteur (110) ; oxyder des premières et deuxièmes portions de la couche semiconductrice jusqu'à l'isolant ; générer des contraintes (310L) dans des troisièmes portions (210) de la couche semiconductrice chacune s'étendant entre deux portions oxydées à l'étape précédente de la couche semiconductrice ; former des cavités s'étendant au moins jusqu'au substrat à travers les deuxièmes portions et l'isolant ; former des transistors bipolaires (545) dans au moins une partie des cavités et des premiers transistors à effet de champ (610) dans et sur les troisièmes portions ; et former des points mémoire (640) à changement de phase reliés aux transistors bipolaires. Figure pour l'abrégé : Fig. 6A
FR2004330A 2020-04-30 2020-04-30 Transistors contraints et mémoire à changement de phase Active FR3109838B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR2004330A FR3109838B1 (fr) 2020-04-30 2020-04-30 Transistors contraints et mémoire à changement de phase
US17/244,514 US11723220B2 (en) 2020-04-30 2021-04-29 Strained transistors and phase change memory
US18/335,940 US20230329008A1 (en) 2020-04-30 2023-06-15 Strained transistors and phase change memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2004330 2020-04-30
FR2004330A FR3109838B1 (fr) 2020-04-30 2020-04-30 Transistors contraints et mémoire à changement de phase

Publications (2)

Publication Number Publication Date
FR3109838A1 FR3109838A1 (fr) 2021-11-05
FR3109838B1 true FR3109838B1 (fr) 2022-05-20

Family

ID=72178678

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2004330A Active FR3109838B1 (fr) 2020-04-30 2020-04-30 Transistors contraints et mémoire à changement de phase

Country Status (2)

Country Link
US (2) US11723220B2 (fr)
FR (1) FR3109838B1 (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7811879B2 (en) * 2008-05-16 2010-10-12 International Business Machines Corporation Process for PCM integration with poly-emitter BJT as access device
IT1391861B1 (it) * 2008-09-10 2012-01-27 St Microelectronics Rousset Processo per la realizzazione di un dispositivo di memoria includente un transistore verticale bipolare a giunzione ed un transistore cmos con spaziatori
FR3003685B1 (fr) 2013-03-21 2015-04-17 St Microelectronics Crolles 2 Procede de modification localisee des contraintes dans un substrat du type soi, en particulier fd soi, et dispositif correspondant
FR3049111B1 (fr) 2016-03-21 2018-04-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de realisation de transistors mos et bipolaires

Also Published As

Publication number Publication date
FR3109838A1 (fr) 2021-11-05
US20210343788A1 (en) 2021-11-04
US20230329008A1 (en) 2023-10-12
US11723220B2 (en) 2023-08-08

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