FR3101980B1 - Processeur - Google Patents

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Publication number
FR3101980B1
FR3101980B1 FR1911348A FR1911348A FR3101980B1 FR 3101980 B1 FR3101980 B1 FR 3101980B1 FR 1911348 A FR1911348 A FR 1911348A FR 1911348 A FR1911348 A FR 1911348A FR 3101980 B1 FR3101980 B1 FR 3101980B1
Authority
FR
France
Prior art keywords
data
processor
masked
arithmetic
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1911348A
Other languages
English (en)
Other versions
FR3101980A1 (fr
Inventor
Rene Peyrard
Fabrice Romain
Jean-Michel Derien
Christophe Eichwald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
STMicroelectronics Grenoble 2 SAS
Original Assignee
STMicroelectronics Rousset SAS
STMicroelectronics Grenoble 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS, STMicroelectronics Grenoble 2 SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1911348A priority Critical patent/FR3101980B1/fr
Priority to US17/038,774 priority patent/US11922133B2/en
Priority to CN202011079492.XA priority patent/CN112650471A/zh
Publication of FR3101980A1 publication Critical patent/FR3101980A1/fr
Application granted granted Critical
Publication of FR3101980B1 publication Critical patent/FR3101980B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/764—Masking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/04—Masking or blinding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Image Processing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

Processeur La présente description concerne un procédé de traitement de données masquées (Data_M, Data_S) par un processeur (100) comprenant une unité (104) arithmétique et logique, dans lequel lesdites données masquées (Data_M, Data_S) restent masquées pendant leur traitement dans ladite unité arithmétique et logique. Figure pour l'abrégé : Fig. 1
FR1911348A 2019-10-11 2019-10-11 Processeur Active FR3101980B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1911348A FR3101980B1 (fr) 2019-10-11 2019-10-11 Processeur
US17/038,774 US11922133B2 (en) 2019-10-11 2020-09-30 Processor and method for processing mask data
CN202011079492.XA CN112650471A (zh) 2019-10-11 2020-10-10 用于处理掩蔽数据的处理器和方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1911348A FR3101980B1 (fr) 2019-10-11 2019-10-11 Processeur
FR1911348 2019-10-11

Publications (2)

Publication Number Publication Date
FR3101980A1 FR3101980A1 (fr) 2021-04-16
FR3101980B1 true FR3101980B1 (fr) 2021-12-10

Family

ID=69810935

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1911348A Active FR3101980B1 (fr) 2019-10-11 2019-10-11 Processeur

Country Status (3)

Country Link
US (1) US11922133B2 (fr)
CN (1) CN112650471A (fr)
FR (1) FR3101980B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3101982B1 (fr) 2019-10-11 2024-03-08 St Microelectronics Grenoble 2 Détermination d'un bit indicateur
FR3101983B1 (fr) 2019-10-11 2021-11-12 St Microelectronics Grenoble 2 Détermination d'un bit indicateur
FR3129011B1 (fr) * 2021-11-10 2023-11-10 St Microelectronics Rousset Multiplication

Family Cites Families (30)

* Cited by examiner, † Cited by third party
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US6173393B1 (en) 1998-03-31 2001-01-09 Intel Corporation System for writing select non-contiguous bytes of data with single instruction having operand identifying byte mask corresponding to respective blocks of packed data
FR2820914A1 (fr) 2001-02-15 2002-08-16 Bull Cp8 Procede de securisation d'un ensemble electronique mettant en oeuvre en algorithme cryptographique utilisant des operations booleennes et des operations arithmetiques, et systeme embarque correspondant
US20040254966A1 (en) 2003-05-16 2004-12-16 Daewoo Educational Foundation Bit manipulation operation circuit and method in programmable processor
US8156343B2 (en) 2003-11-26 2012-04-10 Intel Corporation Accessing private data about the state of a data processing machine from storage that is publicly accessible
US7370180B2 (en) 2004-03-08 2008-05-06 Arm Limited Bit field extraction with sign or zero extend
DE602004013206T2 (de) * 2004-12-01 2009-05-14 Telecom Italia S.P.A. Verfahren und diesbezügliche einrichtung zur hardwareorientierten umsetzung zwischen arithmetik- und boolscher zufallsmaskierung
JP4783104B2 (ja) * 2005-09-29 2011-09-28 株式会社東芝 暗号化／復号装置
US20100281092A1 (en) 2006-08-09 2010-11-04 Thomas Kuenemund Standard cell for arithmetic logic unit and chip card controller
US7921148B2 (en) * 2006-08-09 2011-04-05 Infineon Technologies Ag Standard cell for arithmetic logic unit and chip card controller
KR101566408B1 (ko) 2009-03-13 2015-11-05 삼성전자주식회사 불 마스크와 산술 마스크의 변환 회로 및 변환 방법
US8392494B2 (en) 2009-06-26 2013-03-05 Intel Corporation Method and apparatus for performing efficient side-channel attack resistant reduction using montgomery or barrett reduction
JP5594427B2 (ja) 2011-03-18 2014-09-24 富士通株式会社 秘匿データ処理方法、プログラム及び装置
WO2013081588A1 (fr) 2011-11-30 2013-06-06 Intel Corporation Instruction et logique destinées à donner une fonctionnalité de comparaison horizontale sur un vecteur
WO2013095630A1 (fr) 2011-12-23 2013-06-27 Intel Corporation Appareil et procédé d'arrière-plan d'instruction d'extrait amélioré
US9390291B2 (en) * 2012-12-29 2016-07-12 Intel Corporation Secure key derivation and cryptography logic for integrated circuits
US9542154B2 (en) 2013-06-25 2017-01-10 Intel Corporation Fused multiply add operations using bit masks
EP2884387B1 (fr) 2013-12-13 2016-09-14 Thomson Licensing Ajout modulaire efficace résistant aux attaques par canaux auxiliaires
US9875377B2 (en) * 2014-03-31 2018-01-23 Stmicroelectronics S.R.L. Encryption device of a substitution-box type, and corresponding encryption method and computer program product
EP3001307B1 (fr) 2014-09-25 2019-11-13 Intel Corporation Processeurs, procédés, systèmes et instructions de mélange binaire
CN108604987B (zh) 2016-03-03 2022-03-29 密码研究公司 将布尔掩码值转换为用于加密操作的算术掩码值
CN106788974B (zh) * 2016-12-22 2020-04-28 深圳国微技术有限公司 掩码s盒、分组密钥计算单元、装置及对应的构造方法
SG11202001591UA (en) 2017-08-30 2020-03-30 Inpher Inc High-precision privacy-preserving real-valued function evaluation
EP3503460A1 (fr) 2017-12-22 2019-06-26 Secure-IC SAS Système et procédé d'addition arithmétique de données avec masque booléen
EP3557813A1 (fr) * 2018-04-17 2019-10-23 Gemalto Sa Procédé protégé contre les attaques par canaux auxiliaires effectuant une opération arithmétique d'un algorithme cryptographique mélangeant des opérations booléennes et arithmétiques
DE102018113475A1 (de) * 2018-06-06 2019-12-12 Infineon Technologies Ag Rechenwerk zum rechnen mit maskierten daten
CN109255967B (zh) 2018-09-12 2022-04-22 三星电子（中国）研发中心 用于发布信息的方法和装置
US11507699B2 (en) * 2019-09-27 2022-11-22 Intel Corporation Processor with private pipeline
FR3101983B1 (fr) 2019-10-11 2021-11-12 St Microelectronics Grenoble 2 Détermination d'un bit indicateur
FR3101981B1 (fr) 2019-10-11 2021-11-12 St Microelectronics Grenoble 2 Extraction et insertion de mots binaires
FR3101982B1 (fr) 2019-10-11 2024-03-08 St Microelectronics Grenoble 2 Détermination d'un bit indicateur

Also Published As

Publication number Publication date
FR3101980A1 (fr) 2021-04-16
US11922133B2 (en) 2024-03-05
CN112650471A (zh) 2021-04-13
US20210109711A1 (en) 2021-04-15

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