FR3101981B1 - Extraction et insertion de mots binaires - Google Patents
Extraction et insertion de mots binaires Download PDFInfo
- Publication number
- FR3101981B1 FR3101981B1 FR1911349A FR1911349A FR3101981B1 FR 3101981 B1 FR3101981 B1 FR 3101981B1 FR 1911349 A FR1911349 A FR 1911349A FR 1911349 A FR1911349 A FR 1911349A FR 3101981 B1 FR3101981 B1 FR 3101981B1
- Authority
- FR
- France
- Prior art keywords
- extraction
- binary data
- masked
- binary words
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000605 extraction Methods 0.000 title abstract 3
- 238000003780 insertion Methods 0.000 title abstract 3
- 230000037431 insertion Effects 0.000 title abstract 3
- 238000000034 method Methods 0.000 abstract 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
- G06F7/764—Masking
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/002—Countermeasures against attacks on cryptographic mechanisms
- H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
- G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/496—Multiplying; Dividing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/727—Modulo N arithmetic, with N being either (2**n)-1,2**n or (2**n)+1, e.g. mod 3, mod 4 or mod 5
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/04—Masking or blinding
- H04L2209/046—Masking or blinding of operations, operands or results of the operations
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
- H04L2209/122—Hardware reduction or efficient architectures
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
- Executing Machine-Instructions (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
Extraction et insertion de mots binaires La présente description concerne un procédé de traitement de données binaires masquées, mis en oeuvre par un dispositif adapté à effectuer des calculs sur des données binaires (10), comprenant une opération d'extraction et d'insertion d'une première partie (B1_M) d'une première donnée binaire masquée (B_M) dans une deuxième donnée binaire masquée (Z_M), dans laquelle les première et deuxième données binaires masquées restent masquées pendant tout le traitement. Figure pour l'abrégé : Fig. 2
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1911349A FR3101981B1 (fr) | 2019-10-11 | 2019-10-11 | Extraction et insertion de mots binaires |
US17/038,584 US20210109713A1 (en) | 2019-10-11 | 2020-09-30 | Device and method for extraction and insertion of binary words |
CN202011078321.5A CN112650470A (zh) | 2019-10-11 | 2020-10-10 | 用于二进制字的提取和插入的设备和方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1911349 | 2019-10-11 | ||
FR1911349A FR3101981B1 (fr) | 2019-10-11 | 2019-10-11 | Extraction et insertion de mots binaires |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3101981A1 FR3101981A1 (fr) | 2021-04-16 |
FR3101981B1 true FR3101981B1 (fr) | 2021-11-12 |
Family
ID=69810936
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1911349A Active FR3101981B1 (fr) | 2019-10-11 | 2019-10-11 | Extraction et insertion de mots binaires |
Country Status (3)
Country | Link |
---|---|
US (1) | US20210109713A1 (fr) |
CN (1) | CN112650470A (fr) |
FR (1) | FR3101981B1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3101983B1 (fr) | 2019-10-11 | 2021-11-12 | St Microelectronics Grenoble 2 | Détermination d'un bit indicateur |
FR3101980B1 (fr) | 2019-10-11 | 2021-12-10 | St Microelectronics Grenoble 2 | Processeur |
FR3101982B1 (fr) | 2019-10-11 | 2024-03-08 | St Microelectronics Grenoble 2 | Détermination d'un bit indicateur |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1245441A (en) * | 1968-08-27 | 1971-09-08 | Int Computers Ltd | Improvements in or relating to adders operating on variable fields within words |
US3906459A (en) * | 1974-06-03 | 1975-09-16 | Control Data Corp | Binary data manipulation network having multiple function capability for computers |
US20040254966A1 (en) * | 2003-05-16 | 2004-12-16 | Daewoo Educational Foundation | Bit manipulation operation circuit and method in programmable processor |
US7370180B2 (en) * | 2004-03-08 | 2008-05-06 | Arm Limited | Bit field extraction with sign or zero extend |
EP1845442B1 (fr) * | 2006-04-11 | 2011-11-09 | STMicroelectronics Srl | Calcul d'une multiplication modulaire avec un circuit électronique |
CN101355421B (zh) * | 2008-09-25 | 2011-05-11 | 中国电信股份有限公司 | 分组加解密数据长度适配的方法 |
WO2012127572A1 (fr) * | 2011-03-18 | 2012-09-27 | 富士通株式会社 | Procédé, programme et dispositif de traitement de données secrètes |
EP2634953A1 (fr) * | 2012-03-02 | 2013-09-04 | Gemalto SA | Procédé de contre-mesure contre l'analyse de canal latéral pour algorithmes cryptographiques utilisant des opérations booléennes et opérations arithmétiques |
CN107196973B (zh) * | 2017-07-25 | 2019-12-17 | 广东虹勤通讯技术有限公司 | 一种数据加密、解密方法及装置 |
CN107689863A (zh) * | 2017-09-05 | 2018-02-13 | 成都三零嘉微电子有限公司 | 一种算术加法掩码转布尔异或掩码的防护电路 |
-
2019
- 2019-10-11 FR FR1911349A patent/FR3101981B1/fr active Active
-
2020
- 2020-09-30 US US17/038,584 patent/US20210109713A1/en not_active Abandoned
- 2020-10-10 CN CN202011078321.5A patent/CN112650470A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
CN112650470A (zh) | 2021-04-13 |
FR3101981A1 (fr) | 2021-04-16 |
US20210109713A1 (en) | 2021-04-15 |
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