FR2445983A1 - Dispositif pour executer des operations arithmetiques decimales - Google Patents

Dispositif pour executer des operations arithmetiques decimales

Info

Publication number
FR2445983A1
FR2445983A1 FR7931831A FR7931831A FR2445983A1 FR 2445983 A1 FR2445983 A1 FR 2445983A1 FR 7931831 A FR7931831 A FR 7931831A FR 7931831 A FR7931831 A FR 7931831A FR 2445983 A1 FR2445983 A1 FR 2445983A1
Authority
FR
France
Prior art keywords
binary
arithmetic
result
arithmetic operations
logic unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7931831A
Other languages
English (en)
Other versions
FR2445983B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of FR2445983A1 publication Critical patent/FR2445983A1/fr
Application granted granted Critical
Publication of FR2445983B1 publication Critical patent/FR2445983B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4921—Single digit adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)

Abstract

Dispositif pour exécuter des opérations arithmétiques décimales codées en binaire à l'aide d'une unité arithmétique et logique binaire. Le dispositif comprend des moyens 350 et 352 pour recevoir un premier et un second opérande sous forme decimale codée en binaire, une unité arithmétique et logique 354 pour exécuter des opérations d'addition et de soustraction sur lesdits opérandes et produire un résultat sous une forme binaire, un moyen d'indication du type d'opération exécutée 359 et un moyen d'indication de présence de signal de sortie de report 361 et un moyen pour corriger le résultat produit par l'unité 356 en fonction des indications données par lesdits moyens d'indication pour produire un résultat corrigé sous la forme décimale codée en binaire. Application aux systèmes de traitement de données numériques.
FR7931831A 1979-01-03 1979-12-27 Dispositif pour executer des operations arithmetiques decimales Expired FR2445983B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/000,735 US4245328A (en) 1979-01-03 1979-01-03 Binary coded decimal correction apparatus for use in an arithmetic unit of a data processing unit

Publications (2)

Publication Number Publication Date
FR2445983A1 true FR2445983A1 (fr) 1980-08-01
FR2445983B1 FR2445983B1 (fr) 1987-03-27

Family

ID=21692791

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7931831A Expired FR2445983B1 (fr) 1979-01-03 1979-12-27 Dispositif pour executer des operations arithmetiques decimales

Country Status (7)

Country Link
US (1) US4245328A (fr)
JP (1) JPS5917457B2 (fr)
AU (1) AU531028B2 (fr)
CA (1) CA1137229A (fr)
DE (1) DE2952072C2 (fr)
FR (1) FR2445983B1 (fr)
GB (1) GB2039108B (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3172895D1 (en) * 1980-07-10 1985-12-19 Int Computers Ltd Digital adder circuit
US4577282A (en) * 1982-02-22 1986-03-18 Texas Instruments Incorporated Microcomputer system for digital signal processing
US4604695A (en) * 1983-09-30 1986-08-05 Honeywell Information Systems Inc. Nibble and word addressable memory arrangement
US4707799A (en) * 1984-01-30 1987-11-17 Kabushiki Kaisha Toshiba Bit sliced decimal adding/subtracting unit for multi-digit decimal addition and subtraction
US5007010A (en) * 1985-01-31 1991-04-09 Unisys Corp. (Formerly Burroughs Corp.) Fast BCD/binary adder
WO1986004699A1 (fr) * 1985-01-31 1986-08-14 Burroughs Corporation Additionneur binaire/dcb rapide
US7477171B2 (en) * 2007-03-27 2009-01-13 Intel Corporation Binary-to-BCD conversion
US8539015B2 (en) * 2008-08-01 2013-09-17 Hewlett-Packard Development Company, L.P. Performing a binary coded decimal (BCD) calculation

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3045914A (en) * 1958-02-14 1962-07-24 Ibm Arithmetic circuit
US3749899A (en) * 1972-06-15 1973-07-31 Hewlett Packard Co Binary/bcd arithmetic logic unit
FR2248552A1 (fr) * 1973-10-20 1975-05-16 Ver Flugtechnische Werke
US4001567A (en) * 1975-07-21 1977-01-04 National Semiconductor Corporation Bdc corrected adder

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB913605A (en) * 1959-03-24 1962-12-19 Developments Ltd Comp Improvements in or relating to electronic calculating apparatus
JPS549009B1 (fr) * 1971-02-17 1979-04-20
GB1375588A (fr) * 1971-02-22 1974-11-27
US3958112A (en) * 1975-05-09 1976-05-18 Honeywell Information Systems, Inc. Current mode binary/bcd arithmetic array
US4001570A (en) * 1975-06-17 1977-01-04 International Business Machines Corporation Arithmetic unit for a digital data processor
US4125867A (en) * 1976-10-27 1978-11-14 Texas Instruments Incorporated Electronic calculator or microprocessor having a hexadecimal/binary coded decimal arithmetic unit
JPS5520533A (en) * 1978-07-28 1980-02-14 Nec Corp Decimal correction circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3045914A (en) * 1958-02-14 1962-07-24 Ibm Arithmetic circuit
US3749899A (en) * 1972-06-15 1973-07-31 Hewlett Packard Co Binary/bcd arithmetic logic unit
FR2248552A1 (fr) * 1973-10-20 1975-05-16 Ver Flugtechnische Werke
US4001567A (en) * 1975-07-21 1977-01-04 National Semiconductor Corporation Bdc corrected adder

Also Published As

Publication number Publication date
FR2445983B1 (fr) 1987-03-27
AU531028B2 (en) 1983-08-04
CA1137229A (fr) 1982-12-07
GB2039108A (en) 1980-07-30
GB2039108B (en) 1983-09-01
DE2952072A1 (de) 1980-07-17
US4245328A (en) 1981-01-13
DE2952072C2 (de) 1986-09-04
JPS5917457B2 (ja) 1984-04-21
JPS5592944A (en) 1980-07-14
AU5419979A (en) 1980-07-10

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Legal Events

Date Code Title Description
ST Notification of lapse