FR2248552A1 - - Google Patents

Info

Publication number
FR2248552A1
FR2248552A1 FR7435196A FR7435196A FR2248552A1 FR 2248552 A1 FR2248552 A1 FR 2248552A1 FR 7435196 A FR7435196 A FR 7435196A FR 7435196 A FR7435196 A FR 7435196A FR 2248552 A1 FR2248552 A1 FR 2248552A1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7435196A
Other versions
FR2248552B3 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vereinigte Flugtechnische Werke Fokker GmbH
Original Assignee
Vereinigte Flugtechnische Werke Fokker GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vereinigte Flugtechnische Werke Fokker GmbH filed Critical Vereinigte Flugtechnische Werke Fokker GmbH
Publication of FR2248552A1 publication Critical patent/FR2248552A1/fr
Application granted granted Critical
Publication of FR2248552B3 publication Critical patent/FR2248552B3/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924—Digit-parallel adding or subtracting
FR7435196A 1973-10-20 1974-10-18 Expired FR2248552B3 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2352686A DE2352686B2 (de) 1973-10-20 1973-10-20 Dezimaler Parallel-Addierer/Substrahierer

Publications (2)

Publication Number Publication Date
FR2248552A1 true FR2248552A1 (fr) 1975-05-16
FR2248552B3 FR2248552B3 (fr) 1977-07-29

Family

ID=5895971

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7435196A Expired FR2248552B3 (fr) 1973-10-20 1974-10-18

Country Status (6)

Country Link
US (1) US3935438A (fr)
JP (1) JPS5619648B2 (fr)
CH (1) CH577711A5 (fr)
DE (1) DE2352686B2 (fr)
FR (1) FR2248552B3 (fr)
GB (1) GB1484149A (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2445983A1 (fr) * 1979-01-03 1980-08-01 Honeywell Inf Systems Dispositif pour executer des operations arithmetiques decimales
FR2463452A1 (fr) * 1979-08-10 1981-02-20 Sems Dispositif additionneur et soustracteur, comportant au moins un operateur binaire, et operateur decimal comportant un tel dispositif

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5437948B2 (fr) * 1974-05-27 1979-11-17
DE2460897C3 (de) * 1974-12-21 1978-10-05 Olympia Werke Ag, 2940 Wilhelmshaven Parallel-Rechenwerk für Addition und Subtraktion
US4172288A (en) * 1976-03-08 1979-10-23 Motorola, Inc. Binary or BCD adder with precorrected result
DE3172895D1 (en) * 1980-07-10 1985-12-19 Int Computers Ltd Digital adder circuit
JPS59128633A (ja) * 1983-01-13 1984-07-24 Seiko Epson Corp １チツプマイクロコンピユ−タ
US4644489A (en) * 1984-02-10 1987-02-17 Prime Computer, Inc. Multi-format binary coded decimal processor with selective output formatting
JPS6381143U (fr) * 1986-11-14 1988-05-28
US4805131A (en) * 1987-07-09 1989-02-14 Digital Equipment Corporation BCD adder circuit
EP0433315A1 (fr) * 1988-09-09 1991-06-26 Siemens Aktiengesellschaft Circuits d'addition ou de soustraction d'operandes codes selon un code bcd ou dual
US6546411B1 (en) * 1999-12-03 2003-04-08 International Business Machines Corporation High-speed radix 100 parallel adder
DE10085322B4 (de) * 1999-12-23 2006-10-26 Intel Corporation, Santa Clara Schaltungsanordnung, Verfahren und Datenverarbeitungs-Einrichtung zum Durchführen einer Ein-Zyklus-Addition oder -Subtraktion und eines Vergleichs bei einer Arithmetik redundanter Form
US6813628B2 (en) 1999-12-23 2004-11-02 Intel Corporation Method and apparatus for performing equality comparison in redundant form arithmetic
US6826588B2 (en) 1999-12-23 2004-11-30 Intel Corporation Method and apparatus for a fast comparison in redundant form arithmetic
US7299254B2 (en) 2003-11-24 2007-11-20 International Business Machines Corporation Binary coded decimal addition
US9128759B2 (en) * 2012-11-27 2015-09-08 International Business Machines Corporation Decimal multi-precision overflow and tininess detection
JP2015143949A (ja) * 2014-01-31 2015-08-06 富士通株式会社 演算プログラム、演算装置および演算方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL276777A (fr) * 1961-04-04
US3629565A (en) * 1970-02-13 1971-12-21 Ibm Improved decimal adder for directly implementing bcd addition utilizing logic circuitry
US3711693A (en) * 1971-06-30 1973-01-16 Honeywell Inf Systems Modular bcd and binary arithmetic and logical system
US3752394A (en) * 1972-07-31 1973-08-14 Ibm Modular arithmetic and logic unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2445983A1 (fr) * 1979-01-03 1980-08-01 Honeywell Inf Systems Dispositif pour executer des operations arithmetiques decimales
FR2463452A1 (fr) * 1979-08-10 1981-02-20 Sems Dispositif additionneur et soustracteur, comportant au moins un operateur binaire, et operateur decimal comportant un tel dispositif
EP0024232A1 (fr) * 1979-08-10 1981-02-25 Sems - Societe Europeenne De Mini-Informatique Et De Systemes Dispositif additionneur et soustracteur, comportant au moins un opérateur binaire, et opérateur décimal comportant un tel dispositif

Also Published As

Publication number Publication date
US3935438A (en) 1976-01-27
JPS5068749A (fr) 1975-06-09
GB1484149A (en) 1977-08-24
FR2248552B3 (fr) 1977-07-29
DE2352686A1 (de) 1975-04-30
JPS5619648B2 (fr) 1981-05-08
DE2352686B2 (de) 1978-05-11
CH577711A5 (fr) 1976-07-15

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