FR3103584B1 - Procédé de gestion du débogage d’un système sur puce formant par exemple un microcontrôleur, et système sur puce correspondant - Google Patents

Procédé de gestion du débogage d’un système sur puce formant par exemple un microcontrôleur, et système sur puce correspondant Download PDF

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Publication number
FR3103584B1
FR3103584B1 FR1913127A FR1913127A FR3103584B1 FR 3103584 B1 FR3103584 B1 FR 3103584B1 FR 1913127 A FR1913127 A FR 1913127A FR 1913127 A FR1913127 A FR 1913127A FR 3103584 B1 FR3103584 B1 FR 3103584B1
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Prior art keywords
chip
slave resources
debugging
several
master devices
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FR1913127A
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English (en)
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FR3103584A1 (fr
Inventor
Loic Pallardy
Nicolas Anquet
Dragos Davidescu
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STMicroelectronics Rousset SAS
STMicroelectronics Alps SAS
STMicroelectronics Grand Ouest SAS
Original Assignee
STMicroelectronics Rousset SAS
STMicroelectronics Alps SAS
STMicroelectronics Grand Ouest SAS
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Application filed by STMicroelectronics Rousset SAS, STMicroelectronics Alps SAS, STMicroelectronics Grand Ouest SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1913127A priority Critical patent/FR3103584B1/fr
Priority to US16/953,993 priority patent/US11829188B2/en
Priority to CN202011319002.9A priority patent/CN112835845B/zh
Publication of FR3103584A1 publication Critical patent/FR3103584A1/fr
Application granted granted Critical
Publication of FR3103584B1 publication Critical patent/FR3103584B1/fr
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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2247—Verification or detection of system hardware configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G06F11/3656—Software debugging using additional hardware using a specific debug interface
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
    • G06F21/44—Program or device authentication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Software Systems (AREA)
  • Debugging And Monitoring (AREA)
  • Storage Device Security (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

Système sur puce, comprenant plusieurs équipements maîtres comportant plusieurs microprocesseurs, plusieurs ressources esclaves, un circuit d’interconnexion (INTC) couplé entre les équipements maîtres et les ressources esclaves et capable de router des transactions entre des équipements maîtres et des ressources esclaves, et des moyens de traitement (MT) au moins configurés pour permettre à un utilisateur du système sur puce d’implémenter au sein du système sur puce (MCU) au moins un schéma de configuration (SCH) de ce système défini par un ensemble d’informations de configuration utilisé pour définir une assignation d’au moins un équipement maître à certaines au moins des ressources esclaves, et les moyens de traitement étant en outre configurés pour sélectionner l’un au moins des microprocesseurs et autoriser un outil de débogage externe (DBT) à accéder, en vue d’un débogage, uniquement aux ressources esclaves assignées audit au moins un microprocesseur sélectionné. Figure pour l’abrégé : Fig 1
FR1913127A 2019-11-22 2019-11-22 Procédé de gestion du débogage d’un système sur puce formant par exemple un microcontrôleur, et système sur puce correspondant Active FR3103584B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1913127A FR3103584B1 (fr) 2019-11-22 2019-11-22 Procédé de gestion du débogage d’un système sur puce formant par exemple un microcontrôleur, et système sur puce correspondant
US16/953,993 US11829188B2 (en) 2019-11-22 2020-11-20 Method for managing the debugging of a system on chip forming for example a microcontroller, and corresponding system on chip
CN202011319002.9A CN112835845B (zh) 2019-11-22 2020-11-23 用于管理形成例如微控制器的片上系统的调试的方法和对应片上系统

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1913127 2019-11-22
FR1913127A FR3103584B1 (fr) 2019-11-22 2019-11-22 Procédé de gestion du débogage d’un système sur puce formant par exemple un microcontrôleur, et système sur puce correspondant

Publications (2)

Publication Number Publication Date
FR3103584A1 FR3103584A1 (fr) 2021-05-28
FR3103584B1 true FR3103584B1 (fr) 2023-05-05

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FR1913127A Active FR3103584B1 (fr) 2019-11-22 2019-11-22 Procédé de gestion du débogage d’un système sur puce formant par exemple un microcontrôleur, et système sur puce correspondant

Country Status (3)

Country Link
US (1) US11829188B2 (fr)
CN (1) CN112835845B (fr)
FR (1) FR3103584B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3103585B1 (fr) 2019-11-22 2023-04-14 Stmicroelectronics Grand Ouest Sas Procédé de gestion de la configuration d’accès à des périphériques et à leurs ressources associées d’un système sur puce formant par exemple un microcontrôleur, et système sur puce correspondant
FR3103586B1 (fr) 2019-11-22 2023-04-14 St Microelectronics Alps Sas Procédé de gestion du fonctionnement d’un système sur puce formant par exemple un microcontrôleur, et système sur puce correspondant
CN115455397B (zh) * 2022-10-28 2023-03-21 湖北芯擎科技有限公司 一种输入输出接口控制方法及系统

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Also Published As

Publication number Publication date
CN112835845A (zh) 2021-05-25
FR3103584A1 (fr) 2021-05-28
US20210157668A1 (en) 2021-05-27
CN112835845B (zh) 2024-07-19
US11829188B2 (en) 2023-11-28

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