FR3101214B1 - Convertisseur analogique numérique pour circuit logique adiabatique capacitif - Google Patents

Convertisseur analogique numérique pour circuit logique adiabatique capacitif Download PDF

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Publication number
FR3101214B1
FR3101214B1 FR1910403A FR1910403A FR3101214B1 FR 3101214 B1 FR3101214 B1 FR 3101214B1 FR 1910403 A FR1910403 A FR 1910403A FR 1910403 A FR1910403 A FR 1910403A FR 3101214 B1 FR3101214 B1 FR 3101214B1
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FR
France
Prior art keywords
cell
converter
logic circuit
capacitive
analog converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1910403A
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English (en)
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FR3101214A1 (fr
Inventor
Gaël Pillonnet
Hervé Fanet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1910403A priority Critical patent/FR3101214B1/fr
Priority to US17/019,089 priority patent/US11139821B2/en
Publication of FR3101214A1 publication Critical patent/FR3101214A1/fr
Application granted granted Critical
Publication of FR3101214B1 publication Critical patent/FR3101214B1/fr
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
    • H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

Convertisseur analogique numérique pour circuit logique adiabatique capacitif La présente description concerne un convertisseur analogique numérique (100) pour circuit logique adiabatique, comprenant une cellule (Ci) à capacité variable, la cellule (Ci) comportant des première (D) et deuxième (S) bornes principales et au moins une borne de commande (G, R) isolée de ses première (D) et deuxième (S) bornes principales et adaptée à recevoir une tension de commande pour faire varier la capacité entre ses bornes principales entre une valeur basse et une valeur haute, dans lequel : - la cellule (Ci) a sa première borne principale (D) reliée à un noeud d’application d’une tension variable périodique d’alimentation du convertisseur ; - la cellule (Ci) a sa deuxième borne principale (S) reliée à un noeud (outi) de fourniture d’un signal binaire de sortie (Ai) du convertisseur ; et - la cellule (Ci) reçoit sur sa première borne de commande (G) une tension analogique d’entrée (Vana) du convertisseur. Figure pour l'abrégé : Fig. 4
FR1910403A 2019-09-20 2019-09-20 Convertisseur analogique numérique pour circuit logique adiabatique capacitif Active FR3101214B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1910403A FR3101214B1 (fr) 2019-09-20 2019-09-20 Convertisseur analogique numérique pour circuit logique adiabatique capacitif
US17/019,089 US11139821B2 (en) 2019-09-20 2020-09-11 Analog-to-digital converter for a capacitive adiabatic logic circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1910403 2019-09-20
FR1910403A FR3101214B1 (fr) 2019-09-20 2019-09-20 Convertisseur analogique numérique pour circuit logique adiabatique capacitif

Publications (2)

Publication Number Publication Date
FR3101214A1 FR3101214A1 (fr) 2021-03-26
FR3101214B1 true FR3101214B1 (fr) 2023-02-24

Family

ID=69190903

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1910403A Active FR3101214B1 (fr) 2019-09-20 2019-09-20 Convertisseur analogique numérique pour circuit logique adiabatique capacitif

Country Status (2)

Country Link
US (1) US11139821B2 (fr)
FR (1) FR3101214B1 (fr)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6438422B1 (en) * 1998-10-28 2002-08-20 Medtronic, Inc. Power dissipation reduction in medical devices using adiabatic logic
DE10237162A1 (de) * 2002-08-14 2004-02-26 Robert Bosch Gmbh Vorrichtung zur Aufprallsensierung
JP2005123426A (ja) * 2003-10-17 2005-05-12 Matsushita Electric Ind Co Ltd 電圧制御可変容量
US9531384B1 (en) * 2014-12-01 2016-12-27 University Of South Florida Adiabatic dynamic differential logic for differential power analysis resistant secure integrated circuits
FR3045982B1 (fr) * 2015-12-18 2019-06-14 Commissariat A L'energie Atomique Et Aux Energies Alternatives Cellule logique a faible consommation
LU93109B1 (en) * 2016-06-16 2018-01-23 Technische Univ Hamburg Harburg In-situ sensor
FR3067853A1 (fr) 2017-06-15 2018-12-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Condensateur a capacite variable electromecanique a quatre electrodes
FR3069742B1 (fr) 2017-07-25 2019-10-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Cellule logique capacitive
US20190393776A1 (en) * 2018-06-25 2019-12-26 Psemi Corporation Start-up of step-up power converter with switched-capacitor network
FR3088508B1 (fr) * 2018-11-14 2021-07-02 Commissariat Energie Atomique Cellule logique capacitive
US10686367B1 (en) * 2019-03-04 2020-06-16 Psemi Corporation Apparatus and method for efficient shutdown of adiabatic charge pumps

Also Published As

Publication number Publication date
US20210091779A1 (en) 2021-03-25
US11139821B2 (en) 2021-10-05
FR3101214A1 (fr) 2021-03-26

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