FR3059465A1 - MICROELECTRONIC SYSTEM WITH HEAT DISSIPATION - Google Patents

Abstract

The present invention relates to a microelectronic system comprising a support (8) and a microelectronic device comprising at least one component (9) generating heat, a first face (15) of the device being preferably assembled to the support by a bonding interface (12). ), characterized in that the device comprises a thermally conductive layer (10) disposed facing at least a portion of the component (9) and thermal conduction means configured to receive heat from the thermally conductive layer (10) and to drive it to a second face (16) of the device, opposite to the first face (15).

Description

Holder (s): COMMISSIONER FOR ATOMIC ENERGY AND ALTERNATIVE ENERGIES.

Extension request (s)

Agent (s): CABINET HAUTIER.

MICROELECTRONIC SYSTEM WITH HEAT DISSIPATION.

FR 3 059 465 - A1 (57) The present invention relates to a microelectronic system comprising a support (8) and a microelectronic device comprising at least one component (9) generating heat, a first face (15) of the device being preferably assembled to the support by a bonding interface (12), characterized in that the device comprises a thermally conductive layer (10) disposed opposite at least a part of the component (9) and thermal conduction means configured to receive heat from the thermally conductive layer (10) and to conduct it to a second face (16) of the device, opposite to the first face (15).

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FIELD OF THE INVENTION

The present invention generally relates to microelectronic systems. It is intended in particular for systems comprising wireless communication devices.

By microelectronic device or system is meant any type of device produced with microelectronic means, this term being understood to include devices at the nanometric scale. These devices include in particular in addition to purely electronic devices, micromechanical or electromechanical devices (MEMS, NEMS ...) as well as optical or optoelectronic devices (MOEMS / NOEMS ...). A preferred application of the invention is the field of wireless communication devices implementing techniques of emission and / or reception by radiofrequency waves (hereinafter referred to as RF).

TECHNOLOGICAL BACKGROUND

The integration and cost of microelectronic devices are important issues for the miniaturization of the devices incorporating them and for the widening of applications. In the field of so-called RF devices, for example for mobile telephony, techniques have been recently developed for manufacturing these parts on substrates of silicon on insulator type (generally called SOI, acronym for Silicon on Insulator); this type of starting substrate offers increased performance.

To further improve the performance of these RF devices from SOI, it has been proposed to transfer the latter to a receiving substrate, for example glass or metallic foil, for flexible applications. The publication "Application-oriented performance of RF CMOS technologies on flexible substrates" by Justine PHILIPPE et al, IEEE IEDM 2015 illustrates a technique of transfer to flexible substrate of an RF device made from an initial SOI type substrate. This transfer includes a transfer to a temporary support, or handle, then an elimination of the initial support made of silicon until exposing a buried oxide layer (BOX or Buried Oxide layer in English). Finally, this assembly is assembled to a final substrate by fixing the BOX layer on this substrate, via a bonding layer, and the temporary support is eliminated. This technique is called Dual Layer Transfer or DLT (i.e. double transfer layer, two transfers being necessary to achieve the final result on the final substrate).

Very fine and possibly flexible final systems can be obtained. 5 However, heat dissipation difficulties are encountered. In fact, the thermal absorption capacity is low in this type of structure, which is fine and based on materials with low thermal conductivity, and RF devices can cause catastrophic overheating which limit the uses of this technique. For example, a temperature over 125 ° C degrades the performance of a CMOS transistor.

A recommendation of the aforementioned publication is to use a final substrate which is a good thermal conductor, for example a metal sheet, as well as an indium-based bonding layer, also a good heat conductor. However, the performance of this heat dissipation is always reduced.

It is therefore an object of the invention to at least partially overcome the drawbacks of current techniques, by offering an improved microelectronic system as to the efficiency of the dissipation of the heat produced by at least one of its components. This is particularly but not limited to the case for RF components.

SUMMARY OF THE INVENTION

One nonlimiting aspect of the invention relates to a microelectronic system comprising a support and a microelectronic device comprising at least one heat generating component, a first face of the device being disposed on the support.

Advantageously, the device comprises a thermally conductive layer disposed opposite at least a part of the component and thermal conduction means configured to receive heat from the thermally conductive layer and to conduct it to a second face of the device, opposite the first side.

Thus, the calories are removed by the front face of the device which can, for example, include one or more thermal pads. The support is not involved in this heat dissipation path (which does not exclude parallel dissipation by the support). It can therefore be chosen more freely according to the desired application, and not according to heat dissipation constraints. The thermal conduction means can easily be designed and dimensioned according to the thermal power to be dissipated.

Another separable aspect of the present invention relates to a method of manufacturing a microelectronic system in which a thermally conductive layer is formed and means of thermal conduction from this layer to the second face of the device. The thermally conductive layer can in particular be produced before a phase of transfer of the device to the final support and be brought into contact with the bonding interface during transfer. Alternatively, the conductive layer can be produced after transfer of the latter onto the final support.

BRIEF INTRODUCTION OF FIGURES

Other characteristics, objects and advantages of the present invention will appear on reading the detailed description which follows, with reference to the appended drawings, given by way of examples, nonlimiting, and in which:

- Figures 1a and 1b show preliminary manufacturing steps of a system of the invention according to a first embodiment of transfer;

- Figures 2a to 2c show subsequent steps;

- Figure 3 shows a result of the manufacture of the previous figures;

- Figure 4 is a top view corresponding to the embodiment of Figure 3;

- Figures 5a to 5c show another embodiment of the system of the invention, with a DLT transfer technique;

- Figure 6 illustrates the result of the manufacture of Figures 5a to 5c;

- Figure 7 is a top view corresponding to embodiment 30 of the previous figure.

The drawings are given as examples and are not limitative of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily at the scale of practical applications.

DETAILED DESCRIPTION

Before starting a detailed review of embodiments of the invention, there are set out below optional features which may possibly be used in any combination or alternatively:

- an electrically insulating layer is interposed between the component 9 and the thermally conductive layer 10;

- the first face (15) of the device is arranged on the support by means of a bonding interface (12)

the electrically insulating layer is an underground electrically insulating layer 19;

- the thermally conductive layer 10 extends laterally beyond the component 9;

- At least part of the thermal conduction means are offset laterally relative to the component 9;

- The thermal conduction means comprise at least one pad 5; 7 thermally conductive protruding from the second face 16 of the device;

- the at least one pad 5; 7 is in contact with the thermally conductive layer 10;

- the at least one pad 5; 7 is in contact with a surface of the thermally conductive layer 10 laterally offset from the component 9;

- The thermally conductive layer 10 is exposed at the second face 16 and the component 9 is located below the thermally conductive layer 10 relative to the second face 16;

- The device comprises at least one level of interconnection, the thermal conduction means extending along the thickness of the at least one level of interconnection;

each interconnection level comprises at least one electrical interconnection element 2, the thermal conduction means comprising in each level at least one electrical interconnection element 2, said electrical interconnection elements 2 included in the conduction means being in continuity of thermal conduction between them and with the thermally conductive layer 10;

- said electrical interconnection elements 2 included in the conduction means are in thermal continuity with the at least one pad 7;

- said electrical interconnection elements 2 included in the conduction means are offset laterally from component 9;

- the thermally conductive layer 10 is in contact with the bonding interface 12;

- component 9 comprises at least one electronic chip for transmitting and / or receiving radiofrequency waves

- component 9 comprises at least one CMOS transistor;

- The thermally conductive layer 10 is electrically insulating;

- The thermally conductive layer 10 is passive to radio frequency waves, and / or has a loss angle such that tgô <10 '¹;

- the thermally conductive layer (10) comprises at least one of the following materials: aluminum nitride, nanocrystalline diamond, porous silicon.

The system according to the invention may comprise a box containing at least said support (8) and said microelectronic device, said box being in thermal continuity with the thermal conduction means.

It is specified that, in the context of the present invention, the term "on" or "above" does not necessarily mean "in contact with". Thus, for example, the deposition of a layer on another layer, does not necessarily mean that the two layers are directly in contact with each other but it does mean that one of the layers at least partially covers the another by being either directly in contact with it, or by being separated from it by a film, yet another layer or another element. A layer can also be composed of several sublayers of the same material or of different materials.

It is specified that in the context of the present invention, the thickness of a layer or of a substrate is measured in a direction perpendicular to the surface along which this layer or this substrate has its maximum extension.

The use of the singular for certain elements of the invention does not necessarily mean that a given element is present uniquely in the invention. The word "one" or "one" therefore does not mean exclusively "one" or "one" respectively, unless otherwise provided.

îo Certain parts of the device of the invention can have an electrical function. Some are used for electrical conduction properties and by electrically conductive or equivalent is meant elements formed from at least one material having sufficient conductivity, in the application, to perform the desired function. Other parts, on the contrary, are used for electrical insulation properties and any material having sufficient resistivity to achieve this insulation are concerned and are in particular called dielectrics.

The term thermal continuity means the ability of organs in contact with each other to conduct heat efficiently in the desired application, in particular to limit the heating of the microelectronic device below a value acceptable for its proper functioning. A level of thermal conductivity greater than 10W / m / K and preferably greater than 50W / m / K is acceptable for the material or materials involved in this thermal continuity and in general for the level of thermal conductivity of the materials chosen for the thermally conductive parts of the invention.

The thermally conductive layer is preferably dielectric and / or with low RF losses. In particular, its electrical resistivity can be greater than 10 ³ Om and / or its RF losses with a loss angle such as tgô <10 ' ¹ and preferably <10' ² .

The thermally conductive layer may be made of several sublayers of the same material or of different materials. The term layer does not mean that such a part is "full plate". Indeed, particularly for the thermally conductive layer, this advantageously does not extend over the entire plane of the system, but only over a part of it, in particular facing the component or components whose heating is at control.

A first embodiment of the invention is illustrated in Figures 1a,

1b, 2a to 2c, 3 and 4. It is part of a first possibility of transfer of the microelectronic device from an initial support 14. The other figures are part of another possibility of transfer.

According to the first embodiment, a microelectronic device is initially secured to an initial support 14 as in the case of FIG. 1a. It is possible, in the context of the present invention, to implement techniques relating to semiconductor substrates, and in particular so-called SOI (for Silicon On Insulator) substrates comprising a sublayer of semiconductor material, typically silicon , an intermediate layer of electrical insulator, typically silicon dioxide, and a layer of monocrystalline silicon from which portions of the microelectronic device can be formed. This technology can be used to produce the support 14. In the context of the manufacture of the microelectronic device, the electrically insulating layer is advantageously left, represented in the example by a buried insulating layer 19, which may for example be in silicon dioxide. In the case of the latter material, layer 19 is generally called BOX for Buried Oxide layer, being a buried oxide layer.

Above the layers 14, 19, the microelectronic device is formed.

The invention can be applied to different types of devices, as indicated above. In the example shown, an application is the production of a radiofrequency transmitter device using, above the buried insulating layer 19, a functional stack forming an active part 1. According to one possibility of the invention, this stack comprises a part located near the support 14 and the buried layer 19, producing a start of line (in English Front End Of Line, FEOL) at the level of which one or more components are formed 9. As a preferred example, at least one of its components uses CMOS technology and implements, for example, one or more transistors, such as MOSFETs, and in particular LDMOSs.

The active part 1 then comprises one or more electrical interconnection levels making it possible to produce the appropriate electrical connection networks in conjunction with the start of line layer, for example for electrically connecting the source, drain and transistor gate areas. Generally speaking, this connection part is called in English Back End Of Line, BEOL, because it forms a line back part. An interconnection level comprises at least one electrical interconnection element 2, in the form of a track extending laterally in the thickness of the interconnection level and an electrical connection 3 traversing the thickness of a layer insulating so as to connect the electrical interconnection element 2 to another element located in superposition with the first. Typically, copper is a material usually used to make the elements 2 and the connections 3.

In order to electrically isolate this stacked assembly, the technology

CMOS also generally employs an insulating layer 20 covering said assembly. Layer 20 can be made of at least one layer of nitride or oxide of semiconductor material, for example silicon dioxide. Of course, the invention can be implemented by leaving this example, in particular with techniques which do not resort to the use of layer 19 and / or layer 20. In addition, the examples given of materials, in particular for layer 19, are not limiting. In particular, unlike conventional CMOS on SOI techniques, a material that is both good electrical insulator and good thermal conductor can be used for layer 19.

It is explained further on in the description that a thermally conductive layer 10 of the invention can be produced from nanocrystalline diamond. It can also be an alternative to silicon dioxide for layer 19 and reference is made to the description for layer 10 with regard to an example of manufacture of this part. It is also therefore possible, if appropriate, to combine the thermal conduction function of layer 10 and the electrical insulation function of layer 19 into a single layer having these two functions, layer 10 then replacing layer 19.

In general, the first face 15 of the device is understood to mean the face of the latter, above the BEOL levels, and in the example shown, the upper surface of the insulating layer 20. Furthermore, in a manner general, the second face 16 of the device is understood to mean the face of the latter located below the FEOL level or levels, and in the example shown, the lower surface of the buried insulating layer 19.

As also shown in FIG. 1a, a contact resumption element 4 can be electrically connected to the electrical interconnection elements of the active part 1 through the insulating layer 20.

According to the transfer mode illustrated from FIG. 1a, a second support, support 8, is integral with the assembly previously described by the first face 15 of the device, and advantageously via a bonding interface 12 well that the use of such an interface is not absolutely necessary in the invention. One can for example use a polymer film laminated above the surface 15 to produce the interface 12. It is the support 8 which is intended to carry the microelectronic device definitively. Its thickness and its material will depend on the desired application. It is understood that it suffices to bring the final support 8 opposite the initial support 14 so as to effect the transfer of the device. It is therefore a single layer transfer technique known as SLT, acronym for Single Layer Transfer.

According to this technique, the support 14 is eliminated by using the buried insulating layer 19 as a stop layer for removal. The latter can be achieved by thinning, for example with a mechanical or mechanochemical polishing technique. In particular, a discontinuity in the polishing torque is detected at the start of the attack due to layer 19 and the thinning is stopped at this stage or after a predefined time from the start of attack on layer 19. The result of this operation is illustrated in Figure 1b, the assembly having been returned at the same time. For example, the thickness of layer 19 is ultimately less than 200 nm, or even 100 nm and possibly 50 nm.

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Rather than making the necessary contact recoveries at this stage to access the active part of the device, this embodiment of the present invention previously forms a thermally conductive layer 10, above the second face 16. This formation can be done by a deposit, preferably a full plate, above the layer 19. It is possible in particular to use a physical vapor deposition technique called PVD, for example for depositing a layer 10 made of AIN. The latter material is in fact a good thermal conductor while exhibiting properties of electrical insulation and passivity to radiofrequency waves which are advantageous in certain applications of the present invention.

The choice of these materials is not, however, limiting.

According to another possibility, in fact, a synthetic diamond structure is used, advantageously in film, and preferably nanocrystalline diamond (called NCD). The formation of such a layer can be achieved by chemical vapor deposition CVD. For example, one can use a reactor using chemical vapor deposition optimized by microwave plasma, carrying the acronym MPCVD. According to another possibility, the layer 10 can be made of porous semiconductor material, in particular porous silicon. This layer can then be obtained directly from the initial substrate while preserving a sufficient thickness of the latter during the thinning phase, so as to preserve a layer of silicon above the buried layer 19.

In general, by way of example, the thickness of the layer 10 can be less than 2 μm and / or greater than 200 nm. The layer 10 is configured to capture at least part of the heat given off by at least one component.

An example of the result obtained is provided in Figure 2a. It will be noted that the layer 10 is in this case immediately above the layer 19, without an intermediate layer. The layer 19 is itself advantageously directly above the component or components 9.

It is then possible to provide access to the upper level of the active part 1, so as to connect the device to the outside, on the first metallization level of the BEOL according to this embodiment by means of a stud. electrical connection 6. To do this, in figure

2b, an etching was carried out after masking the parts to be preserved, so as to open the layers 10 and 19 to expose at least one electrical interconnection element 2 of the first level of the active part 1. Typically, the thicknesses to be etched are weak and can use a single lithography step. The etching itself can be of the "multistep" type in that it comprises a plurality of etching sub-steps each adapted to the material of one of the layers to be opened.

The opening 11 thus formed allows contact recovery, for example with a contact recovery element 5, in particular of metallic type.

Preferably simultaneously, to form a thermal connection pad 7, a resumption of thermal contact 13 is also carried out. For example, these two parts 5, 13 come from a deposit, preferably PVD, with a layer of a barrier material, for example made of titanium or titanium nitride, and for example of a thickness between 25 and 50 nm, and an upper conductive layer, for example of 1.2 μm, and for example of Al Cu alloy. The deposition of these parts can be made full plate and followed by an engraving so as to delimit the elements 5 and 13. The result of this step is illustrated in Figure 2c. Although it is advantageous to simultaneously make a thermal connection of the layer 10 with conduction means (comprising the various parts which made it possible to produce the pad 7) and the electrical connection of the active part with a pad 6 with an electrical function, making the thermal connection may suffice in the context of the present invention.

It is then possible to produce stud bodies 6, 7 surmounting the contact recoveries 5, 13. For example, the studs are produced on the basis of a thin bonding layer, which can be deposited by PVD, a step of lithography then the deposition of two layers respectively of copper Cu and of Sn Ag alloy. The whole is finalized by the removal of the bonding layer at the places where it is still exposed. The assembly associating body of pad 6.7 and bonding layer and / or contact recovery layer 5 forms the thermal pad. Of course, in certain embodiments the bonding and / or contact recovery layer is not necessary. These various potential elements of construction of the stud form an integral part thereof. The term pad means a member accessible from outside the system of the invention, in particular for being connected with a heat sink or an electrical connection element, without limitation of shape.

Finally, an example of the structure that can be obtained is illustrated in Figure 3.

The thermal continuity between the pad 7 and the layer 10 will be noted so that conduction means (or systems) are formed by the pad 7 including any layer underlying the body of the pad which has enabled it to be produced, it will be noted that in this embodiment, except at the level of the opening 11 having allowed electrical access to the active part 1, the entire layer 10 has been preserved on the surface of the device. This case is not limitative of the invention. However, to ensure efficient transmission of heat from the component 9 to the outside, at least part of the surface of the component 9 is located opposite at least part of the layer 10. By a situation in as the projection of these layers, in the direction of the thickness of the substrate, overlaps at least partially. Thus, at least part of the layer 10 is located in line with at least part of the surface of the component 9 which it surmounts. Advantageously, the entire surface of the component 9 is surmounted by the layer 10.

It will also be noted that, in the case of FIG. 3, the layer 10 extends laterally relative to the component 9 (in other words extends beyond the component) so as to allow the offset of the stud 7 with which the layer 10 in thermal continuity. Thus, in the case of FIG. 3, the stud 7 (or any other means of thermal conduction in contact with the layer 10) is kept away from the component 9 and is not located opposite it. This is also the case for the electrical connection pad 6. Indeed, this prevents the component 9 from being overcome by disturbing elements, for example likely to be non-passive to radio frequencies; this situation is particularly advantageous in the case where the component 9 is or comprises a radiofrequency transmitter. In this way, not only does the layer 10 serve as a device for recovering thermal energy from the component 9, but also ensures the lateral offset between the component 9 and the thermal conduction means which will allow '' dissipate the heat thus recovered to the outside.

FIG. 4 shows a top view of the result thus obtained with a simplified illustration in which a single stud 7 has been produced. It is understood that a plurality of thermal conduction pads can be formed in the thermal continuity of the layer 10. It is the same for the pads 6 intended for the electrical connection.

Another embodiment of the invention can implement a technique for transferring the microelectronic device by means of two transfer layers. This technique, often called by its acronym DLT (for Dual Transfer Layer) is implemented in the case of FIGS. 5a to 5c, 6 and 7.

As before, a microelectronic device is formed above an initial substrate 14, the device comprising a first face 15 here produced by the upper face of an insulating layer 20 and a second face 16 here produced by the lower face of a layer electrically insulating buried 19. However, this assembly is preliminary connected to a handle 18, for example of semiconductor material via a bonding interface 17 which may be of the same type as the bonding interface 12 exposed with reference to the previous embodiment.

In FIG. 5b, the substrate 14 was removed, for example by using a technique as set out for the previous embodiment. In addition, a thermally conductive layer 10 has been formed. Likewise, reference may be made to the examples given for the first embodiment with regard to the formation of this layer.

Then, by the second face 16 of the device, the final support 8 is reported, by means of a bonding interface 12.

The handle 18 and the bonding interface 17 are then eliminated so as to leave only the support 8 as a substrate and to make the first face 15 of the device visible, as shown in FIG. 5c.

In this case, the resumption of electrical contact takes place via the element 4 previously described with reference to the usual CMOS technology. In particular, a stud body 6 can be formed above the contact resumption 4, the latter being connected to the interconnection level of the BEOL of the active part 1 of the microelectronic device.

For heat dissipation, arrangements are made for layer 10 to be close to one or more electrical interconnection elements 2 so as to establish a heat dissipation circuit through these elements from layer 10. Thus, in in the case of FIG. 6, an element 2 of the first interconnection level is opposite a part of the layer 10. In addition, this element 2 is itself thermally connected to elements 2 of the other levels of interconnection so as to establish thermal conduction through all of the interconnection levels up to the distal end of these levels, which is in the case of the figures, in contact with the underside of the insulating layer 20. The thermal continuity between the elements 2 of different levels takes place by electrical connections 3 which connect them.

The assembly forms conduction means which will allow a path of heat towards the outside of the formed system.

Between the step in FIG. 5c and in FIG. 6, an opening of the layer 20 was made so as to access this thermal continuity path. This opening can be operated by etching after masking the areas to be preserved. It is then possible to manufacture a contact resumption 13, for example with a technique similar to that developed for the first embodiment. Similarly, a block body 7 then overcomes the contact recovery 13 which can be manufactured as in the first example.

As indicated above for the first embodiment, it is advantageous to offset the heat conduction means, and generally all of the means capable of disturbing the operation of the component 9, so that the latter is not located opposite the either of these means. This principle is preferably applied to the second embodiment as illustrated in FIG. 6 as well as in FIG. 7 in top view. Thus, the elements 2 and the connections 3 used for thermal conduction through the active part 1 are offset laterally relative to the component 2 and / or the stud (s) 6, 7 are themselves also located in lateral offset from the component 9 so as not to be in front of the latter.

It will be noted that in this embodiment, the pad 7 may as well have an electrical connection function as a heat dissipation function.

The conduction means thermally connecting the thermally conductive layer 10 to the outside can be brought into contact with other heat dissipation devices. For example, parts of a compact housing of these pads can serve as heatsinks. The studs themselves can be used as thermal radiators.

Claims (21)

1. Microelectronic system comprising a support (8) and a microelectronic device comprising at least one generator component (9) 5 heat, a first face (15) of the device being disposed on the support characterized in that the device comprises a thermally conductive layer (10) disposed opposite at least a portion of the component (9) and conduction means thermally configured to receive heat from the thermally conductive layer (10) and to conduct it to a second face (16) of the device, opposite the first face (15). 2. System according to the preceding claim, in which the first face (15) of the device is arranged on the support by means of a bonding interface (12). 3. System according to one of the preceding claims, comprising an electrically insulating layer interposed between the component (9) and the thermally conductive layer (10). 4. System according to the preceding claim, in which the electrically insulating layer is an underground electrically insulating layer (19). 5. System according to one of the preceding claims, in which the thermally conductive layer (10) extends laterally beyond the component (9). 6. System according to the preceding claim, wherein at least a portion of the thermal conduction means is offset laterally relative to the component (9). 25 7. System according to one of the preceding claims, in which the thermal conduction means comprise at least one thermally conductive stud (7) projecting from the second face (16) of the device. 8. System according to the preceding claim, wherein the at least one stud (7) is in contact with the thermally conductive layer (10). 30 9. System according to the preceding claim, wherein the at least one stud (7) is in contact with a surface of the thermally conductive layer (10) offset laterally from the component (9). 10. System according to one of the two preceding claims, in which the thermally conductive layer (10) is exposed at the second face (16) and the component (9) is located below the thermally conductive layer (10 ) relative to the second face (16). 5 11. System according to one of claims 1 to 7, in which the device comprises at least one interconnection level, the heat conduction means extending along the thickness of the at least one interconnection level. 12. System according to the preceding claim, in which each interconnection level comprises at least one electrical interconnection element (2), the thermal conduction means comprising in each level at least one electrical interconnection element (2), said electrical interconnection elements (2) included in the conduction means being in continuity of thermal conduction between them and with the thermal layer 15 conductive (10). 13. System according to claim 7 and the preceding claim in combination, wherein said electrical interconnection elements (2) included in the conduction means are in thermal continuity with the at least one stud (7). 20 14. System according to one of the two preceding claims, in which said electrical interconnection elements (2) included in the conduction means are offset laterally from the component (9). 15. System according to one of claims 11 to 14 in combination with claim 2, wherein the thermally conductive layer (10) 25 is in contact with the bonding interface (12). 16. System according to one of the preceding claims, in which the component (9) comprises at least one electronic chip for transmitting and / or receiving radiofrequency waves. 17. System according to one of the preceding claims, in which the component (9) comprises at least one CMOS transistor. 18. System according to one of the preceding claims, in which the thermally conductive layer (10) is electrically insulating. 19. System according to one of the preceding claims, in which the thermally conductive layer (10) has an angle of losses such that tgô <10 ' ¹ . 20. System according to one of the preceding claims, in which the thermally conductive layer (10) comprises at least one of the following materials: aluminum nitride, nanocrystalline diamond, porous silicon. 21. System according to one of the preceding claims, comprising a box containing at least said support (8) and said microelectronic device, said box being in thermal continuity with the thermal conduction means. 1/5