US20200357765A1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- US20200357765A1 US20200357765A1 US16/404,830 US201916404830A US2020357765A1 US 20200357765 A1 US20200357765 A1 US 20200357765A1 US 201916404830 A US201916404830 A US 201916404830A US 2020357765 A1 US2020357765 A1 US 2020357765A1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 99
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 239000004020 conductor Substances 0.000 claims abstract description 46
- 230000000149 penetrating effect Effects 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 151
- 230000008569 process Effects 0.000 claims description 64
- 239000007769 metal material Substances 0.000 claims description 32
- 238000000151 deposition Methods 0.000 claims description 27
- 230000004888 barrier function Effects 0.000 claims description 26
- 230000008021 deposition Effects 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 238000005530 etching Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 239000003870 refractory metal Substances 0.000 description 9
- 238000004377 microelectronic Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000004380 ashing Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- -1 silicon nitrides Chemical class 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 238000000347 anisotropic wet etching Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Definitions
- the present disclosure relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a stacked integrated circuit device.
- 3D integrated circuits are stacked three dimensional integrated circuits.
- Some areas where 3D integrated circuits are a suitable consideration include stacking of two or more chips that are fabricated using different fabrication processes, or stacking of chips that are fabricated using the same fabrication processes to reduce the footprint of the integrated circuit apparatus.
- One aspect of the present disclosure provides a method of manufacturing a semiconductor device.
- the method includes steps of providing a first wafer comprising a first substrate, a first inter-layer dielectric (ILD) layer disposed on a first front surface of the first substrate, and a plurality of first conductors disposed in the first ILD layer; forming a first interconnect structure penetrating through the first substrate and into the first ILD layer and contacting one of the plurality of first conductors; forming a bonding dielectric on a first back surface opposite to the first front surface and on the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer comprises a second substrate, a second ILD layer disposed on a second front surface of the second substrate, and a plurality of second conductors disposed in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; and forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting
- the forming of the first interconnect structure includes steps of forming a first opening penetrating through the first substrate and into the first ILD layer to expose the one of the plurality of first conductors; and depositing a first metallic material in the first opening.
- the forming of the second interconnect structure includes steps of forming a first trench penetrating through the second substrate, the second ILD layer and the bonding dielectric to expose the first metallic material; forming a second trench penetrating through the second substrate and into the second ILD layer to expose one of the second conductors; forming a recess communicating with the first trench and the second trench; and depositing a second metallic layer in the first trench, the second trench and recess.
- the method further includes steps of depositing a first insulating layer along the first back surface and the first opening before the deposition of the first metallic material; removing a portion of the first insulating layer to expose the one of the first conductors; depositing a second insulating layer along a second back surface of the second substrate, the recess, the first trench, and the second trench before the deposition of the second metallic material; and removing portions of the second insulating layer to expose the one of the second conductors and the first metallic material.
- the method further includes steps of depositing a first barrier layer on the first insulator and the one of the first conductors before the deposition of the first metallic material; and depositing a second barrier layer on the second insulating layer and the one of the second metallic contacts before the deposition of the second metallic material.
- the method further includes steps of performing a first planarizing process to remove portions of the first metallic material and the first barrier layer that are above the first insulating layer; and performing a second planarizing process to remove portions of the second metallic material and the second barrier layer that are above the second insulating layer.
- the forming of the first interconnect structure further includes steps of forming a second opening communicating with the first opening in the first substrate before the deposition of the first metallic material; and depositing the first metallic material in the second opening.
- the second opening has a substantially consistent diameter
- the first opening has a diameter that gradually decreases at positions of increasing distance from the first back surface, wherein the diameter of the first opening is less than the diameter of the second opening.
- the first opening has a central line, which is offset from a central line of the second opening.
- the method further includes steps of depositing a passivation layer over the second back surface, and forming an external contact in contact with the second interconnect structure.
- the method further includes steps of providing a carrier wafer before providing the first wafer; forming a forming a bonding layer on the carrier wafer; and bonding the first wafer on the carrier wafer, wherein the first ILD layer is in contact with the bonding layer.
- the method further includes a step of thinning the first substrate after bonding the first wafer to the carrier wafer.
- the method further includes a step of grinding the carrier wafer after the forming of the second metallic structure.
- the first interconnect structure includes a mesa, and a protrusion extending from the mesa and contacting the first conductor.
- the second interconnect structure includes a base, a first leg extending from the base and contacting the one of the second conductors, and a second leg extending from the base and contacting the first interconnect structure.
- FIG. 1 is a cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure.
- FIG. 2 is a flow diagram illustrating a method of manufacturing a package device in accordance with some embodiments of the present disclosure.
- FIGS. 3 to 28 illustrate cross-sectional views of intermediate stages in the formation of a semiconductor structure in accordance with some embodiments of the present disclosure.
- first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
- FIG. 1 is a cross-sectional view of a semiconductor device 10 in accordance with some embodiments of the present disclosure.
- the semiconductor device 10 includes a first wafer 20 and a second wafer 30 stacked and bonded to a top of the first wafer 20 .
- the first wafer 20 and the second wafer 30 may be fabricated using the same fabrication process.
- the first wafer 20 and the second wafer 30 may form a memory stack.
- the first wafer 20 and the second wafer 30 may be fabricated using different fabrication processes.
- one of the first wafer 20 and the second wafer 30 may be a memory device and the other of the first wafer 20 and the second wafer 30 may be a processor, an image sensor or an application-specific integrated circuit (ASIC) device.
- ASIC application-specific integrated circuit
- the first wafer 20 and the second wafer 30 may be bonded using a dielectric-to-dielectric bonding process.
- the second wafer 30 is bonded on the first wafer 20 by an oxide-to-oxide bonding process.
- a back surface 214 of the first wafer 20 may be coated with one or more bonding dielectrics 44 including oxide to provide a high-quality bonding interface.
- the first wafer 20 may be stacked and bonded on a carrier wafer 42 by a dielectric-to-dielectric bonding process, wherein a bonding layer 40 may be sandwiched between the first wafer 20 and the carrier wafer 42 to provide a high-quality bonding interface.
- the first wafer 20 includes a first substrate 210 having a front surface 212 opposite to the back surface 214 , a first inter-layer dielectric (ILD) layer 220 disposed on the front surface 212 , and a plurality of conductors 230 disposed in the first ILD layer 220 .
- the first substrate 210 may further include various layers that are not separately depicted and that combine to form various microelectronic elements that may include transistors, resistors, diodes, capacitors, inductors, fuses, other suitable elements, or combinations thereof.
- the various layers may include high-k dielectric layers, gate layers, interfacial layers, diffusion/barrier layers, dielectric layers, conductive layers, other suitable layers, or combinations thereof.
- the various layers of the first substrate 210 may also include various doped regions, isolation features, other features, or combinations thereof. Moreover, such microelectronic elements may interconnect with one another to form a portion of the first substrate 210 , such as a logic device, a memory device, a radio frequency device, an input/output device, a system-on-chip device, other suitable type of device, or combinations thereof.
- the first ILD layer 220 covers the microelectronic elements, the doped regions and the isolation features.
- the first wafer 20 further includes at least one first interconnect structure 292 penetrating through the first substrate 210 and into the first ILD layer 220 and contacting one of the first conductors 230 .
- the first interconnect structure 292 includes a mesa 2920 and a protrusion 2922 extending from the mesa 2920 and contacting the one of the first conductors 230 .
- the first interconnect structure 292 includes metal such as copper or aluminum.
- the first wafer 20 further includes a first insulating layer 270 extending along the first back surface 214 and attached to sidewalls 2921 , 2923 of the mesa 2920 and the protrusion 2922 .
- the first insulating layer 270 is formed to prevent diffusion spikes causing shorts across the first substrate 210 and the first interconnect structure 292 .
- the first wafer 20 may further include a first barrier layer 280 sandwiched between the first interconnect structure 292 and the first insulating layer 270 and between the first interconnect structure 292 and the first conductor 230 .
- the first barrier layer 280 acts as a glue layer.
- refractory metals, refractory metal nitrides, refractory metal silicon nitrides and combinations thereof are typically used for the first barrier layer 280 .
- the first barrier layer 280 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium silicon nitride (TiSN), tantalum silicon nitride (TaSiN), or the like.
- the second wafer 30 includes a second substrate 310 , a second ILD layer 320 disposed on a front surface 312 of the second substrate 310 , and a plurality of second conductors 330 disposed in the second ILD layer 320 .
- the second substrate 310 may further include various layers that are not separately depicted and that combine to form various microelectronic elements, doped regions and isolation features mentioned above.
- the second ILD layer 320 covers the microelectronic elements, the doped regions and the isolation features.
- the second wafer 30 further includes at least one second interconnect structure 392 coupled to one of the first conductors 230 to provide an external electrical connection and coupled to one of the second conductors 330 to provide an internal connection.
- the second interconnect structure 392 includes a base 3920 , a first leg 3922 extending from the base 3920 and contacting the second conductor 330 , and a second leg 3924 extending from the base 3920 and contacting the first interconnect structure 292 .
- the base 3920 , the first leg 3922 and the second leg 3924 are integrated and formed of material including metal such as copper or aluminum.
- the second wafer 30 may further include a second insulator 370 disposed on a back surface 314 opposite the front surface 312 of the second substrate 310 and on sidewalls 3921 , 3923 and 3925 of the base 3920 , the first leg 3922 and the second leg 3924 , respectively.
- the second insulating layer 370 is formed to prevent diffusion spikes causing shorts across the second substrate 310 and the second interconnect structure 392 .
- the second wafer 30 may further include a second diffusion layer 380 disposed between the second interconnect structure 392 and the second insulating layer 370 and between the second interconnect structure 392 and the second conductor 330 .
- the semiconductor device 10 further includes a passivation layer 46 disposed on the second insulating layer 370 and at least one external contact 48 disposed on the second interconnect structure 292 .
- the passivation layer 46 is used to protect the second wafer 30 from the environment.
- FIG. 2 is a flow diagram illustrating a method 50 of manufacturing a semiconductor device 10 in accordance with some embodiments of the present disclosure.
- FIGS. 3 to 28 are schematic diagrams illustrating various fabrication stages constructed according to the method 50 for manufacturing the semiconductor device 10 in accordance with some embodiments of the present disclosure. The stages shown in FIGS. 3 to 28 are also illustrated schematically in the flow diagram in FIG. 2 . In the subsequent discussion, the fabrication stages shown in FIGS. 3 to 28 are discussed in reference to the process steps shown in FIG. 2 .
- a carrier wafer 42 is provided according to a step 502 in FIG. 2 .
- the carrier wafer 42 may be a bare silicon wafer without any electrical circuitry disposed thereon.
- the carrier wafer 42 includes a first surface 422 and a second surface 424 opposite to the first surface 422 .
- the carrier wafer 42 has a thickness T 1 , which may be, for example, greater than 750 ⁇ m, such as 775 ⁇ m.
- a bonding layer 40 is formed on the first surface 422 according to a step 504 in FIG. 2 .
- the bonding layer 40 includes oxide, such as silicon oxide.
- the bonding layer 40 may be formed by a thermal oxidation process or a chemical vapor deposition (CVD) process.
- a first wafer 20 is provided and bonded on the carrier wafer 42 according to a step 506 in FIG. 2 .
- the first wafer 20 is bonded on the carrier wafer 42 by a dielectric-to-dielectric bonding process, such as an oxide fusion bonding process.
- the first wafer 20 includes a first substrate 210 , a first inter layer dielectric (ILD) layer 220 disposed on a first front surface 212 of the first substrate 210 , and a plurality of first conductors 230 disposed in the ILD layer 220 .
- ILD inter layer dielectric
- the first substrate 210 may include, for example, doped or undoped bulk silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate.
- the first substrate 210 may further include various layers that are not separately depicted and that combine to form various microelectronic elements, doped regions and isolation features, wherein the first ILD layer 220 is disposed over the microelectronic elements, the doped regions and the isolation features.
- a thinning process may be performed to thin the first wafer 20 according to a step 508 in FIG. 2 . Accordingly, a first back surface 214 ′ is exposed. In some embodiments, the thinning process is performed on an initial back surface 214 (shown in FIGS. 4 and 5 ), opposite to the front surface 212 , to thin the first substrate 210 . In FIG. 6 , the dotted line marks an original thickness of the first substrate 210 .
- the thinning process may be implemented using suitable techniques such as a grinding process, a polishing process and/or a chemical etching process.
- a first opening 240 is formed to expose one of the first contacts 230 according to a step 510 in FIG. 2 .
- the first opening 240 is formed by coating a first photoresist pattern 62 on the first back surface 214 ′ and performing a first etching process to remove portions of the first substrate 210 and the first ILD layer 220 .
- the first photoresist pattern 62 may be formed by performing an exposure process and a develop process on a first photoresist material fully covering the first back surface 214 ′. In some embodiments, a portion of the first back surface 214 ′ to be etched is exposed through the first photoresist pattern 62 .
- the first opening 240 stops at one of the first contacts 230 .
- the first etch process may utilize multiple etchants to etch the first substrate 210 and the first ILD layer 220 , wherein the etchants are selected based on the materials being etched.
- the first substrate 210 and the first ILD layer 220 may be etched using a dry etching process, an anisotropic wet etching process, or any other suitable anisotropic etching process.
- the first photoresist pattern 62 is removed, for example, by an ashing process or a wet strip process, wherein the wet strip process may chemically alter the first photoresist pattern 62 so that it no longer adheres to the first substrate 210 .
- a second opening 250 communicating with the first opening 240 is formed according to a step 512 in FIG. 2 .
- the second opening 250 is formed by coating a second photoresist pattern 64 on the first back surface 214 ′ and performing a second etching process to remove a portion of the first substrate 210 .
- the first opening 240 and a portion of the first back surface 214 ′ are exposed through the second photoresist pattern 64 .
- the first opening 240 and the second opening 250 constitute a stepped hole 260 .
- the first opening 240 has a diameter D 1 that gradually decreases at positions of increasing distance from the first back surface 214 ′.
- the second opening 250 has a substantially consistent diameter D 2 , which is greater than the diameter D 1 of the first opening 240 .
- the first opening 240 has a central line 242
- the second opening 250 has a central line 252 that is offset from the central line 242 .
- a first insulating layer 270 is deposited on the first back surface 214 ′ and in the stepped hole 260 according to a step 514 in FIG. 2 .
- the first conductor 230 exposed through the stepped hole 260 is covered by the first insulating layer 270 .
- the first insulating layer 270 is a substantially conformal layer.
- the first insulating layer 270 includes oxide such as silicon oxide.
- the first insulating layer 270 may be formed by a high-density plasma CVD process.
- a portion of the first insulating layer 270 is removed to expose the first conductor 230 , as shown in FIG. 12 .
- the portion of the first insulating layer 270 is removed by a suitable process, such as an etching process.
- a first barrier layer 280 is optionally deposited on the first insulating layer 270 and the first conductor 230 according to a step 516 in FIG. 2 .
- the first barrier layer 280 is a substantially conformal layer.
- the first barrier layer 280 may be a single-layered structure including refractory metals, refractory metal nitrides or refractory metal silicon nitrides.
- the first barrier layer 280 may have a multi-layered structure including one or more refractory metals, refractory metal nitrides or refractory metal silicon nitrides.
- the first barrier layer 280 is formed using a physical vapor deposition (PVD) process or an atomic layer deposition process, for example.
- PVD physical vapor deposition
- a first metallic material 290 is deposited on the first barrier layer 280 according to a step 518 in FIG. 2 .
- the first metallic material 290 has a thickness sufficient to fill the stepped hole 260 .
- the first metallic material 290 is formed by a plating process.
- a first planarizing process is performed to expose the first insulating layer 270 according to a step 520 in FIG. 2 . Accordingly, a first interconnect structure 292 is formed. In some embodiments, the first metallic material 290 and the first barrier layer 280 are planarized to expose the first insulating layer 270 . In some embodiments, the first planarizing process includes a chemical mechanical polishing (CMP) process.
- CMP chemical mechanical polishing
- a bonding dielectric 44 is deposited on the first insulating layer 270 , the first barrier layer 280 and the first interconnect structure 292 according to a step 522 in FIG. 2 .
- the bonding dielectric 44 includes oxide, such as silicon oxide.
- the bonding dielectric 44 is formed in a manner similar to that used to form the bonding layer 40 .
- a second wafer 30 is provided and bonded on the first wafer 20 using the bonding dielectric 44 according to a step 524 in FIG. 2 .
- the second wafer 30 is bonded on the first wafer 20 by a dielectric-to-dielectric bonding process.
- the second wafer 30 includes a second substrate 310 , a second ILD layer 320 disposed on a second front surface 312 of the second substrate 310 , and a plurality of second contacts 330 in the second ILD layer 320 . After the second wafer 30 is bonded to the first wafer 20 , the second wafer 30 is stacked on the first wafer 20 , and the second ILD layer 320 is in contact with the bonding dielectric 44 .
- a first trench 340 is formed to expose one of the second contacts 330 and a second trench 342 is formed to expose the first interconnect structure 292 according to a step 526 in FIG. 2 .
- the first trench 340 and the second trench 342 are formed using photolithography techniques.
- the photolithography techniques involve depositing a photoresist material 66 , which is subsequently irradiated (exposed) and developed to remove a portion of the photoresist material 66 , on the second back surface 314 . The remaining photoresist material 66 protects the underlying second substrate 310 during subsequent etching processes.
- the etching processes such as a reactive ion beam etch (RIE) process, are performed to remove portions of the second substrate 310 and the second ILD layer 320 that overlie the one of the second contacts 330 and the first interconnect structure 292 .
- the remaining photoresist material 66 is then removed, for example, by an ashing process or a wet strip process.
- a recess 350 communicating with the first trench 340 and the second trench 342 is formed in the second substrate 310 according to a step 528 in FIG. 2 .
- the recess 350 may be formed, for example, using photolithography techniques to deposit and pattern a photoresist material 68 on the second back surface 314 to expose portions of the second back surface 314 , the first trench 340 and the second trench 342 .
- An etching process such as an anisotropic dry etch process, may be used to create the recess 350 in the second substrate 310 .
- the material 68 is then removed, for example, by an ashing process or a wet strip process.
- a substantially conformal second insulating layer 370 is deposited on the second back surface 314 and in the first trench 340 , the second trench 342 and the recess 350 according to a step 530 in FIG. 2 .
- the second insulating layer 370 is formed in a manner similar to that used to form the first insulating layer 270 .
- portions of the second insulating layer 370 deposited on the first interconnect structure 292 and the second conductor 330 are removed by a suitable process, such as an etching process.
- a substantially conformal second barrier layer 380 is optionally deposited on the first interconnect structure 292 , the second conductor 330 , and the second insulating layer 370 according to a step 532 in FIG. 2 .
- the second barrier layer 380 is formed in a manner similar to that used to form the first barrier layer 280 .
- a second metallic material 390 is deposited on the second barrier layer 380 according to a step 534 in FIG. 2 .
- the second metallic material 390 has a thickness sufficient to fill the first trench 340 , the second trench 342 and the recess 350 .
- the second metallic material 390 is formed in a manner similar to that used to form the first metallic material 290 .
- a second planarizing process is performed to expose the second insulating layer 370 according to a step 536 in FIG. 2 . Accordingly, a second interconnect structure 392 is formed. In some embodiments, the second metallic material 390 and the second barrier layer 380 are planarized to expose the second insulating layer 370 .
- one or more additional isolating layers 46 are formed on the second insulating layer 270 and one or more external contacts 48 are formed on the second interconnect structure 392 according to a step 538 in FIG. 2 .
- the external contacts 48 are used to transmit input/output (I/O), ground or power signals of the first wafer 20 and the second wafer 30 .
- a grinding process is performed to thin the carrier wafer 42 according to a step 540 in FIG. 2 . Accordingly, the semiconductor device 10 is completely formed.
- the carrier wafer 42 is thinned to a thickness T 2 , such as less than or equal to about 50 ⁇ m.
- One aspect of the present disclosure provides a method of manufacturing a semiconductor device.
- the method includes steps of providing a first wafer comprising a first substrate, a first inter-layer dielectric (ILD) layer disposed on a first front surface of the first substrate, and a plurality of first conductors disposed in the first ILD layer; forming a first interconnect structure penetrating through the first substrate and into the first ILD layer and contacting one of the first conductors; forming a bonding dielectric on a first back surface opposite to the first front surface and on the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer comprises a second substrate, a second ILD layer disposed on a second front surface of the second substrate, and a plurality of second conductors disposed in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting one of the pluralit
Abstract
Description
- The present disclosure relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a stacked integrated circuit device.
- As integrated circuit technologies continue to advance, ongoing efforts seek to increase performance and density, improve form factor, and reduce costs. One approach explored by designers to realize such benefits is the implementation of stacked three dimensional (3D) integrated circuits. Some areas where 3D integrated circuits are a suitable consideration include stacking of two or more chips that are fabricated using different fabrication processes, or stacking of chips that are fabricated using the same fabrication processes to reduce the footprint of the integrated circuit apparatus.
- This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this Discussion of the Background section constitute prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.
- One aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer comprising a first substrate, a first inter-layer dielectric (ILD) layer disposed on a first front surface of the first substrate, and a plurality of first conductors disposed in the first ILD layer; forming a first interconnect structure penetrating through the first substrate and into the first ILD layer and contacting one of the plurality of first conductors; forming a bonding dielectric on a first back surface opposite to the first front surface and on the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer comprises a second substrate, a second ILD layer disposed on a second front surface of the second substrate, and a plurality of second conductors disposed in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; and forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting one of the plurality of second conductors and the first interconnect structure.
- In some embodiments, the forming of the first interconnect structure includes steps of forming a first opening penetrating through the first substrate and into the first ILD layer to expose the one of the plurality of first conductors; and depositing a first metallic material in the first opening.
- In some embodiments, the forming of the second interconnect structure includes steps of forming a first trench penetrating through the second substrate, the second ILD layer and the bonding dielectric to expose the first metallic material; forming a second trench penetrating through the second substrate and into the second ILD layer to expose one of the second conductors; forming a recess communicating with the first trench and the second trench; and depositing a second metallic layer in the first trench, the second trench and recess.
- In some embodiments, the method further includes steps of depositing a first insulating layer along the first back surface and the first opening before the deposition of the first metallic material; removing a portion of the first insulating layer to expose the one of the first conductors; depositing a second insulating layer along a second back surface of the second substrate, the recess, the first trench, and the second trench before the deposition of the second metallic material; and removing portions of the second insulating layer to expose the one of the second conductors and the first metallic material.
- In some embodiments, the method further includes steps of depositing a first barrier layer on the first insulator and the one of the first conductors before the deposition of the first metallic material; and depositing a second barrier layer on the second insulating layer and the one of the second metallic contacts before the deposition of the second metallic material.
- In some embodiments, the method further includes steps of performing a first planarizing process to remove portions of the first metallic material and the first barrier layer that are above the first insulating layer; and performing a second planarizing process to remove portions of the second metallic material and the second barrier layer that are above the second insulating layer.
- In some embodiments, the forming of the first interconnect structure further includes steps of forming a second opening communicating with the first opening in the first substrate before the deposition of the first metallic material; and depositing the first metallic material in the second opening.
- In some embodiments, the second opening has a substantially consistent diameter, and the first opening has a diameter that gradually decreases at positions of increasing distance from the first back surface, wherein the diameter of the first opening is less than the diameter of the second opening.
- In some embodiments, the first opening has a central line, which is offset from a central line of the second opening.
- In some embodiments, the method further includes steps of depositing a passivation layer over the second back surface, and forming an external contact in contact with the second interconnect structure.
- In some embodiments, the method further includes steps of providing a carrier wafer before providing the first wafer; forming a forming a bonding layer on the carrier wafer; and bonding the first wafer on the carrier wafer, wherein the first ILD layer is in contact with the bonding layer.
- In some embodiments, the method further includes a step of thinning the first substrate after bonding the first wafer to the carrier wafer.
- In some embodiments, the method further includes a step of grinding the carrier wafer after the forming of the second metallic structure.
- In some embodiments, the first interconnect structure includes a mesa, and a protrusion extending from the mesa and contacting the first conductor.
- In some embodiments, the second interconnect structure includes a base, a first leg extending from the base and contacting the one of the second conductors, and a second leg extending from the base and contacting the first interconnect structure.
- The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and technical advantages of the disclosure are described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the concepts and specific embodiments disclosed may be utilized as a basis for modifying or designing other structures, or processes, for carrying out the purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit or scope of the disclosure as set forth in the appended claims.
- A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims. The disclosure should also be understood to be coupled to the figures' reference numbers, which refer to similar elements throughout the description.
-
FIG. 1 is a cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure. -
FIG. 2 is a flow diagram illustrating a method of manufacturing a package device in accordance with some embodiments of the present disclosure. -
FIGS. 3 to 28 illustrate cross-sectional views of intermediate stages in the formation of a semiconductor structure in accordance with some embodiments of the present disclosure. - Embodiments, or examples, of the disclosure illustrated in the drawings are now described using specific language. It shall be understood that no limitation of the scope of the disclosure is hereby intended. Any alteration or modification of the described embodiments, and any further applications of principles described in this document, are to be considered as normally occurring to one of ordinary skill in the art to which the disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that feature(s) of one embodiment apply to another embodiment, even if they share the same reference numeral.
- It shall be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
- The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting to the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It shall be understood that the terms “comprises” and “comprising,” when used in this specification, point out the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
-
FIG. 1 is a cross-sectional view of asemiconductor device 10 in accordance with some embodiments of the present disclosure. Referring toFIG. 1 , thesemiconductor device 10 includes afirst wafer 20 and asecond wafer 30 stacked and bonded to a top of thefirst wafer 20. In some embodiments, thefirst wafer 20 and thesecond wafer 30 may be fabricated using the same fabrication process. For example, thefirst wafer 20 and thesecond wafer 30 may form a memory stack. In some embodiments, thefirst wafer 20 and thesecond wafer 30 may be fabricated using different fabrication processes. For example, one of thefirst wafer 20 and thesecond wafer 30 may be a memory device and the other of thefirst wafer 20 and thesecond wafer 30 may be a processor, an image sensor or an application-specific integrated circuit (ASIC) device. - The
first wafer 20 and thesecond wafer 30 may be bonded using a dielectric-to-dielectric bonding process. For example, thesecond wafer 30 is bonded on thefirst wafer 20 by an oxide-to-oxide bonding process. In some embodiments, aback surface 214 of thefirst wafer 20 may be coated with one ormore bonding dielectrics 44 including oxide to provide a high-quality bonding interface. In some embodiments, thefirst wafer 20 may be stacked and bonded on acarrier wafer 42 by a dielectric-to-dielectric bonding process, wherein abonding layer 40 may be sandwiched between thefirst wafer 20 and the carrier wafer 42 to provide a high-quality bonding interface. - In some embodiments, the
first wafer 20 includes afirst substrate 210 having afront surface 212 opposite to theback surface 214, a first inter-layer dielectric (ILD)layer 220 disposed on thefront surface 212, and a plurality ofconductors 230 disposed in thefirst ILD layer 220. In some embodiments, thefirst substrate 210 may further include various layers that are not separately depicted and that combine to form various microelectronic elements that may include transistors, resistors, diodes, capacitors, inductors, fuses, other suitable elements, or combinations thereof. The various layers may include high-k dielectric layers, gate layers, interfacial layers, diffusion/barrier layers, dielectric layers, conductive layers, other suitable layers, or combinations thereof. The various layers of thefirst substrate 210 may also include various doped regions, isolation features, other features, or combinations thereof. Moreover, such microelectronic elements may interconnect with one another to form a portion of thefirst substrate 210, such as a logic device, a memory device, a radio frequency device, an input/output device, a system-on-chip device, other suitable type of device, or combinations thereof. In some embodiments, thefirst ILD layer 220 covers the microelectronic elements, the doped regions and the isolation features. - The
first wafer 20 further includes at least onefirst interconnect structure 292 penetrating through thefirst substrate 210 and into thefirst ILD layer 220 and contacting one of thefirst conductors 230. In some embodiments, thefirst interconnect structure 292 includes amesa 2920 and aprotrusion 2922 extending from themesa 2920 and contacting the one of thefirst conductors 230. In some embodiments, thefirst interconnect structure 292 includes metal such as copper or aluminum. - In some embodiments, the
first wafer 20 further includes a first insulatinglayer 270 extending along thefirst back surface 214 and attached to sidewalls 2921, 2923 of themesa 2920 and theprotrusion 2922. The first insulatinglayer 270 is formed to prevent diffusion spikes causing shorts across thefirst substrate 210 and thefirst interconnect structure 292. - In some embodiments, the
first wafer 20 may further include afirst barrier layer 280 sandwiched between thefirst interconnect structure 292 and the first insulatinglayer 270 and between thefirst interconnect structure 292 and thefirst conductor 230. In some embodiments, thefirst barrier layer 280 acts as a glue layer. In some embodiments, refractory metals, refractory metal nitrides, refractory metal silicon nitrides and combinations thereof are typically used for thefirst barrier layer 280. In some embodiments, thefirst barrier layer 280 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium silicon nitride (TiSN), tantalum silicon nitride (TaSiN), or the like. - The
second wafer 30 includes asecond substrate 310, asecond ILD layer 320 disposed on afront surface 312 of thesecond substrate 310, and a plurality ofsecond conductors 330 disposed in thesecond ILD layer 320. In some embodiments, thesecond substrate 310 may further include various layers that are not separately depicted and that combine to form various microelectronic elements, doped regions and isolation features mentioned above. In some embodiments, thesecond ILD layer 320 covers the microelectronic elements, the doped regions and the isolation features. - The
second wafer 30 further includes at least onesecond interconnect structure 392 coupled to one of thefirst conductors 230 to provide an external electrical connection and coupled to one of thesecond conductors 330 to provide an internal connection. In some embodiments, thesecond interconnect structure 392 includes abase 3920, afirst leg 3922 extending from thebase 3920 and contacting thesecond conductor 330, and asecond leg 3924 extending from thebase 3920 and contacting thefirst interconnect structure 292. In some embodiments, thebase 3920, thefirst leg 3922 and thesecond leg 3924 are integrated and formed of material including metal such as copper or aluminum. - The
second wafer 30 may further include asecond insulator 370 disposed on aback surface 314 opposite thefront surface 312 of thesecond substrate 310 and on sidewalls 3921, 3923 and 3925 of thebase 3920, thefirst leg 3922 and thesecond leg 3924, respectively. The secondinsulating layer 370 is formed to prevent diffusion spikes causing shorts across thesecond substrate 310 and thesecond interconnect structure 392. - The
second wafer 30 may further include asecond diffusion layer 380 disposed between thesecond interconnect structure 392 and the second insulatinglayer 370 and between thesecond interconnect structure 392 and thesecond conductor 330. - In some embodiments, the
semiconductor device 10 further includes apassivation layer 46 disposed on the second insulatinglayer 370 and at least oneexternal contact 48 disposed on thesecond interconnect structure 292. Thepassivation layer 46 is used to protect thesecond wafer 30 from the environment. -
FIG. 2 is a flow diagram illustrating a method 50 of manufacturing asemiconductor device 10 in accordance with some embodiments of the present disclosure.FIGS. 3 to 28 are schematic diagrams illustrating various fabrication stages constructed according to the method 50 for manufacturing thesemiconductor device 10 in accordance with some embodiments of the present disclosure. The stages shown inFIGS. 3 to 28 are also illustrated schematically in the flow diagram inFIG. 2 . In the subsequent discussion, the fabrication stages shown inFIGS. 3 to 28 are discussed in reference to the process steps shown inFIG. 2 . - Referring to
FIG. 3 , acarrier wafer 42 is provided according to astep 502 inFIG. 2 . In some embodiments, thecarrier wafer 42 may be a bare silicon wafer without any electrical circuitry disposed thereon. In some embodiments, thecarrier wafer 42 includes afirst surface 422 and asecond surface 424 opposite to thefirst surface 422. In some embodiments, thecarrier wafer 42 has a thickness T1, which may be, for example, greater than 750 μm, such as 775 μm. - Next, a
bonding layer 40 is formed on thefirst surface 422 according to astep 504 inFIG. 2 . In some embodiments, thebonding layer 40 includes oxide, such as silicon oxide. In some embodiments, thebonding layer 40 may be formed by a thermal oxidation process or a chemical vapor deposition (CVD) process. - Referring to
FIGS. 4 and 5 , afirst wafer 20 is provided and bonded on thecarrier wafer 42 according to astep 506 inFIG. 2 . In some embodiments, thefirst wafer 20 is bonded on thecarrier wafer 42 by a dielectric-to-dielectric bonding process, such as an oxide fusion bonding process. In some embodiments, thefirst wafer 20 includes afirst substrate 210, a first inter layer dielectric (ILD)layer 220 disposed on a firstfront surface 212 of thefirst substrate 210, and a plurality offirst conductors 230 disposed in theILD layer 220. After thefirst wafer 20 and thecarrier wafer 42 are bonded, thefirst wafer 20 is stacked on thecarrier wafer 42, and thefirst ILD layer 220 is in contact with thebonding layer 40. Thefirst substrate 210 may include, for example, doped or undoped bulk silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. In some embodiments, thefirst substrate 210 may further include various layers that are not separately depicted and that combine to form various microelectronic elements, doped regions and isolation features, wherein thefirst ILD layer 220 is disposed over the microelectronic elements, the doped regions and the isolation features. - Referring to
FIG. 6 , a thinning process may be performed to thin thefirst wafer 20 according to astep 508 inFIG. 2 . Accordingly, afirst back surface 214′ is exposed. In some embodiments, the thinning process is performed on an initial back surface 214 (shown inFIGS. 4 and 5 ), opposite to thefront surface 212, to thin thefirst substrate 210. InFIG. 6 , the dotted line marks an original thickness of thefirst substrate 210. The thinning process may be implemented using suitable techniques such as a grinding process, a polishing process and/or a chemical etching process. - Referring to
FIGS. 7 and 8 , in some embodiments, afirst opening 240 is formed to expose one of thefirst contacts 230 according to astep 510 inFIG. 2 . In some embodiments, thefirst opening 240 is formed by coating afirst photoresist pattern 62 on thefirst back surface 214′ and performing a first etching process to remove portions of thefirst substrate 210 and thefirst ILD layer 220. In some embodiments, thefirst photoresist pattern 62 may be formed by performing an exposure process and a develop process on a first photoresist material fully covering thefirst back surface 214′. In some embodiments, a portion of thefirst back surface 214′ to be etched is exposed through thefirst photoresist pattern 62. In some embodiments, thefirst opening 240 stops at one of thefirst contacts 230. In some embodiments, the first etch process may utilize multiple etchants to etch thefirst substrate 210 and thefirst ILD layer 220, wherein the etchants are selected based on the materials being etched. In some embodiments, thefirst substrate 210 and thefirst ILD layer 220 may be etched using a dry etching process, an anisotropic wet etching process, or any other suitable anisotropic etching process. After the first etching process, thefirst photoresist pattern 62 is removed, for example, by an ashing process or a wet strip process, wherein the wet strip process may chemically alter thefirst photoresist pattern 62 so that it no longer adheres to thefirst substrate 210. - Referring to
FIGS. 9 and 10 , in some embodiments, asecond opening 250 communicating with thefirst opening 240 is formed according to astep 512 inFIG. 2 . In some embodiments, thesecond opening 250 is formed by coating asecond photoresist pattern 64 on thefirst back surface 214′ and performing a second etching process to remove a portion of thefirst substrate 210. In some embodiments, thefirst opening 240 and a portion of thefirst back surface 214′ are exposed through thesecond photoresist pattern 64. In some embodiments, thefirst opening 240 and thesecond opening 250 constitute a steppedhole 260. In some embodiments, thefirst opening 240 has a diameter D1 that gradually decreases at positions of increasing distance from thefirst back surface 214′. In some embodiments, thesecond opening 250 has a substantially consistent diameter D2, which is greater than the diameter D1 of thefirst opening 240. In some embodiments, thefirst opening 240 has acentral line 242, and thesecond opening 250 has acentral line 252 that is offset from thecentral line 242. After the second etching process, thesecond photoresist pattern 64 is removed, for example, by an ashing process or a wet strip process. - Referring to
FIG. 11 , in some embodiments, a first insulatinglayer 270 is deposited on thefirst back surface 214′ and in the steppedhole 260 according to astep 514 inFIG. 2 . In the resulting structure, thefirst conductor 230 exposed through the steppedhole 260 is covered by the first insulatinglayer 270. In some embodiments, the first insulatinglayer 270 is a substantially conformal layer. In some embodiments, the first insulatinglayer 270 includes oxide such as silicon oxide. In some embodiments, the first insulatinglayer 270 may be formed by a high-density plasma CVD process. - Next, a portion of the first insulating
layer 270 is removed to expose thefirst conductor 230, as shown inFIG. 12 . In some embodiments, the portion of the first insulatinglayer 270 is removed by a suitable process, such as an etching process. - Referring to
FIG. 13 , in some embodiments, afirst barrier layer 280 is optionally deposited on the first insulatinglayer 270 and thefirst conductor 230 according to astep 516 inFIG. 2 . In some embodiments, thefirst barrier layer 280 is a substantially conformal layer. In some embodiments, thefirst barrier layer 280 may be a single-layered structure including refractory metals, refractory metal nitrides or refractory metal silicon nitrides. In some embodiments, thefirst barrier layer 280 may have a multi-layered structure including one or more refractory metals, refractory metal nitrides or refractory metal silicon nitrides. In some embodiments, thefirst barrier layer 280 is formed using a physical vapor deposition (PVD) process or an atomic layer deposition process, for example. - Referring to
FIG. 14 , a firstmetallic material 290 is deposited on thefirst barrier layer 280 according to astep 518 inFIG. 2 . In some embodiments, the firstmetallic material 290 has a thickness sufficient to fill the steppedhole 260. In some embodiments, the firstmetallic material 290 is formed by a plating process. - Referring to
FIG. 15 , in some embodiments, a first planarizing process is performed to expose the first insulatinglayer 270 according to astep 520 inFIG. 2 . Accordingly, afirst interconnect structure 292 is formed. In some embodiments, the firstmetallic material 290 and thefirst barrier layer 280 are planarized to expose the first insulatinglayer 270. In some embodiments, the first planarizing process includes a chemical mechanical polishing (CMP) process. - Referring to
FIG. 16 , in some embodiments, abonding dielectric 44 is deposited on the first insulatinglayer 270, thefirst barrier layer 280 and thefirst interconnect structure 292 according to astep 522 inFIG. 2 . In some embodiments, thebonding dielectric 44 includes oxide, such as silicon oxide. In some embodiments, thebonding dielectric 44 is formed in a manner similar to that used to form thebonding layer 40. - Referring to
FIG. 17 , in some embodiments, asecond wafer 30 is provided and bonded on thefirst wafer 20 using thebonding dielectric 44 according to astep 524 inFIG. 2 . In some embodiments, thesecond wafer 30 is bonded on thefirst wafer 20 by a dielectric-to-dielectric bonding process. In some embodiments, thesecond wafer 30 includes asecond substrate 310, asecond ILD layer 320 disposed on a secondfront surface 312 of thesecond substrate 310, and a plurality ofsecond contacts 330 in thesecond ILD layer 320. After thesecond wafer 30 is bonded to thefirst wafer 20, thesecond wafer 30 is stacked on thefirst wafer 20, and thesecond ILD layer 320 is in contact with thebonding dielectric 44. - Referring to
FIGS. 18 and 19 , in some embodiments, afirst trench 340 is formed to expose one of thesecond contacts 330 and asecond trench 342 is formed to expose thefirst interconnect structure 292 according to astep 526 inFIG. 2 . In some embodiments, thefirst trench 340 and thesecond trench 342 are formed using photolithography techniques. In further detail, the photolithography techniques involve depositing aphotoresist material 66, which is subsequently irradiated (exposed) and developed to remove a portion of thephotoresist material 66, on thesecond back surface 314. The remainingphotoresist material 66 protects the underlyingsecond substrate 310 during subsequent etching processes. The etching processes, such as a reactive ion beam etch (RIE) process, are performed to remove portions of thesecond substrate 310 and thesecond ILD layer 320 that overlie the one of thesecond contacts 330 and thefirst interconnect structure 292. The remainingphotoresist material 66 is then removed, for example, by an ashing process or a wet strip process. - Referring to
FIGS. 20 and 21 , in some embodiments, arecess 350 communicating with thefirst trench 340 and thesecond trench 342 is formed in thesecond substrate 310 according to astep 528 inFIG. 2 . In some embodiments, therecess 350 may be formed, for example, using photolithography techniques to deposit and pattern aphotoresist material 68 on thesecond back surface 314 to expose portions of thesecond back surface 314, thefirst trench 340 and thesecond trench 342. An etching process, such as an anisotropic dry etch process, may be used to create therecess 350 in thesecond substrate 310. Thematerial 68 is then removed, for example, by an ashing process or a wet strip process. - Referring to
FIG. 22 , in some embodiments, a substantially conformal second insulatinglayer 370 is deposited on thesecond back surface 314 and in thefirst trench 340, thesecond trench 342 and therecess 350 according to astep 530 inFIG. 2 . In some embodiments, the second insulatinglayer 370 is formed in a manner similar to that used to form the first insulatinglayer 270. - Referring to
FIG. 23 , portions of the second insulatinglayer 370 deposited on thefirst interconnect structure 292 and thesecond conductor 330 are removed by a suitable process, such as an etching process. - Referring to
FIG. 24 , in some embodiments, a substantially conformalsecond barrier layer 380 is optionally deposited on thefirst interconnect structure 292, thesecond conductor 330, and the second insulatinglayer 370 according to astep 532 inFIG. 2 . In some embodiments, thesecond barrier layer 380 is formed in a manner similar to that used to form thefirst barrier layer 280. - Referring to
FIG. 25 , a secondmetallic material 390 is deposited on thesecond barrier layer 380 according to astep 534 inFIG. 2 . In some embodiments, the secondmetallic material 390 has a thickness sufficient to fill thefirst trench 340, thesecond trench 342 and therecess 350. In some embodiments, the secondmetallic material 390 is formed in a manner similar to that used to form the firstmetallic material 290. - Referring to
FIG. 26 , in some embodiments, a second planarizing process is performed to expose the second insulatinglayer 370 according to astep 536 inFIG. 2 . Accordingly, asecond interconnect structure 392 is formed. In some embodiments, the secondmetallic material 390 and thesecond barrier layer 380 are planarized to expose the second insulatinglayer 370. - Referring to
FIG. 27 , one or more additional isolatinglayers 46 are formed on the second insulatinglayer 270 and one or moreexternal contacts 48 are formed on thesecond interconnect structure 392 according to astep 538 inFIG. 2 . In some embodiments, theexternal contacts 48 are used to transmit input/output (I/O), ground or power signals of thefirst wafer 20 and thesecond wafer 30. - Referring to
FIG. 28 , a grinding process is performed to thin thecarrier wafer 42 according to astep 540 inFIG. 2 . Accordingly, thesemiconductor device 10 is completely formed. In some embodiments, thecarrier wafer 42 is thinned to a thickness T2, such as less than or equal to about 50 μm. - One aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer comprising a first substrate, a first inter-layer dielectric (ILD) layer disposed on a first front surface of the first substrate, and a plurality of first conductors disposed in the first ILD layer; forming a first interconnect structure penetrating through the first substrate and into the first ILD layer and contacting one of the first conductors; forming a bonding dielectric on a first back surface opposite to the first front surface and on the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer comprises a second substrate, a second ILD layer disposed on a second front surface of the second substrate, and a plurality of second conductors disposed in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting one of the plurality of second conductors and the first interconnect structure.
- Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
- Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods and steps.
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US7452805B2 (en) | 2006-03-20 | 2008-11-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Aluminum based conductor for via fill and interconnect |
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