JPH042154A - Method of packaging semiconductor device - Google Patents
Method of packaging semiconductor deviceInfo
- Publication number
- JPH042154A JPH042154A JP2101562A JP10156290A JPH042154A JP H042154 A JPH042154 A JP H042154A JP 2101562 A JP2101562 A JP 2101562A JP 10156290 A JP10156290 A JP 10156290A JP H042154 A JPH042154 A JP H042154A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- semiconductor device
- heat
- heat sink
- aluminum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims description 16
- 238000004806 packaging method and process Methods 0.000 title 1
- 238000002161 passivation Methods 0.000 claims abstract description 19
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052737 gold Inorganic materials 0.000 claims abstract description 18
- 239000010931 gold Substances 0.000 claims abstract description 18
- 230000017525 heat dissipation Effects 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 16
- 229910052782 aluminium Inorganic materials 0.000 abstract description 32
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 32
- 239000000919 ceramic Substances 0.000 abstract description 7
- 230000004888 barrier function Effects 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 230000005012 migration Effects 0.000 abstract description 3
- 238000013508 migration Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 44
- 239000010410 layer Substances 0.000 description 8
- 239000010409 thin film Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、放熱効果の大きい半導体装置の実装方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for mounting a semiconductor device that has a large heat dissipation effect.
［従来の技術］
絶縁基板上に形成した薄膜トランジスタや抵抗を有する
半導体装置をパッケージに実装する方法としては、従来
、第３図の断面図に示す方法がある。[Prior Art] As a method for mounting a semiconductor device having a thin film transistor or a resistor formed on an insulating substrate into a package, there is a conventional method shown in the cross-sectional view of FIG. 3.
第３図において、Ａは半導体装置である。半導体装置Ａ
はシリコン基板２、絶縁膜３、ソース領域４、ドレイン
領域５、チャンネル領域６、ゲート絶縁膜７、ゲート電
極８、層間絶縁膜９、アルミ配線１０、及びパッシベー
ション膜１１から成っており、シリコン基板２をパッケ
ージのアイランド１２と接合し、リード１３とアルミワ
イヤー１４で接続した後、キャップ１５で封止する。In FIG. 3, A is a semiconductor device. Semiconductor device A
consists of a silicon substrate 2, an insulating film 3, a source region 4, a drain region 5, a channel region 6, a gate insulating film 7, a gate electrode 8, an interlayer insulating film 9, an aluminum wiring 10, and a passivation film 11. 2 is bonded to the island 12 of the package, connected to the lead 13 with an aluminum wire 14, and then sealed with a cap 15.
また第４図の断面図に示す様な方法で、半導体装置Ａを
パッケージに実装する方法もある。第４図において、第
３図と同一番号は同一の内容を示す。There is also a method of mounting the semiconductor device A in a package as shown in the cross-sectional view of FIG. In FIG. 4, the same numbers as in FIG. 3 indicate the same contents.
第４図において、アルミ配線１０上にバリアメタル１６
とバンプ１７を形成した後、セラミックのヒート・シン
クｌに半導体装置Ａを固定し、パッシベーション膜１１
上に樹脂１９を形成した後、セラミック基板１８上のリ
ード１３にバンプ１７を熱圧着する。In FIG. 4, barrier metal 16 is placed on aluminum wiring 10.
After forming the bumps 17, the semiconductor device A is fixed to a ceramic heat sink l, and the passivation film 11 is
After forming resin 19 thereon, bumps 17 are thermocompression bonded to leads 13 on ceramic substrate 18 .
［発明が解決しようとする課題］
しかしながら、上記第３図の従来例においては、薄膜ト
ランジスタ部Ｂや、アルミ配！！１０等の発熱部からの
熱は、熱伝導率の小さい層間絶縁膜９と絶縁膜３を経由
して更にシリコン基板２からアイランド１２へ熱伝導し
た後、大気中に放熱するか、熱伝導率の小さいパッシベ
ーション膜１１から、同じ（熱伝導率の小さな空気２０
を介し、キャップ１５を経て、大気中に放熱しているた
め、放熱効率が良（ないという問題がある。[Problems to be Solved by the Invention] However, in the conventional example shown in FIG. ! The heat from the heat generating parts such as 10 is further conducted from the silicon substrate 2 to the island 12 via the interlayer insulating film 9 and the insulating film 3, which have low thermal conductivity, and then is radiated into the atmosphere or is From the passivation film 11 with a small thermal conductivity to the air 20 with a small thermal conductivity
Since the heat is radiated into the atmosphere through the cap 15, there is a problem that the heat radiation efficiency is not good.
また、上記第４図の従来例では、薄膜トランジスタ部Ｂ
や、アルミ配線１０からの発熱は、熱伝導率の小さい層
間絶縁膜９と、絶縁膜３を経由して、シリコン基板２か
らヒートシンク１に熱伝導した後、大気中に放熱するか
、熱伝導率の小さいパッシベーション膜１１から同じく
熱伝導率の小さな樹脂１９を経由して、セラミック基板
１８から大気中に放熱しているため、やはり放熱効率は
良くないという問題がある。Furthermore, in the conventional example shown in FIG. 4 above, the thin film transistor section B
The heat generated from the aluminum wiring 10 is conducted from the silicon substrate 2 to the heat sink 1 via the interlayer insulating film 9 and the insulating film 3, which have low thermal conductivity, and then is radiated into the atmosphere or by thermal conduction. Since heat is radiated from the ceramic substrate 18 to the atmosphere from the passivation film 11, which has a low thermal conductivity, through the resin 19, which also has a low thermal conductivity, there is a problem that the heat radiation efficiency is not good.
また、１７はアルミ配置ｌｌ １０とリード１３を接続
して信号電流を通すためのバンプであるが、このバンプ
１７とリード１３を伝わっても、アルミ配線１０から発
生する熱の放熱が為される。ところが、第４図の例では
、ヒートシンク１が半導体装置の下部に取り付けられて
おり、即ちバンプ１７と基板２を挾んで反対側に設けら
れている。そのため、やはり放熱効率は良くないという
問題がある。Further, 17 is a bump for connecting the aluminum wiring ll 10 and the lead 13 to pass a signal current, but even if it is transmitted through the bump 17 and the lead 13, the heat generated from the aluminum wiring 10 is dissipated. . However, in the example shown in FIG. 4, the heat sink 1 is attached to the lower part of the semiconductor device, that is, it is provided on the opposite side of the bump 17 and the substrate 2. Therefore, there is still a problem that the heat dissipation efficiency is not good.
この様に、従来の半導体装置の実装方法では、放熱効率
が悪く、薄膜トランジスタＢやアルミ配線１０の温度が
上昇し、温度上昇によるトランジスタ特性の劣化や、マ
イグレーションによるアルミ配線１０の断線が生じやす
くなり、トランジスタの誤動作や信頼性の低下がおこる
という欠点があった。As described above, in the conventional semiconductor device mounting method, the heat dissipation efficiency is poor, and the temperature of the thin film transistor B and the aluminum wiring 10 rises, resulting in deterioration of transistor characteristics due to the temperature rise and breakage of the aluminum wiring 10 due to migration. However, there were drawbacks such as malfunction of the transistor and reduction in reliability.
［課題を解決するための手段及び作用］本発明は、上述
した課題を解決するための手段として、
絶縁基板上に形成した半導体装置の実装方法において、
前記絶縁基板上に設けられる半導体装置、及び該半導体
装置の上方に設けられるバンプ、及び該バンプの上方に
設けられる放熱用ヒートシンクとを放熱経路として有す
ることを特徴とする半導体装置の実装方法を提供するも
のである。[Means and effects for solving the problems] The present invention provides a method for mounting a semiconductor device formed on an insulating substrate as a means for solving the above-mentioned problems, including: a semiconductor device provided on the insulating substrate; A method for mounting a semiconductor device is provided, characterized in that a bump provided above the semiconductor device and a heat sink for heat radiation provided above the bump are used as a heat radiation path.
また前言己半導体装置の発熱部上に、パッシベーション
膜を介して、信号電流の通らないバンプを熱伝導膜とし
て形成し、前記放熱用ヒート・シンクと熱的に結合する
ことを特徴とする半導体装置の実装方法によって、前記
課題を解決しようとするものである。Furthermore, a semiconductor device characterized in that a bump through which a signal current does not pass is formed as a heat conductive film on the heat generating part of the semiconductor device via a passivation film, and is thermally coupled to the heat sink for heat dissipation. This implementation method attempts to solve the above problem.
本発明によれば、ヒートシンクをバンプの上方に熱的に
接続して設けることにより、従来例の様に基板の下にヒ
ートシンクを設けたものに比較して、放熱効率が良くな
る。According to the present invention, by providing the heat sink in a thermally connected manner above the bump, the heat dissipation efficiency is improved compared to the conventional example in which the heat sink is provided below the substrate.
またパッシベーション膜１１上に信号電流用でないバン
プ１７を形成してヒート・シンク１と熱的に結合する事
により、薄膜トランジスタＢやアルミ配線１０等の発熱
部からの発熱を大気中へ効率良く放熱することができる
。In addition, by forming bumps 17 not for signal current on the passivation film 11 and thermally coupling them to the heat sink 1, heat generated from heat generating parts such as the thin film transistor B and the aluminum wiring 10 can be efficiently radiated into the atmosphere. be able to.
［実施例］ 以下本発明の実施例を詳細に説明する。[Example] Examples of the present invention will be described in detail below.
（実施例１） 第１図において、第３図と同一番号は同一内容を示す。(Example 1) In FIG. 1, the same numbers as in FIG. 3 indicate the same contents.
まず半導体装置Ａを形成する為、シリコン基板２上に絶
縁膜３を１μｍ形成した後、シリコン薄膜にソース領域
４、ドレイン領域５、チャンネル領域６とゲート絶縁膜
７とゲート電極８を形成する。First, to form the semiconductor device A, an insulating film 3 of 1 μm thickness is formed on a silicon substrate 2, and then a source region 4, a drain region 5, a channel region 6, a gate insulating film 7, and a gate electrode 8 are formed on the silicon thin film.
次に眉間絶縁膜９としてＰＳＧ膜を０．８μｍ堆積し、
アルミ配線１０とパッシベーション膜１１としてプラズ
マ窒化膜を６０００人堆積する。Next, a 0.8 μm thick PSG film was deposited as the glabellar insulating film 9.
6,000 plasma nitride films are deposited as aluminum wiring 10 and passivation film 11.
次にパッシベーション膜１１に開口して、このパッシベ
ーション膜１１の開口部と、パッシベーション膜１１上
に、バリアメタル１６と、厚さ１０μｍの金バンプ１７
と２３（熱伝導膜２３）をメツキで形成した後、アルミ
配線１０上の金バンプ１７をセラミックのヒート・シン
ク１に形成した信号線用のリード１３に熱圧着し、同時
に、バリアメタル１６上の金バンプ２３（熱伝導膜２３
）を放熱用のリード２２に熱圧着する。Next, an opening is made in the passivation film 11, and a barrier metal 16 and a gold bump 17 with a thickness of 10 μm are placed in the opening of the passivation film 11 and on the passivation film 11.
and 23 (thermal conductive film 23) by plating, the gold bumps 17 on the aluminum wiring 10 are bonded by thermocompression to the signal line leads 13 formed on the ceramic heat sink 1, and at the same time, the gold bumps 17 on the aluminum wiring 10 are bonded to the signal wire leads 13 formed on the ceramic heat sink 1. gold bump 23 (thermal conductive film 23
) is thermocompression bonded to the heat dissipation lead 22.
ここで、バンプ１７は信号電流の流れるバンプであるが
、バンプ２３はパッシベーション膜１１により、アルミ
配線１０とは電気的に絶縁されており、信号電流が流れ
ることはないが、熱的には結合されており、アルミ配！
！１０や、トランジスタ部Ｂから発生する熱の放熱経路
としての熱伝導膜として用いられる。Here, the bump 17 is a bump through which a signal current flows, but the bump 23 is electrically insulated from the aluminum wiring 10 by the passivation film 11, so no signal current flows therethrough, but the bump 23 is thermally coupled. It is made of aluminum!
! 10 and as a heat conductive film as a heat dissipation path for heat generated from the transistor section B.
本実施例では、信号電流接続用のバンプ１７の形成処理
時に、同時に熱伝導膜としてのバンプ２３を形成するこ
とができ、また史にその上方に配置されるヒートシンク
１と熱的に接ｂ“ｃｆることにより、放熱効率を高める
ことができる。In this embodiment, when forming the bump 17 for signal current connection, the bump 23 as a thermally conductive film can be formed at the same time, and the bump 23 can be thermally connected to the heat sink 1 disposed above the bump 23. cf, it is possible to improve heat dissipation efficiency.
本実施例では、金を用いて、バンプ１７及び熱伝導膜と
してのバンプ２３を形成したが、熱伝導率の大きいイン
ジウム、銅でもよい。In this embodiment, the bumps 17 and the bumps 23 as thermally conductive films are formed using gold, but they may also be made of indium or copper, which have high thermal conductivity.
（実施例２）
第２図は、本発明の他の実施例を示す半導体装置Ａとそ
のパッケージの断面図である。(Embodiment 2) FIG. 2 is a sectional view of a semiconductor device A and its package showing another embodiment of the present invention.
上述した実施例１と同様に、半導体装置Ａを形成後、ア
ルミ層２１を３０００人スパッタリングにより堆積した
後、パッシベーション膜１１に開口して、パッシベーシ
ョン膜１１の開口部と、アルミ層２１上の一部にバリア
メタル１６と、厚さ５０ッ、の金バンプ１７及び２３を
形成する。ここで、金バンプ２３は、パッシベーション
膜１１により電気的に絶縁されているため、信号電流が
流れることはないが、熱的には半導体装置と結合されて
いる。Similarly to Example 1 described above, after forming the semiconductor device A, an aluminum layer 21 is deposited by sputtering for 3000 people, and an opening is made in the passivation film 11 to form an opening in the passivation film 11 and a portion on the aluminum layer 21. A barrier metal 16 and gold bumps 17 and 23 with a thickness of 50 mm are formed on the portion. Here, since the gold bumps 23 are electrically insulated by the passivation film 11, no signal current flows through them, but they are thermally coupled to the semiconductor device.
本実施例では、熱伝導膜となる金バンプ２３は、発熱部
であるトランジスタ部Ｂとアルミ配線１０上にのみ形成
するところが実施例１と異なり、バンプ材料を節約する
ことができる。This embodiment differs from embodiment 1 in that the gold bumps 23, which serve as thermally conductive films, are formed only on the transistor section B, which is a heat generating section, and on the aluminum wiring 10, so that the bump material can be saved.
次に、金バンプ１７及び２３の間のアルミ層２１上に、
樹脂１９を滴下する。その後アルミ配線１０上の金バン
プ１７を、ヒート・シンク１に形成した信号線用のり−
ド１３に熱圧着し、アルミ層２１上の金バンプ（熱伝導
膜）２３を放熱用のり−ド２２に熱圧着すると、金バン
プ１７及び２３（熱伝導膜２３）の間の空間は樹脂１９
で満たされる。Next, on the aluminum layer 21 between the gold bumps 17 and 23,
Drop resin 19. Thereafter, the gold bumps 17 on the aluminum wiring 10 are attached to the signal line glue formed on the heat sink 1.
When the gold bumps (thermal conductive film) 23 on the aluminum layer 21 are thermocompressed to the heat dissipating glue 22, the space between the gold bumps 17 and 23 (thermal conductive film 23) becomes the resin 19.
filled with.
本実施例では、パッシベーション膜１１の上に放熱経路
となるアルミ層２１を設け、このアルミ層２１上に、半
導体装置の発熱部上にのみ設けられたバンプ１７及びバ
ンプ（熱伝導膜）２３を伝わってヒートシンク１によっ
て、大気中に放熱が為される。In this embodiment, an aluminum layer 21 serving as a heat dissipation path is provided on the passivation film 11, and bumps 17 and bumps (thermal conductive film) 23 provided only on heat generating parts of the semiconductor device are provided on this aluminum layer 21. The heat is then radiated into the atmosphere by the heat sink 1.
尚、アルミ層２１は、熱伝導率の大きい金、ベリリウム
、銅、シリコン、ゲルマニウムなどの薄膜でもよい。Note that the aluminum layer 21 may be a thin film of gold, beryllium, copper, silicon, germanium, or the like having high thermal conductivity.
［発明の効果］
以上説明した様に、本発明によれば、絶縁基板上に作成
された半導体装置の上方にバンプと放熱用ヒートシンク
を設けること、及びパッシベーション膜１１上に信号電
流接続用でなく、放熱経路としてのバンプ２３を形成し
て熱伝導膜２３とし、放熱用ヒートシンクと熱的に結合
することにより、薄膜トランジスタＢやアルミ配置！！
１０からの発熱が、効率よく大気中に放熱されるとい効
果が得られる。[Effects of the Invention] As explained above, according to the present invention, a bump and a heat sink for heat dissipation are provided above a semiconductor device fabricated on an insulating substrate, and a bump and a heat sink for heat dissipation are provided on the passivation film 11 instead of for signal current connection. , by forming bumps 23 as heat dissipation paths and using them as the heat conductive film 23, and thermally coupling them to the heat sink for heat dissipation, thin film transistor B and aluminum arrangement can be achieved! !
An effect is obtained in that the heat generated from 10 is efficiently radiated into the atmosphere.
このため、温度上昇によるトランジスタ特性の劣化や、
マイグレーシジンによるアルミ配線の断線を防止するこ
とができ、半導体装置の信頼性や、安定性を向上する効
果がある。For this reason, the transistor characteristics deteriorate due to temperature rise,
It is possible to prevent disconnection of aluminum wiring due to migration resin, and has the effect of improving the reliability and stability of semiconductor devices.
また、バンプ（熱伝導膜）２３は、信号電流の流れるバ
ンプ１７と同じ製造方法で同時に作成することができる
ため、作成も容易である。Further, the bump (thermal conductive film) 23 can be manufactured simultaneously with the bump 17 through which the signal current flows, using the same manufacturing method, so that it is easy to manufacture.
第１図は、本発明の実施例１による半導体装置の実装方
法。
第２図は、本発明の実施例２による半導体装置の実装方
法。
第３図は、従来の方法による半導体装置の実装方法。
第４図は、他の従来の方法による半導体装置の実装方法
。
ッシベーシロン膜、１２・・・アイランド、１３．２２
・・・リード、１４・・・アルミワイヤー １５・・・
キャップ、１６・・・バリアメタル、１７・・・（信号
電流の流れる）バンプ、１８・・・セラミック基板、１
９・・・樹脂、２０・・・空気、２１・・・アルミ層、
２３・・・（信号電流の流れない）バンプ（熱伝導膜）
。
代理人 弁理士 山 下 穣 平
Ａ・・・半導体装置、Ｂ・・・薄膜トランジスタ、１・
・・ヒート・シンク、２・・・シリコン基板、３・・・
絶縁膜、４・・・ソース領域、５・・・ドレイン領域、
６・・・チャンネル領域、７・・・ゲート絶縁膜、８・
・・ゲート電極、９・・・層間絶縁膜、１０・・・アル
ミ配線、１１・・・パ第１図
第２図
第
図
第
図Embodiment 1 FIG. 1 shows a method for mounting a semiconductor device according to a first embodiment of the present invention. FIG. 2 shows a method for mounting a semiconductor device according to a second embodiment of the present invention. FIG. 3 shows a conventional method for mounting a semiconductor device. FIG. 4 shows a semiconductor device mounting method using another conventional method. Basilon membrane, 12...Island, 13.22
...Lead, 14...Aluminum wire 15...
Cap, 16... Barrier metal, 17... Bump (through which signal current flows), 18... Ceramic substrate, 1
9...Resin, 20...Air, 21...Aluminum layer,
23... (signal current does not flow) bump (thermal conductive film)
. Agent Patent Attorney Minoru Yamashita A: Semiconductor device, B: Thin film transistor, 1.
...Heat sink, 2...Silicon substrate, 3...
Insulating film, 4... source region, 5... drain region,
6... Channel region, 7... Gate insulating film, 8.
...Gate electrode, 9...Interlayer insulating film, 10...Aluminum wiring, 11...P Figure 1 Figure 2 Figure Figure
Claims (4)
いて、 前記絶縁基板上に設けられる半導体装置、及び該半導体
装置の上方に設けられるバンプ、及び該バンプの上方に
設けられる放熱用ヒートシンクとを放熱経路として有す
ることを特徴とする半導体装置の実装方法。(1) A method for mounting a semiconductor device formed on an insulating substrate, which includes a semiconductor device provided on the insulating substrate, a bump provided above the semiconductor device, and a heat sink for heat dissipation provided above the bump. 1. A method for mounting a semiconductor device, characterized in that a semiconductor device is provided as a heat dissipation path.
膜を介して、信号電流の通らないバンプを熱伝導膜とし
て形成し、前記放熱用ヒート・シンクと熱的に結合する
ことを特徴とする請求項１に記載の半導体装置の実装方
法。(2) A claim characterized in that a bump through which a signal current does not pass is formed as a heat conductive film on the heat generating portion of the semiconductor device via a passivation film, and is thermally coupled to the heat sink for heat dissipation. Item 1. A method for mounting a semiconductor device according to item 1.
に記載の半導体装置の実装方法。(3) Claim 1, wherein the bump is formed of a gold bump.
A method for mounting a semiconductor device according to .
されることを特徴とする請求項２に記載の半導体装置の
実装方法。(4) The method for mounting a semiconductor device according to claim 2, wherein the bump is formed at the same time as a signal current bump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2101562A JPH042154A (en) | 1990-04-19 | 1990-04-19 | Method of packaging semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2101562A JPH042154A (en) | 1990-04-19 | 1990-04-19 | Method of packaging semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH042154A true JPH042154A (en) | 1992-01-07 |
Family
ID=14303855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2101562A Pending JPH042154A (en) | 1990-04-19 | 1990-04-19 | Method of packaging semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH042154A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3059465A1 (en) * | 2016-11-30 | 2018-06-01 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | MICROELECTRONIC SYSTEM WITH HEAT DISSIPATION |
-
1990
- 1990-04-19 JP JP2101562A patent/JPH042154A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3059465A1 (en) * | 2016-11-30 | 2018-06-01 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | MICROELECTRONIC SYSTEM WITH HEAT DISSIPATION |
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