FR3024930A1 - - Google Patents
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- Publication number
- FR3024930A1 FR3024930A1 FR1457764A FR1457764A FR3024930A1 FR 3024930 A1 FR3024930 A1 FR 3024930A1 FR 1457764 A FR1457764 A FR 1457764A FR 1457764 A FR1457764 A FR 1457764A FR 3024930 A1 FR3024930 A1 FR 3024930A1
- Authority
- FR
- France
- Prior art keywords
- data
- circuit
- transmission line
- voltage levels
- values
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 98
- 230000000630 rising effect Effects 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 9
- 238000001514 detection method Methods 0.000 claims description 2
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 22
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 22
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 18
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 12
- 230000008901 benefit Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 102000010954 Link domains Human genes 0.000 description 1
- 108050001157 Link domains Proteins 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/54—Systems for transmission via power distribution lines
- H04B3/548—Systems for transmission via power distribution lines the power on the line being DC
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Dc Digital Transmission (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1457764A FR3024930B1 (fr) | 2014-08-12 | 2014-08-12 | Liaison serie a haut debit |
| US14/821,053 US9571160B2 (en) | 2014-08-12 | 2015-08-07 | High data rate serial link |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1457764A FR3024930B1 (fr) | 2014-08-12 | 2014-08-12 | Liaison serie a haut debit |
| FR1457764 | 2014-08-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR3024930A1 true FR3024930A1 (enExample) | 2016-02-19 |
| FR3024930B1 FR3024930B1 (fr) | 2019-08-09 |
Family
ID=52130356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR1457764A Expired - Fee Related FR3024930B1 (fr) | 2014-08-12 | 2014-08-12 | Liaison serie a haut debit |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9571160B2 (enExample) |
| FR (1) | FR3024930B1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10673477B2 (en) * | 2015-10-21 | 2020-06-02 | Tendyron Corporation | Communication device, adapter device, communication system |
| CN107769782A (zh) * | 2017-11-06 | 2018-03-06 | 长沙曙通信息科技有限公司 | 一种新型多路复用模拟数字转换器装置 |
| FR3089370B1 (fr) * | 2018-11-29 | 2020-11-27 | Teledyne E2V Semiconductors Sas | Dispositif de génération de signaux analogiques |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0407031A2 (en) * | 1989-07-06 | 1991-01-09 | Advanced Micro Devices, Inc. | Apparatus for transmitting digital data in analog form |
| US20050231399A1 (en) * | 2004-04-15 | 2005-10-20 | Fowler Michael L | Sending and/or receiving serial data with bit timing and parallel data conversion |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4410879A (en) * | 1980-10-31 | 1983-10-18 | Tektronix, Inc. | High resolution digital-to-analog converter |
| JP3951441B2 (ja) * | 1998-04-28 | 2007-08-01 | ソニー株式会社 | 符号状態判定方法および符号化装置 |
| EP1098463B1 (en) * | 1999-05-21 | 2007-10-24 | Fujitsu Limited | Digital subscriber's line transmitting method and device |
| US7206149B2 (en) * | 2001-06-28 | 2007-04-17 | Stmicroelectronics, Inc. | Circuit and method for detecting a spin-up wedge and a corresponding servo wedge on spin up of a data-storage disk |
| CN1739265A (zh) * | 2003-10-17 | 2006-02-22 | 松下电器产业株式会社 | 数据传输系统、数据传输设备及其方法 |
| US7221298B1 (en) * | 2005-12-08 | 2007-05-22 | Teradyne, Inc. | Calibration circuitry |
| EP2204936A1 (en) * | 2007-10-01 | 2010-07-07 | Panasonic Corporation | Wireless communication device and circular buffer control method |
| US8599941B2 (en) * | 2008-10-31 | 2013-12-03 | Kochi University Of Technology | Data transmission system and method |
-
2014
- 2014-08-12 FR FR1457764A patent/FR3024930B1/fr not_active Expired - Fee Related
-
2015
- 2015-08-07 US US14/821,053 patent/US9571160B2/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0407031A2 (en) * | 1989-07-06 | 1991-01-09 | Advanced Micro Devices, Inc. | Apparatus for transmitting digital data in analog form |
| US20050231399A1 (en) * | 2004-04-15 | 2005-10-20 | Fowler Michael L | Sending and/or receiving serial data with bit timing and parallel data conversion |
Non-Patent Citations (2)
| Title |
|---|
| I-HSIN WANG ET AL: "A 4-bit 10GSample/sec flash ADC with merged interpolation and reference voltage", SOLID-STATE CIRCUITS CONFERENCE, 2008. A-SSCC '08. IEEE ASIAN, IEEE, PISCATAWAY, NJ, USA, 3 November 2008 (2008-11-03), pages 377 - 380, XP031373041, ISBN: 978-1-4244-2604-1 * |
| MUNEHIKO NAGATANI ET AL: "A 32-GS/s 6-Bit Double-Sampling DAC in InP HBT Technology", COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT SYMPOSIUM, 2009. CISC 2009. ANNUAL IEEE, IEEE, PISCATAWAY, NJ, USA, 11 October 2009 (2009-10-11), pages 1 - 4, XP031560501, ISBN: 978-1-4244-5191-3 * |
Also Published As
| Publication number | Publication date |
|---|---|
| US20160049992A1 (en) | 2016-02-18 |
| FR3024930B1 (fr) | 2019-08-09 |
| US9571160B2 (en) | 2017-02-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PLFP | Fee payment |
Year of fee payment: 2 |
|
| PLSC | Publication of the preliminary search report |
Effective date: 20160219 |
|
| PLFP | Fee payment |
Year of fee payment: 3 |
|
| PLFP | Fee payment |
Year of fee payment: 4 |
|
| PLFP | Fee payment |
Year of fee payment: 5 |
|
| PLFP | Fee payment |
Year of fee payment: 6 |
|
| PLFP | Fee payment |
Year of fee payment: 7 |
|
| ST | Notification of lapse |
Effective date: 20220405 |