FR2978867B1 - Resistance ajustable - Google Patents

Resistance ajustable

Info

Publication number
FR2978867B1
FR2978867B1 FR1157056A FR1157056A FR2978867B1 FR 2978867 B1 FR2978867 B1 FR 2978867B1 FR 1157056 A FR1157056 A FR 1157056A FR 1157056 A FR1157056 A FR 1157056A FR 2978867 B1 FR2978867 B1 FR 2978867B1
Authority
FR
France
Prior art keywords
adjustable resistance
adjustable
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1157056A
Other languages
English (en)
Other versions
FR2978867A1 (fr
Inventor
Pascal Fornara
Arnaud Regnier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1157056A priority Critical patent/FR2978867B1/fr
Priority to US13/552,973 priority patent/US8729668B2/en
Publication of FR2978867A1 publication Critical patent/FR2978867A1/fr
Application granted granted Critical
Publication of FR2978867B1 publication Critical patent/FR2978867B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
FR1157056A 2011-08-01 2011-08-01 Resistance ajustable Expired - Fee Related FR2978867B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1157056A FR2978867B1 (fr) 2011-08-01 2011-08-01 Resistance ajustable
US13/552,973 US8729668B2 (en) 2011-08-01 2012-07-19 Adjustable resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1157056A FR2978867B1 (fr) 2011-08-01 2011-08-01 Resistance ajustable

Publications (2)

Publication Number Publication Date
FR2978867A1 FR2978867A1 (fr) 2013-02-08
FR2978867B1 true FR2978867B1 (fr) 2014-03-21

Family

ID=45592484

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1157056A Expired - Fee Related FR2978867B1 (fr) 2011-08-01 2011-08-01 Resistance ajustable

Country Status (2)

Country Link
US (1) US8729668B2 (fr)
FR (1) FR2978867B1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3084521B1 (fr) * 2018-07-25 2020-08-14 Stmicroelectronics Rousset Procede de protection d'un module de circuit integre et dispositif correspondant
FR3084520B1 (fr) 2018-07-25 2020-08-14 Stmicroelectronics Rousset Procede de protection d'un circuit integre, et dispositif correspondant
FR3084492A1 (fr) 2018-07-30 2020-01-31 Stmicroelectronics (Rousset) Sas Procede de detection d'une attaque par un faisceau de particules electriquement chargees sur un circuit integre, et circuit integre correspondant
FR3093591B1 (fr) * 2019-03-06 2021-04-02 St Microelectronics Rousset Procédé de fabrication d’un élément capacitif haute tension, et circuit intégré correspondant
FR3099259B1 (fr) 2019-07-24 2021-08-13 St Microelectronics Rousset Procédé de protection de données stockées dans une mémoire, et circuit intégré correspondant

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3526701B2 (ja) * 1995-08-24 2004-05-17 セイコーインスツルメンツ株式会社 半導体装置
US5952695A (en) * 1997-03-05 1999-09-14 International Business Machines Corporation Silicon-on-insulator and CMOS-on-SOI double film structures
US6319783B1 (en) * 1999-11-19 2001-11-20 Chartered Semiconductor Manufatcuring Ltd. Process to fabricate a novel source-drain extension
JP4966466B2 (ja) * 2000-03-13 2012-07-04 公益財団法人国際科学振興財団 酸化膜の形成方法、酸化膜のスパッタリング方法、酸窒化膜のスパッタリング方法、ゲート絶縁膜の形成方法
KR20040079509A (ko) * 2003-03-07 2004-09-16 삼성전자주식회사 저항 소자를 구비하는 반도체 장치 및 그 제조 방법
US20050116301A1 (en) * 2003-12-01 2005-06-02 Shaw Jonathan A. High performance voltage controlled poly resistor for mixed signal and RF applications
US8009011B2 (en) * 2007-06-29 2011-08-30 Semtech Corporation Electrically adjustable resistor
FR2931289A1 (fr) * 2008-05-13 2009-11-20 St Microelectronics Rousset Memoire a structure du type eeprom et a lecture seule
EP2264759B1 (fr) * 2009-06-17 2012-07-04 STMicroelectronics (Rousset) SAS Elément d'identification d'une puce de circuit intégré

Also Published As

Publication number Publication date
US20130032926A1 (en) 2013-02-07
FR2978867A1 (fr) 2013-02-08
US8729668B2 (en) 2014-05-20

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20150430