FR2881564B1 - Circuit integre de memoire, en particulier de memoire sram et procede de fabrication correspondant - Google Patents

Circuit integre de memoire, en particulier de memoire sram et procede de fabrication correspondant

Info

Publication number
FR2881564B1
FR2881564B1 FR0501037A FR0501037A FR2881564B1 FR 2881564 B1 FR2881564 B1 FR 2881564B1 FR 0501037 A FR0501037 A FR 0501037A FR 0501037 A FR0501037 A FR 0501037A FR 2881564 B1 FR2881564 B1 FR 2881564B1
Authority
FR
France
Prior art keywords
corresponding manufacturing
memory circuit
memory
integrated
especially sram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0501037A
Other languages
English (en)
Other versions
FR2881564A1 (fr
Inventor
Francois Jacquet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0501037A priority Critical patent/FR2881564B1/fr
Priority to US11/343,920 priority patent/US7569889B2/en
Publication of FR2881564A1 publication Critical patent/FR2881564A1/fr
Application granted granted Critical
Publication of FR2881564B1 publication Critical patent/FR2881564B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
FR0501037A 2005-02-02 2005-02-02 Circuit integre de memoire, en particulier de memoire sram et procede de fabrication correspondant Expired - Fee Related FR2881564B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0501037A FR2881564B1 (fr) 2005-02-02 2005-02-02 Circuit integre de memoire, en particulier de memoire sram et procede de fabrication correspondant
US11/343,920 US7569889B2 (en) 2005-02-02 2006-01-30 Memory integrated circuit, in particular an SRAM memory integrated circuit, and corresponding fabrication process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0501037A FR2881564B1 (fr) 2005-02-02 2005-02-02 Circuit integre de memoire, en particulier de memoire sram et procede de fabrication correspondant

Publications (2)

Publication Number Publication Date
FR2881564A1 FR2881564A1 (fr) 2006-08-04
FR2881564B1 true FR2881564B1 (fr) 2007-06-01

Family

ID=35094390

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0501037A Expired - Fee Related FR2881564B1 (fr) 2005-02-02 2005-02-02 Circuit integre de memoire, en particulier de memoire sram et procede de fabrication correspondant

Country Status (2)

Country Link
US (1) US7569889B2 (fr)
FR (1) FR2881564B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11710698B2 (en) * 2020-09-24 2023-07-25 Advanced Micro Devices, Inc. Dual-track bitline scheme for 6T SRAM cells
US11437316B2 (en) 2020-09-24 2022-09-06 Advanced Micro Devices, Inc. Folded cell layout for 6T SRAM cell

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69121503T2 (de) * 1990-09-29 1997-02-13 Nippon Electric Co Halbleiterspeicheranordnung mit einer rauscharmen Abfühlstruktur
EP0593152B1 (fr) * 1992-10-14 2000-12-27 Sun Microsystems, Inc. Conception de mémoire à accès aléatoire
US5986914A (en) * 1993-03-31 1999-11-16 Stmicroelectronics, Inc. Active hierarchical bitline memory architecture
JP3938808B2 (ja) * 1997-12-26 2007-06-27 株式会社ルネサステクノロジ 半導体記憶装置
JP3860403B2 (ja) * 2000-09-25 2006-12-20 株式会社東芝 半導体メモリ装置
US6430076B1 (en) * 2001-09-26 2002-08-06 Infineon Technologies Ag Multi-level signal lines with vertical twists
US6657880B1 (en) * 2002-12-04 2003-12-02 Virtual Silicon Technology, Inc. SRAM bit line architecture

Also Published As

Publication number Publication date
US7569889B2 (en) 2009-08-04
US20060187702A1 (en) 2006-08-24
FR2881564A1 (fr) 2006-08-04

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20121031