FR2878072B1 - Structure multicouche comprenant un substrat portant une couche heteroepitaxiale de silicium et germanium, et procede pour sa fabrication. - Google Patents

Structure multicouche comprenant un substrat portant une couche heteroepitaxiale de silicium et germanium, et procede pour sa fabrication.

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Publication number
FR2878072B1
FR2878072B1 FR0511147A FR0511147A FR2878072B1 FR 2878072 B1 FR2878072 B1 FR 2878072B1 FR 0511147 A FR0511147 A FR 0511147A FR 0511147 A FR0511147 A FR 0511147A FR 2878072 B1 FR2878072 B1 FR 2878072B1
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FR
France
Prior art keywords
silicon
layer
germanium
multilayer structure
manufacturing
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Application number
FR0511147A
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English (en)
Other versions
FR2878072A1 (fr
Inventor
Peter Storck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siltronic AG
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Siltronic AG
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Publication date
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Publication of FR2878072A1 publication Critical patent/FR2878072A1/fr
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Publication of FR2878072B1 publication Critical patent/FR2878072B1/fr
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Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

La structure multicouche obtenue selon le procédé de l'invention comprend un substrat portant une couche hétéroépitaxiale de silicium et de germanium (couche SiGe) de composition globale Si1-xGex et ayant un paramètre de maille qui diffère du paramètre de maille du silicium, de même qu'une couche mince piège, de composition globale Si1-yGey, déposée sur la couche SiGe et reliant des dislocations vis, et au moins une autre couche déposée sur la couche piège.
FR0511147A 2004-11-04 2005-11-02 Structure multicouche comprenant un substrat portant une couche heteroepitaxiale de silicium et germanium, et procede pour sa fabrication. Active FR2878072B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102004053307A DE102004053307B4 (de) 2004-11-04 2004-11-04 Mehrschichtenstruktur umfassend ein Substrat und eine darauf heteroepitaktisch abgeschiedene Schicht aus Silicium und Germanium und ein Verfahren zu deren Herstellung

Publications (2)

Publication Number Publication Date
FR2878072A1 FR2878072A1 (fr) 2006-05-19
FR2878072B1 true FR2878072B1 (fr) 2011-07-22

Family

ID=36217127

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0511147A Active FR2878072B1 (fr) 2004-11-04 2005-11-02 Structure multicouche comprenant un substrat portant une couche heteroepitaxiale de silicium et germanium, et procede pour sa fabrication.

Country Status (6)

Country Link
US (2) US7723214B2 (fr)
JP (1) JP4700472B2 (fr)
KR (1) KR100797131B1 (fr)
CN (1) CN100580893C (fr)
DE (1) DE102004053307B4 (fr)
FR (1) FR2878072B1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008062685A1 (de) * 2008-12-17 2010-06-24 Siltronic Ag Halbleiterscheibe mit einer SiGe-Schicht und Verfahren zur Herstellung der SiGe-Schicht
CN102117741B (zh) * 2010-01-06 2013-03-13 上海华虹Nec电子有限公司 改善锗硅或锗硅碳单晶与多晶交界面形貌的方法
US20150194307A1 (en) * 2014-01-06 2015-07-09 Globalfoundries Inc. Strained fin structures and methods of fabrication
US9752224B2 (en) * 2015-08-05 2017-09-05 Applied Materials, Inc. Structure for relaxed SiGe buffers including method and apparatus for forming
US9922941B1 (en) 2016-09-21 2018-03-20 International Business Machines Corporation Thin low defect relaxed silicon germanium layers on bulk silicon substrates
US10535516B2 (en) * 2018-02-01 2020-01-14 Asm Ip Holdings B.V. Method for depositing a semiconductor structure on a surface of a substrate and related semiconductor structures
CN110265402B (zh) * 2019-06-27 2020-09-18 长江存储科技有限责任公司 一种3d nand存储器件及其制造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5442205A (en) * 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
CA2062134C (fr) 1991-05-31 1997-03-25 Ibm Couches hétéroépitaxiales à faible densité de défauts et parmètre de réseau arbitraire
EP1016129B2 (fr) * 1997-06-24 2009-06-10 Massachusetts Institute Of Technology Regulation des densites de dislocation filetees au moyen de couches a teneur echelonnee et d'une planarisation
JP3324573B2 (ja) * 1999-07-19 2002-09-17 日本電気株式会社 半導体装置の製造方法および製造装置
US6524935B1 (en) 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
JP4221928B2 (ja) 2001-12-28 2009-02-12 株式会社Ｓｕｍｃｏ 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法
US6515335B1 (en) * 2002-01-04 2003-02-04 International Business Machines Corporation Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
US6562703B1 (en) 2002-03-13 2003-05-13 Sharp Laboratories Of America, Inc. Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7008857B2 (en) * 2002-08-26 2006-03-07 S.O.I.Tec Silicon On Insulator Technologies S.A. Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom
US8187377B2 (en) 2002-10-04 2012-05-29 Silicon Genesis Corporation Non-contact etch annealing of strained layers
EP1588406B1 (fr) * 2003-01-27 2019-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Structures a semi-conducteur a homogeneite structurelle
JP4306266B2 (ja) 2003-02-04 2009-07-29 株式会社Ｓｕｍｃｏ 半導体基板の製造方法
EP1602125B1 (fr) * 2003-03-07 2019-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Procede d'isolation par tranchee peu profonde
WO2004081986A2 (fr) * 2003-03-12 2004-09-23 Asm America Inc. Procede de planarisation et de reduction de la densite des defauts du silicium germanium
US6882025B2 (en) * 2003-04-25 2005-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Strained-channel transistor and methods of manufacture
US6831350B1 (en) * 2003-10-02 2004-12-14 Freescale Semiconductor, Inc. Semiconductor structure with different lattice constant materials and method for forming the same
US6902965B2 (en) * 2003-10-31 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Strained silicon structure
JP2006108365A (ja) * 2004-10-05 2006-04-20 Renesas Technology Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
JP2006135329A (ja) 2006-05-25
FR2878072A1 (fr) 2006-05-19
KR100797131B1 (ko) 2008-01-22
CN100580893C (zh) 2010-01-13
DE102004053307A1 (de) 2006-05-11
DE102004053307B4 (de) 2010-01-07
US7723214B2 (en) 2010-05-25
US20060091502A1 (en) 2006-05-04
CN1773686A (zh) 2006-05-17
US20100019278A1 (en) 2010-01-28
KR20060049306A (ko) 2006-05-18
JP4700472B2 (ja) 2011-06-15

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