FR2875352B1 - Procede de detection et de correction d'erreurs pour une memoire et circuit integre correspondant - Google Patents

Procede de detection et de correction d'erreurs pour une memoire et circuit integre correspondant

Info

Publication number
FR2875352B1
FR2875352B1 FR0409650A FR0409650A FR2875352B1 FR 2875352 B1 FR2875352 B1 FR 2875352B1 FR 0409650 A FR0409650 A FR 0409650A FR 0409650 A FR0409650 A FR 0409650A FR 2875352 B1 FR2875352 B1 FR 2875352B1
Authority
FR
France
Prior art keywords
detecting
memory
integrated circuit
correcting errors
corresponding integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0409650A
Other languages
English (en)
Other versions
FR2875352A1 (fr
Inventor
Philippe Gendrier
Philippe Candelier
Richard Fournel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0409650A priority Critical patent/FR2875352B1/fr
Priority to US11/220,515 priority patent/US7502985B2/en
Publication of FR2875352A1 publication Critical patent/FR2875352A1/fr
Application granted granted Critical
Publication of FR2875352B1 publication Critical patent/FR2875352B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
FR0409650A 2004-09-10 2004-09-10 Procede de detection et de correction d'erreurs pour une memoire et circuit integre correspondant Expired - Fee Related FR2875352B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0409650A FR2875352B1 (fr) 2004-09-10 2004-09-10 Procede de detection et de correction d'erreurs pour une memoire et circuit integre correspondant
US11/220,515 US7502985B2 (en) 2004-09-10 2005-09-07 Method of detecting and correcting errors for a memory and corresponding integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0409650A FR2875352B1 (fr) 2004-09-10 2004-09-10 Procede de detection et de correction d'erreurs pour une memoire et circuit integre correspondant

Publications (2)

Publication Number Publication Date
FR2875352A1 FR2875352A1 (fr) 2006-03-17
FR2875352B1 true FR2875352B1 (fr) 2007-05-11

Family

ID=34949632

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0409650A Expired - Fee Related FR2875352B1 (fr) 2004-09-10 2004-09-10 Procede de detection et de correction d'erreurs pour une memoire et circuit integre correspondant

Country Status (2)

Country Link
US (1) US7502985B2 (fr)
FR (1) FR2875352B1 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100707200B1 (ko) * 2005-07-22 2007-04-13 삼성전자주식회사 핀-타입 채널 영역을 갖는 비휘발성 메모리 소자 및 그제조 방법
KR100802059B1 (ko) * 2006-09-06 2008-02-12 삼성전자주식회사 읽기 디스터브로 인한 배드 블록의 생성을 억제할 수 있는메모리 시스템 및 그것의 동작 방법
KR100826500B1 (ko) * 2006-10-23 2008-05-02 삼성전자주식회사 비휘발성 반도체 메모리 장치 및 상기 비휘발성 반도체메모리 장치의 데이터 복구 방법
KR101403314B1 (ko) 2008-05-23 2014-06-05 삼성전자주식회사 메모리 장치 및 데이터 비트 저장 방법
KR101423052B1 (ko) * 2008-06-12 2014-07-25 삼성전자주식회사 메모리 장치 및 읽기 레벨 제어 방법
TW201212035A (en) * 2010-09-10 2012-03-16 Jmicron Technology Corp Access method of volatile memory and access apparatus of volatile memory
CN106571167B (zh) * 2016-11-09 2020-01-10 上海华虹集成电路有限责任公司 嵌入式eeprom的“读”测试基准建立方法
US10158380B2 (en) 2016-12-06 2018-12-18 Sandisk Technologies Llc ECC and read adjustment based on dynamic memory error model estimation
US10374639B2 (en) 2016-12-06 2019-08-06 Western Digital Technologies, Inc. Adaptive bit-flipping decoder based on dynamic error information
US10284233B2 (en) * 2016-12-06 2019-05-07 Western Digital Technologies, Inc. ECC adjustment based on dynamic error information
US11838127B2 (en) * 2022-03-11 2023-12-05 Hughes Network Systems, Llc Adaptive satellite communications

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3623155A (en) * 1969-12-24 1971-11-23 Ibm Optimum apparatus and method for check bit generation and error detection, location and correction
JP3542002B2 (ja) * 1996-09-24 2004-07-14 株式会社ルネサステクノロジ システム
US6505305B1 (en) * 1998-07-16 2003-01-07 Compaq Information Technologies Group, L.P. Fail-over of multiple memory blocks in multiple memory modules in computer system
US6604222B1 (en) * 1999-04-30 2003-08-05 Rockwell Collins, Inc. Block code to efficiently correct adjacent data and/or check bit errors
WO2001076077A2 (fr) * 2000-03-31 2001-10-11 Ted Szymanski Emetteur, recepteur et schema de codage concus pour augmenter le debit de donnees et diminuer le taux d'erreur sur les bits d'une liaison de donnees optique
JP4250325B2 (ja) * 2000-11-01 2009-04-08 株式会社東芝 半導体記憶装置
US6691252B2 (en) * 2001-02-23 2004-02-10 Hewlett-Packard Development Company, L.P. Cache test sequence for single-ported row repair CAM
US6373758B1 (en) * 2001-02-23 2002-04-16 Hewlett-Packard Company System and method of operating a programmable column fail counter for redundancy allocation
US7036068B2 (en) * 2001-07-25 2006-04-25 Hewlett-Packard Development Company, L.P. Error correction coding and decoding in a solid-state storage device
US20030023922A1 (en) * 2001-07-25 2003-01-30 Davis James A. Fault tolerant magnetoresistive solid-state storage device
US6961890B2 (en) * 2001-08-16 2005-11-01 Hewlett-Packard Development Company, L.P. Dynamic variable-length error correction code
US7171594B2 (en) * 2002-03-06 2007-01-30 Hewlett-Packard Development Company, L.P. Pausing a transfer of data
US6829167B2 (en) * 2002-12-12 2004-12-07 Sandisk Corporation Error recovery for nonvolatile memory
JP4299558B2 (ja) * 2003-03-17 2009-07-22 株式会社ルネサステクノロジ 情報記憶装置および情報処理システム
JP2004288311A (ja) * 2003-03-24 2004-10-14 Toshiba Corp 半導体記憶装置及びその制御方法
US6868022B2 (en) * 2003-03-28 2005-03-15 Matrix Semiconductor, Inc. Redundant memory structure using bad bit pointers
US6704230B1 (en) * 2003-06-12 2004-03-09 International Business Machines Corporation Error detection and correction method and apparatus in a magnetoresistive random access memory
US6751147B1 (en) * 2003-08-05 2004-06-15 Hewlett-Packard Development Company, L.P. Method for adaptively writing a magnetic random access memory
US7006388B2 (en) * 2003-08-28 2006-02-28 Hewlett-Packard Development Company, L.P. Memory with reference-initiated sequential sensing
US7210077B2 (en) * 2004-01-29 2007-04-24 Hewlett-Packard Development Company, L.P. System and method for configuring a solid-state storage device with error correction coding

Also Published As

Publication number Publication date
US20060075320A1 (en) 2006-04-06
US7502985B2 (en) 2009-03-10
FR2875352A1 (fr) 2006-03-17

Similar Documents

Publication Publication Date Title
FR2875352B1 (fr) Procede de detection et de correction d'erreurs pour une memoire et circuit integre correspondant
FI20051330A (fi) Menetelmä navigointitietojen virheiden havaitesemiseksi
FR2885140B1 (fr) Procede de detection et de caracterisation de microorgarnismes sur une membrane.
FR2898194B1 (fr) Procede de determination d'une lentille ophtalmique progressive.
FR2868158B1 (fr) Procede d'exrapolation d'une position angulaire de rotation
DE602004031685D1 (de) Fehlererkennungsvorrichtung für Drehwinkelsensor
IL170574A (en) Method for measuring force-dependent gyroscope sensitivity
ID30094A (id) Peralatan untuk mendeteksi kesalahan pembacaan
EP1793200A4 (fr) Traitement de direction, procédé de traitement de direction, programme de traitement de direction, instrument de mesure de direction, procédé de correction du décalage d'inclinaison, procédé de mesure de direction, capteur de direction et dispositif électronique p
FR2884336B1 (fr) Dispositif et procede pour calculer une representation d'un operande de resultat.
FR2907695B1 (fr) Procede de percage d'un alesage et machine correspondante.
GB0523167D0 (en) System and method for detecting and correcting defective pixels in a digital image sensor
FR2901422B1 (fr) Module electronique destine a etre integre dans un pneumatique, dispositif comprenant un tel module, pneumatique muni d'un tel dispositif et procede d'obtention d'un tel dispositif
FR2884645B1 (fr) Procede de realisation d'un circuit integre comprenant un condensateur
NO20020648D0 (no) Automatisk system for måling av fysiske parametere i rör
FR2821932B1 (fr) Procede et dispositif de detection de defaillance pour un reseau de capteurs
DE50208390D1 (de) Verfahren und Druckmaschine zum Ermitteln von Registerfehlern
DE50208478D1 (de) Verfahren und Druckmaschine zum Ermitteln von Registerfehlern
DE10394047D2 (de) Verfahren zur Erkennung und/oder Korrektur von Speicherzugriffsfehlern und elektronische Schaltungsanordnung zur Durchführung des Verfahrens
SG120995A1 (en) A method and apparatus for determining asymmetry in an image
DE50111323D1 (de) Schaltungsanordnung zur erkennung eines fehlerzustands
WO2005039173A3 (fr) Procede et conception permettant l'utilisation des sorties multiples d'un capteur d'images
FR2860586B1 (fr) Procede et agencement de circuit pour la correction du decalage d'un pont de mesure
FR2858085B1 (fr) Circuit de detection pour carte a puce et procede de detection de falsification de carte a puce
DE50300455D1 (de) Koordinatenmessmaschine und Fehlerkorrekturverfahren

Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20090529