FR2873833B1 - Debogueur d'un circuit electronique fabrique a partir d'un programme en langage de description de materiel - Google Patents

Debogueur d'un circuit electronique fabrique a partir d'un programme en langage de description de materiel

Info

Publication number
FR2873833B1
FR2873833B1 FR0451716A FR0451716A FR2873833B1 FR 2873833 B1 FR2873833 B1 FR 2873833B1 FR 0451716 A FR0451716 A FR 0451716A FR 0451716 A FR0451716 A FR 0451716A FR 2873833 B1 FR2873833 B1 FR 2873833B1
Authority
FR
France
Prior art keywords
debugging
language
program
equipment
description
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0451716A
Other languages
English (en)
Other versions
FR2873833A1 (fr
Inventor
Pierre Colle
Olivier Potin
Anne Wantens
Yves Devigne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Temento Systems
Original Assignee
Temento Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Temento Systems filed Critical Temento Systems
Priority to FR0451716A priority Critical patent/FR2873833B1/fr
Priority to JP2005213324A priority patent/JP2006048677A/ja
Priority to US11/187,627 priority patent/US7458042B2/en
Publication of FR2873833A1 publication Critical patent/FR2873833A1/fr
Application granted granted Critical
Publication of FR2873833B1 publication Critical patent/FR2873833B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
FR0451716A 2004-07-29 2004-07-29 Debogueur d'un circuit electronique fabrique a partir d'un programme en langage de description de materiel Expired - Fee Related FR2873833B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR0451716A FR2873833B1 (fr) 2004-07-29 2004-07-29 Debogueur d'un circuit electronique fabrique a partir d'un programme en langage de description de materiel
JP2005213324A JP2006048677A (ja) 2004-07-29 2005-07-22 電子回路をデバッグするデバイス及び方法
US11/187,627 US7458042B2 (en) 2004-07-29 2005-07-22 Debugger of an electric circuit manufactured based on a program in hardware description language

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0451716A FR2873833B1 (fr) 2004-07-29 2004-07-29 Debogueur d'un circuit electronique fabrique a partir d'un programme en langage de description de materiel

Publications (2)

Publication Number Publication Date
FR2873833A1 FR2873833A1 (fr) 2006-02-03
FR2873833B1 true FR2873833B1 (fr) 2006-10-13

Family

ID=34949160

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0451716A Expired - Fee Related FR2873833B1 (fr) 2004-07-29 2004-07-29 Debogueur d'un circuit electronique fabrique a partir d'un programme en langage de description de materiel

Country Status (3)

Country Link
US (1) US7458042B2 (fr)
JP (1) JP2006048677A (fr)
FR (1) FR2873833B1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101191819B (zh) * 2006-11-21 2012-05-23 国际商业机器公司 Fpga、fpga配置、调试系统和方法
US9117043B1 (en) * 2012-06-14 2015-08-25 Xilinx, Inc. Net sensitivity ranges for detection of simulation events
EP2977894B1 (fr) * 2014-07-21 2018-09-12 dSPACE digital signal processing and control engineering GmbH Création d'un code FPGA ayant une structure d'influence automatiquement insérée
EP3001318A1 (fr) * 2014-09-24 2016-03-30 dSPACE digital signal processing and control engineering GmbH Détermination de signaux pour collationnement de FPGA
US9929734B2 (en) * 2015-09-08 2018-03-27 Dspace Digital Signal Processing And Control Engineering Gmbh Method for changing the configuration of a programmable logic module
JP7483165B1 (ja) 2023-05-16 2024-05-14 三菱電機株式会社 集積回路試験システム、集積回路試験装置、集積回路試験方法、及びプログラム

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5903466A (en) * 1995-12-29 1999-05-11 Synopsys, Inc. Constraint driven insertion of scan logic for implementing design for test within an integrated circuit design
US6823497B2 (en) * 1999-11-30 2004-11-23 Synplicity, Inc. Method and user interface for debugging an electronic system
US7222315B2 (en) * 2000-11-28 2007-05-22 Synplicity, Inc. Hardware-based HDL code coverage and design analysis
US6973631B2 (en) * 2002-07-18 2005-12-06 Incentia Design Systems Corp. Scan insertion with bypass login in an IC design

Also Published As

Publication number Publication date
US7458042B2 (en) 2008-11-25
FR2873833A1 (fr) 2006-02-03
US20060064678A1 (en) 2006-03-23
JP2006048677A (ja) 2006-02-16

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