FR2868563B1 - Dispositif et procede capables de detecter un etat du bois en vue de regler une horloge - Google Patents
Dispositif et procede capables de detecter un etat du bois en vue de regler une horlogeInfo
- Publication number
- FR2868563B1 FR2868563B1 FR0450622A FR0450622A FR2868563B1 FR 2868563 B1 FR2868563 B1 FR 2868563B1 FR 0450622 A FR0450622 A FR 0450622A FR 0450622 A FR0450622 A FR 0450622A FR 2868563 B1 FR2868563 B1 FR 2868563B1
- Authority
- FR
- France
- Prior art keywords
- clock
- wood
- detecting
- setting
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Stored Programmes (AREA)
- Electric Clocks (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0450622A FR2868563B1 (fr) | 2004-03-30 | 2004-03-30 | Dispositif et procede capables de detecter un etat du bois en vue de regler une horloge |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0450622A FR2868563B1 (fr) | 2004-03-30 | 2004-03-30 | Dispositif et procede capables de detecter un etat du bois en vue de regler une horloge |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2868563A1 FR2868563A1 (fr) | 2005-10-07 |
FR2868563B1 true FR2868563B1 (fr) | 2006-06-09 |
Family
ID=34944296
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0450622A Expired - Fee Related FR2868563B1 (fr) | 2004-03-30 | 2004-03-30 | Dispositif et procede capables de detecter un etat du bois en vue de regler une horloge |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2868563B1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2904129B1 (fr) * | 2006-07-21 | 2008-09-26 | Thales Sa | Coeur processeur a frequence pilotee et procede de demarrage dudit coeur processeur dans un mode programme |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6269443B1 (en) * | 1998-12-29 | 2001-07-31 | Intel Corporation | Method and apparatus for automatically selecting CPU clock frequency multiplier |
US6457137B1 (en) * | 1999-05-28 | 2002-09-24 | 3Com Corporation | Method for configuring clock ratios in a microprocessor |
JP3970474B2 (ja) * | 1999-05-31 | 2007-09-05 | 沖電気工業株式会社 | クロック信号発生回路及びそのクロック周波数調整方法 |
-
2004
- 2004-03-30 FR FR0450622A patent/FR2868563B1/fr not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2868563A1 (fr) | 2005-10-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2003067350A3 (fr) | Appareil et procede permettant d'effectuer simultanement une surveillance, une journalisation, et une commande d'un procede industriel | |
US7240222B1 (en) | Using ACPI power button signal for remotely controlling the power of a PC | |
US7676667B2 (en) | Boot control apparatus and method | |
DE60206257T2 (de) | Verfahren und vorrichtung zum abschalten und/oder neustarten von logischen partitionen in einem datenverarbeitungssystem | |
KR970051293A (ko) | 디램(dram) 시스템, 디램(dram) 시스템의 동작방법 | |
JP2012512555A5 (fr) | ||
TW200602848A (en) | Computer readable storage medium comprising a program product, recording medium, method, and information processing apparatus for controlling an execution mode of a CPU | |
JP2009528635A5 (fr) | ||
US8850175B2 (en) | Computer apparatus and resetting method for real time clock thereof | |
TW200622581A (en) | Error detecting memory module and method | |
TW200721039A (en) | Imaging system, processing method for the imaging system, and program for making computer execute the processing method | |
WO2007047167A3 (fr) | Rotateur rapide avec masquage incorpore et procede associe | |
WO2007002801A3 (fr) | Systeme et procede de commande de puissance dans un processeur multifils | |
TW200601351A (en) | Semiconductor memory device having test mode for data access time | |
DE602005020271D1 (de) | Hierarchische prozessorarchitektur zur videoverarbeitung | |
WO2007144808A3 (fr) | Procédé d'application d'une fréquence d'horloge à un processeur | |
FR2868563B1 (fr) | Dispositif et procede capables de detecter un etat du bois en vue de regler une horloge | |
KR960001949A (ko) | 스톱 클럭 제어장치와 그 방법 | |
TW201312510A (zh) | 警報偵測方法及其電腦裝置 | |
US7249275B2 (en) | Clock generating device and method for executing overclocking operation | |
ATE342493T1 (de) | Verfahren zum betätigen einer waage und waage | |
TWI719584B (zh) | 延遲追蹤方法以及記憶體系統 | |
KR100897277B1 (ko) | 반도체 메모리 장치의 지연 회로 | |
TW200700882A (en) | Display device and method for recovering from abnormal power-on therefor | |
JP2010271986A (ja) | オペレーションシステムのスタートアップ方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 13 |
|
PLFP | Fee payment |
Year of fee payment: 14 |
|
PLFP | Fee payment |
Year of fee payment: 15 |
|
ST | Notification of lapse |
Effective date: 20191106 |