FR2777697B1 - Circuit integre avec couche d'arret et procede de fabrication associe - Google Patents

Circuit integre avec couche d'arret et procede de fabrication associe

Info

Publication number
FR2777697B1
FR2777697B1 FR9804754A FR9804754A FR2777697B1 FR 2777697 B1 FR2777697 B1 FR 2777697B1 FR 9804754 A FR9804754 A FR 9804754A FR 9804754 A FR9804754 A FR 9804754A FR 2777697 B1 FR2777697 B1 FR 2777697B1
Authority
FR
France
Prior art keywords
manufacturing
integrated circuit
stop layer
stop
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9804754A
Other languages
English (en)
French (fr)
Other versions
FR2777697A1 (fr
Inventor
Christophe Verove
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR9804754A priority Critical patent/FR2777697B1/fr
Priority to EP99400744.1A priority patent/EP0951067B1/fr
Priority to JP10647399A priority patent/JP4717972B2/ja
Priority to US09/292,464 priority patent/US6410425B1/en
Publication of FR2777697A1 publication Critical patent/FR2777697A1/fr
Application granted granted Critical
Publication of FR2777697B1 publication Critical patent/FR2777697B1/fr
Priority to US10/144,944 priority patent/US20020127850A1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/086—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving buried masks
FR9804754A 1998-04-16 1998-04-16 Circuit integre avec couche d'arret et procede de fabrication associe Expired - Fee Related FR2777697B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR9804754A FR2777697B1 (fr) 1998-04-16 1998-04-16 Circuit integre avec couche d'arret et procede de fabrication associe
EP99400744.1A EP0951067B1 (fr) 1998-04-16 1999-03-26 Circuit intégré avec couche d'arrêt et procédé de fabrication associé
JP10647399A JP4717972B2 (ja) 1998-04-16 1999-04-14 集積回路の製造方法
US09/292,464 US6410425B1 (en) 1998-04-16 1999-04-15 Integrated circuit with stop layer and method of manufacturing the same
US10/144,944 US20020127850A1 (en) 1998-04-16 2002-05-13 Integrated circuit with stop layer and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9804754A FR2777697B1 (fr) 1998-04-16 1998-04-16 Circuit integre avec couche d'arret et procede de fabrication associe

Publications (2)

Publication Number Publication Date
FR2777697A1 FR2777697A1 (fr) 1999-10-22
FR2777697B1 true FR2777697B1 (fr) 2000-06-09

Family

ID=9525310

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9804754A Expired - Fee Related FR2777697B1 (fr) 1998-04-16 1998-04-16 Circuit integre avec couche d'arret et procede de fabrication associe

Country Status (4)

Country Link
US (2) US6410425B1 (https=)
EP (1) EP0951067B1 (https=)
JP (1) JP4717972B2 (https=)
FR (1) FR2777697B1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6309801B1 (en) * 1998-11-18 2001-10-30 U.S. Philips Corporation Method of manufacturing an electronic device comprising two layers of organic-containing material
US6313025B1 (en) * 1999-08-30 2001-11-06 Agere Systems Guardian Corp. Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit
US6812130B1 (en) * 2000-02-09 2004-11-02 Infineon Technologies Ag Self-aligned dual damascene etch using a polymer
KR100366621B1 (ko) * 2000-06-28 2003-01-09 삼성전자 주식회사 반도체 소자의 도전성 콘택체를 형성하는 방법
KR100434511B1 (ko) * 2002-08-12 2004-06-05 삼성전자주식회사 다마신 배선을 이용한 반도체 소자의 제조방법
JP2004274020A (ja) * 2002-09-24 2004-09-30 Rohm & Haas Electronic Materials Llc 電子デバイス製造
KR100538379B1 (ko) * 2003-11-11 2005-12-21 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03203240A (ja) * 1989-12-28 1991-09-04 Fujitsu Ltd 半導体装置の製造方法
FR2663784B1 (fr) * 1990-06-26 1997-01-31 Commissariat Energie Atomique Procede de realisation d'un etage d'un circuit integre.
JPH05326719A (ja) * 1992-05-27 1993-12-10 Oki Electric Ind Co Ltd 半導体素子の製造方法
JPH08139194A (ja) * 1994-04-28 1996-05-31 Texas Instr Inc <Ti> 半導体デバイス上に電気接続を作製する方法および該方法により作製された電気接続を有する半導体デバイス
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5736457A (en) * 1994-12-09 1998-04-07 Sematech Method of making a damascene metallization
JPH0964179A (ja) * 1995-08-25 1997-03-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
CN1075612C (zh) * 1996-01-11 2001-11-28 三菱自动车工业株式会社 汽车用换档装置
JPH09306988A (ja) * 1996-03-13 1997-11-28 Sony Corp 多層配線の形成方法
US5880018A (en) * 1996-10-07 1999-03-09 Motorola Inc. Method for manufacturing a low dielectric constant inter-level integrated circuit structure
JP3390329B2 (ja) * 1997-06-27 2003-03-24 日本電気株式会社 半導体装置およびその製造方法
JP3300643B2 (ja) * 1997-09-09 2002-07-08 株式会社東芝 半導体装置の製造方法
TW374946B (en) * 1997-12-03 1999-11-21 United Microelectronics Corp Definition of structure of dielectric layer patterns and the manufacturing method

Also Published As

Publication number Publication date
US20020127850A1 (en) 2002-09-12
US6410425B1 (en) 2002-06-25
JP2000003961A (ja) 2000-01-07
EP0951067A1 (fr) 1999-10-20
JP4717972B2 (ja) 2011-07-06
FR2777697A1 (fr) 1999-10-22
EP0951067B1 (fr) 2018-08-01

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20051230