FR2761529B1 - Memoire morte a structure non-et et procede de fabrication - Google Patents

Memoire morte a structure non-et et procede de fabrication

Info

Publication number
FR2761529B1
FR2761529B1 FR9707163A FR9707163A FR2761529B1 FR 2761529 B1 FR2761529 B1 FR 2761529B1 FR 9707163 A FR9707163 A FR 9707163A FR 9707163 A FR9707163 A FR 9707163A FR 2761529 B1 FR2761529 B1 FR 2761529B1
Authority
FR
France
Prior art keywords
structured
manufacturing
dead memory
dead
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9707163A
Other languages
English (en)
Other versions
FR2761529A1 (fr
Inventor
Jemmy Wen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from TW086103969A external-priority patent/TW335552B/zh
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Publication of FR2761529A1 publication Critical patent/FR2761529A1/fr
Application granted granted Critical
Publication of FR2761529B1 publication Critical patent/FR2761529B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/383—Channel doping programmed

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
FR9707163A 1997-03-27 1997-06-10 Memoire morte a structure non-et et procede de fabrication Expired - Fee Related FR2761529B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
TW086103969A TW335552B (en) 1997-03-27 1997-03-27 The structure and produce method of NAND gate logic armophorus silicon ROM
GB9710013A GB2325339B (en) 1997-03-27 1997-05-16 Nand-structured and amorphous silicon based read-only memory device and method of fabricating the same
SG1997001596A SG65651A1 (en) 1997-03-27 1997-05-19 Nand structured and amorphous silicon based read-only memory device and method of fabricating the same
NL1006264A NL1006264C2 (nl) 1997-03-27 1997-06-09 Nand-gestructureerde en amorf-silicium-gebaseerde alleen-uitlees-geheugeninrichting en werkwijze voor het fabriceren hiervan.

Publications (2)

Publication Number Publication Date
FR2761529A1 FR2761529A1 (fr) 1998-10-02
FR2761529B1 true FR2761529B1 (fr) 2000-07-28

Family

ID=27451648

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9707163A Expired - Fee Related FR2761529B1 (fr) 1997-03-27 1997-06-10 Memoire morte a structure non-et et procede de fabrication

Country Status (7)

Country Link
US (1) US5869373A (fr)
JP (1) JP3008185B2 (fr)
DE (1) DE19723652C2 (fr)
FR (1) FR2761529B1 (fr)
GB (1) GB2325339B (fr)
NL (1) NL1006264C2 (fr)
SG (1) SG65651A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4439602B2 (ja) * 1997-09-29 2010-03-24 株式会社東芝 半導体装置の製造方法
US6146949A (en) * 1998-06-25 2000-11-14 Acer Semiconductor Manufacturing Inc. Method of manufacturing mask ROM devices with self-aligned coding implant
US6794764B1 (en) * 2003-03-05 2004-09-21 Advanced Micro Devices, Inc. Charge-trapping memory arrays resistant to damage from contact hole information
US20080123405A1 (en) * 2006-08-18 2008-05-29 Mammen Thomas Implanted multi-bit NAND ROM
JP4300228B2 (ja) 2006-08-28 2009-07-22 株式会社東芝 不揮発性半導体記憶装置
US8648414B2 (en) 2011-07-01 2014-02-11 Micron Technology, Inc. Semiconductor structures including bodies of semiconductor material, devices including such structures and related methods

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04112570A (ja) * 1990-08-31 1992-04-14 Sony Corp マスクｒｏｍ
JPH04294582A (ja) * 1991-03-25 1992-10-19 Nippon Steel Corp 半導体装置の製造方法
CA2117933A1 (fr) * 1993-12-09 1995-06-10 Masakazu Shoji Memoire morte a grande densite
US5627091A (en) * 1994-06-01 1997-05-06 United Microelectronics Corporation Mask ROM process for making a ROM with a trench shaped channel
US5429988A (en) * 1994-06-13 1995-07-04 United Microelectronics Corporation Process for producing high density conductive lines
US5510287A (en) * 1994-11-01 1996-04-23 Taiwan Semiconductor Manuf. Company Method of making vertical channel mask ROM
US5550075A (en) * 1995-01-19 1996-08-27 United Microelectronics Corporation Ion implanted programmable cell for read only memory applications

Also Published As

Publication number Publication date
GB2325339B (en) 1999-03-31
GB9710013D0 (en) 1997-07-09
DE19723652A1 (de) 1998-10-01
JPH10275867A (ja) 1998-10-13
JP3008185B2 (ja) 2000-02-14
GB2325339A (en) 1998-11-18
NL1006264C2 (nl) 1998-12-10
SG65651A1 (en) 1999-06-22
FR2761529A1 (fr) 1998-10-02
US5869373A (en) 1999-02-09
DE19723652C2 (de) 2000-11-23

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Legal Events

Date Code Title Description
ST Notification of lapse