FR2720854B1 - Procédé de fabrication de dispositifs à semiconducteurs dotés d'un câblage en aluminium par gravure et chauffage sous vide. - Google Patents

Procédé de fabrication de dispositifs à semiconducteurs dotés d'un câblage en aluminium par gravure et chauffage sous vide.

Info

Publication number
FR2720854B1
FR2720854B1 FR9506356A FR9506356A FR2720854B1 FR 2720854 B1 FR2720854 B1 FR 2720854B1 FR 9506356 A FR9506356 A FR 9506356A FR 9506356 A FR9506356 A FR 9506356A FR 2720854 B1 FR2720854 B1 FR 2720854B1
Authority
FR
France
Prior art keywords
etching
under vacuum
semiconductor devices
heating under
manufacturing semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9506356A
Other languages
English (en)
Other versions
FR2720854A1 (fr
Inventor
Yasushige Abe
Fumihiko Akaboshi
Katsunori Shimizu
Tetsuo Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP5336321A external-priority patent/JPH07201854A/ja
Priority claimed from JP6029666A external-priority patent/JPH07240412A/ja
Priority claimed from JP6048848A external-priority patent/JPH07263414A/ja
Priority claimed from FR9415773A external-priority patent/FR2714527A1/fr
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of FR2720854A1 publication Critical patent/FR2720854A1/fr
Application granted granted Critical
Publication of FR2720854B1 publication Critical patent/FR2720854B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR9506356A 1993-12-28 1995-05-30 Procédé de fabrication de dispositifs à semiconducteurs dotés d'un câblage en aluminium par gravure et chauffage sous vide. Expired - Fee Related FR2720854B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP5336321A JPH07201854A (ja) 1993-12-28 1993-12-28 半導体装置の製造方法
JP6029666A JPH07240412A (ja) 1994-02-28 1994-02-28 半導体装置の製造方法
JP6048848A JPH07263414A (ja) 1994-03-18 1994-03-18 半導体装置の製造方法
FR9415773A FR2714527A1 (fr) 1993-12-28 1994-12-28 Procédé de fabrication de dispositifs à semiconducteur dotés d'un câblage en aluminium.

Publications (2)

Publication Number Publication Date
FR2720854A1 FR2720854A1 (fr) 1995-12-08
FR2720854B1 true FR2720854B1 (fr) 1998-04-24

Family

ID=27446935

Family Applications (2)

Application Number Title Priority Date Filing Date
FR9506356A Expired - Fee Related FR2720854B1 (fr) 1993-12-28 1995-05-30 Procédé de fabrication de dispositifs à semiconducteurs dotés d'un câblage en aluminium par gravure et chauffage sous vide.
FR9506357A Expired - Fee Related FR2720855B1 (fr) 1993-12-28 1995-05-30 Procédé de fabrication de fispositifs à semiconducteurs dotés d'un câblage en aluminium par exposition du substrat à une solution réactive.

Family Applications After (1)

Application Number Title Priority Date Filing Date
FR9506357A Expired - Fee Related FR2720855B1 (fr) 1993-12-28 1995-05-30 Procédé de fabrication de fispositifs à semiconducteurs dotés d'un câblage en aluminium par exposition du substrat à une solution réactive.

Country Status (1)

Country Link
FR (2) FR2720854B1 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4183781A (en) * 1978-09-25 1980-01-15 International Business Machines Corporation Stabilization process for aluminum microcircuits which have been reactive-ion etched
US4370195A (en) * 1982-03-25 1983-01-25 Rca Corporation Removal of plasma etching residues
JPS593927A (ja) * 1982-06-29 1984-01-10 Fujitsu Ltd 薄膜のエツチング方法
JPS62281331A (ja) * 1986-05-29 1987-12-07 Fujitsu Ltd エツチング方法
JP2906590B2 (ja) * 1990-06-14 1999-06-21 三菱瓦斯化学株式会社 アルミニウム配線半導体基板の表面処理剤

Also Published As

Publication number Publication date
FR2720855A1 (fr) 1995-12-08
FR2720854A1 (fr) 1995-12-08
FR2720855B1 (fr) 1998-03-27

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Date Code Title Description
ST Notification of lapse

Effective date: 20090831