FR2690593A1 - Method for synchronizing at least one component of a multiplex signal. - Google Patents

Abstract

The invention relates to a method for synchronizing at least one analog component of a multiplex signal comprising at least one digital data channel. At the emission, in a channel (IRNS) is inserted at least one additional channel (RDS) comprising digital information, and comprising patterns having a synchronization signal (SYN) allowing to set in phase at least one analog component as well as said digital information. At the reception, the synchronization signal (SYN) is detected and allows to synchronize said analog component and the digital information of the additional channel. The synchronization at the reception may comprise a step for generating a signal with a characteristic frequency from a wave form generator (WG).

Description

Method for synchronizing at least one component of a multiplex signal.

 The present invention relates to a method for synchronizing at least one component of a multiplex signal comprising at least one digital data channel.

 Certain modern broadcasting systems must have precise phase relationships between the multiplex signals broadcast from different points (synchronous FM, DAB digital broadcasting).

 It is already known to reproduce identical analog multiplex signals at different points by transporting this signal entirely in analog form on the distribution network. This solution is simple, but it requires transport systems with good analog performance and it requires going back in digital form if one wants to precisely match the phases of the signals to be broadcast, for example - in isofrequency broadcasting (for example in Synchronous FM).

 Digital transport systems are also known which present information on the phasing of the signals transmitted from the synchronizations carried by the digital distribution system. However, this phasing information is not sufficient to allow the phasing of all the analog components of the broadcast multiplex signal.

 The present invention relates to a method for avoiding these drawbacks.

 The invention thus relates to a method for synchronizing at least one analog component of a multiplex signal comprising at least one digital data channel, characterized in that it comprises the steps of inserting on transmission an additional channel comprising recurring patterns, at least some of which include a synchronization signal, and of synchronizing on reception said component from said synchronization signal.

 The patterns (for example blocks or frames) of the additional channel advantageously have a duration multiple of the periods corresponding to the frequencies of several analog components.

 At least one said component may be a frequency signal characteristic of a transmission, for example in frequency modulation, and the step of synchronization on reception includes a step of generating said characteristic frequency signal from a generator. waveform synchronized from said synchronization signal.

 In a preferred embodiment, the waveform generator is digital and comprises a means for cyclic reading of a waveform memory (for example implementing a cyclic counting of addresses of the memory), and said synchronization of the waveform generator consists in bringing the cyclic address reading means to a given state.

 Said synchronized component can then include data. The method then includes a step of decoding at least some of said data to address sectors of the waveform memory, each sector being scanned by addressing by the cyclic reading means.

 According to a first variant, the patterns are blocks starting with said synchronization signal. The method can then include a step of memorizing each block in a sequential shift memory, the synchronization signal of the (N + p) th block (with p integer greater than or equal to 1) being implemented to control the setting to a specified count of a cyclic counter, said specified count producing a read signal of the Nth block contained in the sequential shift memory.

 According to a second variant, the patterns are wefts. This variant is particularly suitable in the case of reduced bit rate systems, more particularly in the case where the component to be synchronized comprises repetitive data (for example the RDS system), of which only the modifications are transmitted.

 The synchronization signals can contain address signals serving as time pointers for reading a memory containing the abovementioned data.

 The invention finally relates to a use of the method as defined above in a synchronous network comprising a head-end transmitter and a plurality of repeaters characterized in that said additional channel is generated at the head of the network so that at at least one component is synchronized in the same way in all repeaters.

Other characteristics and advantages of the invention will be better understood on reading the description which follows, in conjunction with the drawings which represent
- Figure 1, a block diagram illustrating the method according to the invention implemented in a broadcasting network implementing the AES / EBU standard
- Figures 2a and 2b, respectively the synchronization of a block, and the constitution of a block
- Figure 3 an example of extraction and dissemination of RDS type information
- Figure 4 of the timing diagrams of a coding
NRZ to remove phase ambiguity
- Figure 5 general organization of a frame
- Figure 6 a transmission using a system of compression and expansion of audio data
- Figure 7, an example of a frame comprising a synchronization word constituting a time pointer
- Figures 8a and 8b, respectively a device for inserting RDS data at the head of the network and the corresponding timing diagrams
- Figures 9a, 9b, 10a and 10b respectively a data extraction device
RDS from a signal according to the AES / EBU standard, the corresponding timing diagrams, an RDS waveform generation device, and the corresponding timing diagram
- Figure 11, a device for implementing the method according to the invention in the variant has read pointers which are incorporated in a frame
- And Figure 12, an example of a retransmitter including a data insertion device.

A digital transmission system has channels for transmitting audio signals and, associated with these channels, additional channels which are available to users. A block diagram of the transmission chain according to the invention is given in FIG. 1. The diagram is constructed around an AES / EBU type interface (technical document 3250 of the European Union of
Broadcasting and Supplement No. 1 to this technical document).

 The transmission system used can transmit all the information of the interface or only a part of this information. First, it is assumed that the entirety of at least one user channel and the most significant bits of the audio signal are multiplexed in the digital transmission network.

For transmission, the digital audio information to be transmitted is provided in the standard
AES / EBU. Additional data, for example RDS data, is multiplexed in a user channel of the AES / EBU interface. This user channel is formatted according to the AES / EBU standard. This formatting is carried out according to the invention by a block synchronization generator SYBG and the data is inserted in packets by an insertion circuit INS known per se and corresponding to the insertion protocol provided for by the above-mentioned AES / EBU standard.

 The digital information to be transmitted INF is introduced at the input of a receiver REC and of a clock extractor CLE.

 The receiver supplies data D to the transmitter EM which transmits in standard AES / EBU in a broadcasting network RD. The clock extractor CLE supplies a clock signal H to the transmitter EM and a clock signal SF1 on the one hand to the block synchronization generator SYBG, on the other hand to the frequency generator of the data to be inserted G and finally to an INS inserter.

A data generator, for example according to the RDS standard ("Radio Data System") referenced SRDS receives from the generator G a frequency signal SF2 which generates for the INS inserter on the one hand DRDS data signals and on the other hand clock signals
CLRDS. The INS inserter provides the EM transmitter with a SHDLC signal to be inserted which is in an HDLC frame (see the above-mentioned standard). It will be noted that the insertion techniques are known per se and are provided for by the aforementioned AES / EBU standard.

On reception, a block synchronization signal is extracted to allow precise identification of the remarkable moments of the bit rate and the information transported in the packets is decoded in order to be able to drive waveform generators which are synchronized by the synchronization of blocks. To this end, the signals received from the network RD are of the AES / EBU standard and are introduced to an input of a reception circuit RE in which they are demultiplexed and in which a clock signal HREF is generated. The reception circuit RE supplies demultiplexed data signals DT to a microcontroller MC and to a synchronization detector
SYNDET.It provides the reference clock signal
HREF on the one hand to the synchronization detector circuit
SYNDET and on the other hand to the MC microcontroller. A SYNDET synchronization detector circuit supplies a SYN block synchronization signal to the microcontroller MC. A WG waveform generator receives WDT signals from the microcontroller MC corresponding to the waveforms to be generated. The WG waveform generator produces a read signal RD introduced into the microcontroller MC. The WG waveform generator produces signals (pilot frequency, carrier sounds, RDS signals) which, thus precisely reconstructed and synchronized, are directly usable with the SYN block synchronization signal to carry out, for example, a consumer FM broadcast broadcast from the signals received in AES / EBU, and more particularly within the framework of a synchronous FM network.

 The user channels of the AES / EBU interface are independent of the other transmission channels contained in this interface (digital audio channel, signaling channel). A user bit is associated with each audio frequency sample. When the sampling frequency is - Iron, we obtain an available bit rate F e x Kbit / s. The blocking of this bit rate is carried out according to the invention so as to restore all the frequencies necessary for the synchronization of the sub-carriers useful for the reconstruction, for example of an FM multiplex.

 For a synchronous frequency modulation broadcast, the RD transport network must make it possible to synthesize with precise phase relationships the pilot frequency at 19 kHz, the subcarrier at 38 kHz, and if necessary the RDS subcarrier at 57 kHz as well as the RDS information transitions which have a speed of 19/16 kbit / s.

 On transmission, the user channel is divided into blocks which begin with block synchronization (Figures 2a, 2b and 3).

 This block synchronization makes it possible to easily identify a precise instant in the bit rate which is used to drive the WG waveform generators.

 The pilot frequency at 19 kHz and the two aforementioned subcarriers (38 and 57 kHz) have an integer number of periods every 1/19 ms.

 The RDS information presents an integer number of bits (19) every 16 ms.

 Synchronization is used to identify a precise instant of each of the sinusoidal signals of the pilot frequency and of the subcarriers, and for RDS information to identify a particular bit in 19 x nx bit packets in the 19/16 kbit / bit stream. s.

The duration of the blocks is chosen such that it is a common multiple of 1/19 ms (pilot and undercarriages) and 16 ms (RDS). A length which is particularly suitable for the characteristics of the overall system is 64 ms. Such a block is shown in Figure 2a. When the sampling frequency is 32 kHz, the block contains 2048 bits. Information can be multiplexed in accordance with the standard. The beginning of the blocks is identified (SB) by detecting at least 7 successive ones followed by a zero. This start of the block makes it possible to synchronize the waveform generators and constitute identical multiplex signals at all points of the transmission network. This start of block also allows synchronization of data
RDS. The duration chosen above of 64 ms corresponds to 76 RDS bits, which makes it possible to introduce into the first block the first 76 bits of a first RDS frame of 104 bits (26 x 4), in the following block the remaining 28 bits of the first RDS frame and the first 48 bits of the second RDS frame and so on.

 More generally, the duration of a block is n x 16 ms which corresponds to n x 19 RDS bits. In each block, one or more data packets P1, P2, etc. are inserted which contain n × 19 bits. In the example described, a single packet containing 76 RDS bits is inserted in each block (FIG. 2b) and this packet is multiplexed by insertion with packets already present in the multiplex and coming from other applications. RDS data is provided by the SRDS data source mentioned above.

The DTEX data extractor makes it possible to demultiplex the digital data inserted in each of the blocks and to store them in the memory of the MC microcontroller.

Sine waveform generators
WG are slaved in phase on block synchronization
SB. In addition, the SRDS waveform generator must code with the same phase, the same bit, at the different broadcast points, the time reference being the distributed bit rate.

According to FIG. 3, the RDS bits received in a block N are broadcast for the duration of the next block
N + 1. At the start of the block (N + 1), the RDS bits referenced PNRDS of the previous block N are available in a memory of the first in / first out type
FIFO and arranged in order. The FIFO memory can have a size corresponding to the RDS bits of p successive blocks. In this case, the RDS bits referenced PNRDS of block N are available at the start of the block (N + p).

 Block synchronization makes it possible to precisely identify the output time of the first bit received in the previous block N and to transmit it at a precise time relative to block synchronization, namely at the end of the block synchronization signal.

As shown in Figure 3, the first bit of the packet
RDS contained in block N is exploited by the waveform generator WG from the start of the block (N + 1). In this way, the RDS information which is used by the RDS block generator is the same throughout the network relative to the block synchronization of the user channel. Note also in FIG. 3 that the PNRDS data packet constituting the first packet inserted in the block N, is read at a rate such that the 76 bits which it comprises occupy the entire duration (64 ms) of the block (N + 1), thus restoring the continuity of the RDS frames.

Furthermore, in accordance with FIG. 4, the data signal broadcast according to the RDS standard uses a marked two-phase code which includes a transition in the middle of the bit cell when transmitting "1s". This system therefore has a phase ambiguity. Pre-coding is performed on transmission. It consists in transmitting information
RDS to NRZ-M, the precoding being such that the phase of the NRZ signal is changed each time the RDS data value to be transmitted is equal to 1.

 The RDS clock signal H at 19/16 kHz is synchronized from the block synchronizations mentioned above, and the modulating RDS signal is the result of an exclusive signal between the NRZ-M signal and the clock signal H .

 In this way, the phase ambiguity is removed.

 According to FIG. 5, digital audio channels are transported in other multiplexes which are used, for example, for systems with reduced bit rate.

This may involve, as shown in FIG. 6, in a manner known per se, an AUDCOMP compression of the audio and UICOMP information of the user channels before sending, with other signals, in an ST transmission system, for example in a system 2 Mbit / s transport such as the Administration's G 704
French Post and Telecommunications.

Then, before switching back to standard
AES / EBU, the signal undergoes, in a manner known per se, an expansion to AUDEXP, and an expansion of the user channels UIEXP.

 Generally, the digital data stream is divided into frames which contain audio information at frequencies INF and user bits UI, the start of the frame being identified by a frame alignment word VT. A frame contains a constant number of bits n, for example, 6400 bits (Figure 7). The information field INF inside this frame thus contains audio information and user information UI.

This set of information can be multiplexed with other data. The frame locking word VT and the bit clock allow the information contained in the frame to be demultiplexed simply (FIG. 5).

The user bits UI are organized into an independent channel and managed in the same way as the user channels of the AES / EBU interface, but with a lower bit rate (2 kbit / s for example). This implies in particular in the audio system that the RDS signal contained in the frames transmits only the modifications of the RDS signal to be broadcast, resulting in a significant reduction in the bit rate, the RDS data being, by nature, very repetitive.

 It will be noted that different algorithms are known for achieving compression and expansion of audio frequency data (almost instantaneous compression, etc.). User data can also be compressed.

The synchronization of the blocks is chosen to fulfill the same conditions as in the previous case when possible. This duration is chosen such that the start of the blocks makes it possible to enslave in phase all of the remarkable frequency signals to be found (pilot frequency, subcarriers, frequency
RDS) so that the first bit of each block always ends up in the same place in the frames of the transport system. In the example in FIG. 7, there are 50 user bits UO U49 per frame of 6400 bits. The start of the bit synchronization word arrives for example at U1 and is repeated at the same position in the other frames if necessary.

 The synchronization word can thus be used as a reference to synchronize the waveform generators for the sinusoids at 19, 38 and 57 kHz which are synthesized from a read-only memory which contains the value of the different samples necessary for the creation of these sinusoids. The synchronization word serves as read-only memory pointer at the start of the next synchronization word.

 For the most part, RDS information is repetitive. They are organized into four 26-bit frames which can repeat every 104 bits. These 104 bits are considered a complex waveform which is read into memory at the appropriate rate. The synchronization words serve as previously for the memory read pointer. Changing RDS information can be done at a slower rate and is activated at the start of 104-bit blocks when the new RDS block has been created. These changes are made in 26-bit frames. There is indeed a cyclic CRC redundancy check signal per 26-bit frame. The bit rate on the distribution network is thus reduced by transmitting only the RDS information which changes.

According to FIGS. 8a and 8b, the clock extractor CLE receives the signal INF according to the standard
AES / EBU and produces a signal SF1 of frequency 32 kHz introduced into the generator G of data frequency as well as into a frequency divider by 2048 DIV constituting the aforementioned SYBG circuit. The frequency generator G generates a signal SF2 at 19 kHz which is introduced into the SRDS generator of RDS data. The signal SF1 is also introduced into a microcontroller MC1 (for example 8044 from the company
INTEL) which constitutes the INS inserter. The frequency divider DIV divides the signal SF1 by 2048 to produce a synchronization signal every 64 ms
Recurrent SYN. The SRDS RDS data generator produces DRDS data signals and a 19 kHz CLRDS clock signal to allow the MC1 microcontroller to produce the SHDLC signal according to an HDLC frame to be inserted into the transmitter signals.
EM according to AES / EBU standard. Recall that a standard HDLC frame includes a flag at the start of the frame
DR, an address AD, a control byte CO, an information field INF, control bits for cyclic redundancy CRC and an end of frame flag DR '. The synchronization signal SYN is present at the head of the block in the form of a pattern comprising at least seven successive "1s", followed by a "0", each block possibly comprising a plurality of frames.

As shown in FIG. 8b, the rate of the SYN signal makes it possible to transmit blocks of 2048 bits at a bit rate of 32 kbit / s. The CLRDS signal allows for the same duration the accumulation of 76 RDS bits. The RDS frame can be located at the start of the signal block
SHDLC, and it is inserted according to the AES / EBU protocol.

According to FIGS. 9a, 9b, 10a and 10b, the reception synchronization is carried out as follows. The AES / EBU formatted signals supplied by the distribution network from the signals transmitted at the head of the network in the transmitter EM are introduced on the one hand at the input of the receiver circuit RE. The receiver circuit RE supplies a data signal DT and a reference clock signal HREF which are both introduced, on the one hand at inputs of the synchronization detection circuit SYNDET and on the other hand at inputs of a serial interface circuit SIU associated with a central processing unit CPU of a microcontroller MC2 (for example 8044 from the company "INTEL"). The central processing unit CPU also receives the synchronization signal SYN generated by the circuit
SYNDET.

 The microcontroller MC2 generates, for a memory of the sequential shift type FIFO1, on the one hand a reset signal RS and on the other hand a write signal WR. The FIFO1 memory makes it possible to avoid the microcontroller having to manage each bit of the RDS signals.

 Signals corresponding to the RDS user channel are supplied by the microcontroller MC2 to the memory FIFO1 via a bus BUS1.

The FIFO1 memory receives a read signal RD and generates DRDS signals of RDS data as well as a signal EF to indicate to the microcontroller MC2 that the FIFO1 memory is empty. The signal EF indicates that the operation of reading the preceding block by the memory is complete. The microcontroller MC2 then generates a reset signal RS from the memory FIFO1, then a write signal WR. The microcontroller MC2 checks that the signals SYN and EF arrive at the same time, and if not it forces the reset to zero RS of the memory FIFO1.

In other words, the FIFO1 memory is not loaded until it is read and the microcontroller MC2 keeps in memory the RDS bits not yet loaded in the FIFO memory 1. A decoder DEC of the RDS data receives from the microcontroller MC2 a data DRDS signal
RDS. It generates a CLRDS read signal RD for the memory FIFO1. The decoder DEC supplies data and addresses to a signal processor DSP via a bus BUS2. the signal processor
DSP receives from the SYNDET circuit the synchronization signal SYN and from the receiver RE a signal of sampling frequency FECH (for example a multiple of HREF in particular 256 kHz for HREF at 32 kHz).

The signal processor DSP delivers on a bus BUS3 the digital signals corresponding to the RDS data. The decoder DEC also includes a programmable memory PROM in which waveforms are stored and the operation of which will now be described with regard to the generation of waves.
RDS.

 The signal processor DSP (for example a microcontroller 56001 from the company MOTOROLA) is programmed to cyclically generate addresses for example according to a twelve-bit code A0 ... A11 to cyclically address the twelve least significant address bits PROM programmable memory. When the highest address is obtained, the account is reset to zero. The SYN synchronization signal also resets the above-mentioned count to zero. As long as the synchronization is correct, the two abovementioned resets are concomitant. During reset, bit A11 changes value. Its detection therefore makes it possible to generate a relevant synchronization signal SY even if the SYN signal is not present at each period. The Aîî bit also changes value when the counter reaches half the maximum count. The signal SY therefore has a frequency equal to that of the signal RDS (timing diagram of FIG. 10b).

The three most significant address bits A12,
A13, A14 of the PROM memory are addressed using the RDS data so as to reconstruct completely and with the right phase the RDS analog signals. The decoder DEC is cadenced by clock signals CLK at a frequency which is a multiple of 19 kHz and which corresponds to the clocking frequency of reading of the programmable memory PROM which contains waveforms sampled and prerecorded in digital form . A D type flip-flop B10 receives the most significant bit A11 from the aforementioned counter constituting the signal SY and the CLRDS signal is obtained from the inverting output of the flip-flop B10 (exclusive OR gate 30, one input of which is grounded). This signal is used to control the reading RD of the memory
FIFO1.The FIFO1 memory delivers the DRDS signals of RDS data to the data input D of a flip-flop Bg of type D whose data output Q (point A) is connected to the data input D of a flip-flop B cascaded in the same way by its output Q (point B) with a flip-flop B2 whose output Q delivers a phase signal () to the address input A14 of the memory
PROM (most significant bit).

 The signals present at points A and B are introduced at the inputs of an exclusive OR gate 10 whose output (point C) attacks the input D of a flip-flop B3 cascaded by its output (point E) with a flip-flop B4 whose output Q (point F) is connected to input A13 (weight bit immediately below bit A14). The non-inverting output Q of the flip-flop D3 (point E) is connected to the address input A12 (bit of weight immediately lower than bit A13 of the PROM memory.

The timing diagram of the signals at points A, B, C, E and F and of the phase signal () is shown in Figure 10b. The phase signal () precisely makes it possible to discriminate the phase in the NRZ-M code mentioned in FIG. 4 while the signals at points E and F (bits
A12 and A13 of the PROM memory) make it possible to choose between the four possible forms of curves (to the nearest phase) corresponding to the reconstructed analog signal of RDS data. The outputs ..... D7 of the PROM memory thus provide the samples corresponding to the reconstituted curve of RDS data shown by way of example at the bottom of FIG. 10b in correspondence with the timing diagrams of the signals.

To get the synchronization of the whole, it is enough simply that the program of the processor
DSP forces the counter giving the addresses Ao * A11 to a given account, for example a count 0 when the synchronization signal SYN indicates the start time of a synchronization. Detection of bit A11 (signal
SY) and the subsequent generation of the CLRDS signal initializes if necessary the reading of the FIFO1 memory and therefore synchronizes the RDS signal perfectly in time, without phase ambiguity.

 Of course, synchronization is shown in the substantially complicated case of an RDS signal comprising data for which an address decoding is necessary to address different pages or different sub-blocks of the programmable memory PROM. The same principle is applicable without such decoding for the generations of signals of pilot frequencies and of subcarriers for which it suffices to implement a cyclic counter as mentioned above which is managed directly by the DSP processor and which is reset to zero (or to a given account) when the SYN synchronization signal indicates the moment of synchronization for these signals. As a variant, the cyclic counter can be reset to a variable account which allows other frequencies to be obtained, in which case the SYN signal is followed by an address signal indicating to which account the cyclic counter should be reset .

In the case of a synchronous FM network having a pilot frequency of 19 kHz, subcarriers at 38 and 57 kHz (RDS), the DSP processor cyclically addresses a plurality of memories
PROM (or a larger capacity PROM memory) with synchronization by the SYN signal so as to initialize for example at zero level and with the same phase all the signals (pilot frequency, subcarriers, and possibly RDS signals) at the time of synchronization .

According to FIG. 11, the SYNDET circuit is a shift register with eight outputs, the first seven outputs as well as the eighth inverted output attacking a multiple inverting AND gate 20. The functional link between the memory FIFO1 and the decoder DEC is the same as previously, however the data
RDS which are decoded to address the programmable memory PROM (FIG. 10a) are taken from a memory MEM (which may be the RAM memory of the microcontroller MC2) updated each time the RDS data (104 bits) is modified , and which is read by a cyclic counter generated by the microcontroller
MC2).

 Either a low bit rate user channel of r = 2 kbits / s, comprising blocks of n = 1024 bits or blocks of 512 ms, which corresponds to 608 RDS bits.

If for the first block, the synchronization signal
SYN corresponds for example to a count 0 of the cyclic counter, for the next block, the count must be different because 608 is not divisible by 104 (corresponding to the 104 bits of the RDS information stored in the memory MEM). The remainder of the division of 608 by 104 is 88. For the next block, the synchronization signal SYN therefore corresponds to the count 88 of the cyclic counter for the block which follows it, 72 and so on. For this, an ADR address packet is added to the SYN signal to obtain a pointer allowing the cyclic counter of the microcontroller MC2 to be managed.

As the ADR packet comes after the SYN signal, we shift by one block. The microcontroller MC2, as soon as it receives the signal SYN, decodes in the data DT the address packet ADR which gives directly or indirectly the account to be entered in the cyclic counter for the start of the next block. It will also be noted that the synchronization signal SYN and its associated address packet ADR need not be present at the start of each block. It is sufficient that it is present from time to time because its function is to verify that the synchronization is working properly. In addition, the presence of the pointer allows operation with blocks of variable length.

 FIG. 12 represents a re-transmitter presenting a receiver REC according to signals of the standard AES / EBU and a transmitter REM to re-transmit signals to the standard AES / EBU and a data inserter controlled by a clock CLR at 32 kHz to insert signals RDS.

 According to the invention, it is necessary for a synchronous network that the synchronization signals are present in the multiplex at the head of the network. The insertion of any RDS data can be carried out at the head of the network or downstream in a network retransmitter, as shown in Figure 12.

In the latter case, it will be noted that there is no need for the DIV circuit (FIG. 8a) since the synchronization signal SYN is then present in the multiplex
AES / EBU.

Claims (10)

 1 - Method for synchronizing at least one analog component of a multiplex signal comprising at least one digital data channel characterized in that it comprises the steps of inserting on transmission an additional channel comprising recurring patterns including at at least some include a synchronization signal (SYN) and to synchronize on reception said component from said synchronization signal (SYN).  2 - Method according to claim 1, characterized in that the patterns of the additional channel have a multiple duration of the periods corresponding to the frequencies of several components.  3 - Method according to one of claims 1 or 2, characterized in that at least one said component is a frequency signal characteristic of a transmission and in that the step of synchronization on reception comprises a step of generating said signal of characteristic frequency from a waveform generator (WG) synchronized from said synchronization signal (SYN).  4 - Method according to claim 3, characterized in that said waveform generator (WG) is digital and comprises a means of cyclic reading of a waveform memory (PROM) and in that said synchronization of the waveform generator (WG) consists in bringing the cyclic reading means to a given state.  5 - Method according to claim 4, characterized in that said component to be synchronized comprises data and in that it comprises a step of decoding at least some of said data to address sectors of the waveform memory ( PROM), each sector being able to be scanned by addressing by the cyclic reading means.  6 - Method according to one of the preceding claims characterized in that said patterns are part of blocks starting with said synchronization signal (SYN).  7 - Method according to claim 6 characterized in that it comprises a step of memorizing the patterns of each block in a sequential shift memory (FIFO), the synchronization signal of the (N + p) i th block (with p greater integer or equal to 1) being implemented to control the setting of a cyclic counter to a specified account, said specified account producing a read signal of the Nth block contained in the sequential shift memory (FIFO).  8 - Method according to one of claims 1 to 5 characterized in that said patterns are wefts.  9 - Method according to one of the preceding claims characterized in that it comprises an address signal (ADR) associated with said synchronization signal (SYN), the address signal (ADR) constituting a read address pointer a memory element (MEM) of a pattern of a block.  10 - Use of the method according to one of the preceding claims in a synchronous network comprising a head end transmitter (EM) and a plurality of repeaters (REM), characterized in that said additional channel is generated at the head end so that '' at least one component is synchronized in the same way in all repeaters (REM).