FR2498397A1 - METHOD AND DEVICE FOR SYNCHRONIZING THE RECEPTION OF DIGITAL SIGNALS TRANSMITTED BY PACKETS - Google Patents

Abstract

THE SUBJECT OF THE PRESENT INVENTION IS A METHOD AND A DEVICE FOR SYNCHRONIZING THE RECEPTION OF DIGITAL SIGNALS TRANSMITTED BY PACKETS. THE PROCESS CONSISTS OF GENERATING THE SIGNALS OF A FIRST WINDOW OF A GIVEN WIDTH AT INTERVALS CORRESPONDING TO THE RHYTHM OF THE ONLINE PACKAGES, IN SEARCHING BY DETECTION AT LEAST ONE TRANSITION IN THE SIGNALS RECEIVED DURING THE DURATION OF EACH WINDOW, TO MODIFY THE INTERVALS BETWEEN THE START OF A WINDOW SIGNAL AND THE START OF THE FOLLOWING SIGNAL IN THE CASE OR THE TRANSITIONS DETECTED DO NOT CORRESPOND TO A GIVEN CRITERION AND TO MAINTAIN THIS INTERVAL EQUAL AUDIT RATE OF ONLINE PACKAGES AND PRODUCE A SYNCHRONIZATION SIGNAL TRANSMITTED TO A DEVICE FOR READING PACKAGES IN THE OTHER CASE. THE DEVICE ACCORDING TO THE INVENTION INCLUDES A DIVIDER COUNTER WHICH IS RESET TO ZERO BY TRANSITIONS DETECTED IN THE WINDOW SO THAT THE INTERVAL BETWEEN SUCCESSIVE WINDOWS IS MODIFIED UNTIL SYNCHRONIZATION IS ACQUIRED, THAT IS A -DIY THAT THE END OF THE WINDOW IS AT THE LEVEL OF THE SYNCHRONIZATION TRANSITION T BEGINNING OF THE PACKAGE. APPLICATION TO DIGITAL TELEPHONE TRANSMISSION TO THE ALTERNATE.

Description

METHOD AND DEVICE FOR SYNCHRONIZATION

  RECEPTION OF DIGITAL SIGNALS

TRANSMITTED BY PACKETS

  The present invention relates to a method and a synchronization device for receiving digital signals

transmitted in packets.

  It is known from the prior art to synchronize the reception of digitally transmitted signals, by recognizing a synchronization pattern which is either associated with the transmitted information (word or synchronization bit), or inherent to the code used for the signals.

  represent (self-synchronizing codes).

  In the case of digital packet transmission, that is,

  say when the digital information is transmitted iteratively but discontinuous in time in the form of a plurality of packets spaced from each other and appearing at a given rate, the synchronization devices of the prior art,

  which are typically limited to detecting a pattern of synchronization

  1S tion, for example in the form of a transition present at the beginning of the packet, are likely to produce a false synchronization, or a desynchronization when parasites are present in line, and even, if necessary a lock synchronization

  on a series of repetitive spurious impulses.

  The present invention thus relates to a method and a synchronization device not having the above defects

  and yet allow fast synchronization.

  The invention therefore relates to a synchronization method for receiving digital signals transmitted in packets, which comprises a phase of detection of the transitions received and a phase of recovery of rhythm of the packets in line. It is characterized in that it comprises the following operations: a) generating signals of a first window of given width at intervals corresponding to the rhythm of the packets in line; b) detecting at least one transition possibly present in the received signals during the duration of each window and determining if the transition or transitions detected during the duration of each window satisfy a given criterion of coincidence; c) if the criterion is not satisfied, changing the interval between the beginning of a window signal and the beginning of the next window signal, this constituting a synchronization search step; d) if the criterion is satisfied, maintaining said interval equal to said on-line packet rate and producing a signal representative of the synchronization, this constituting a step of acquisition and of

maintain synchronization.

  The invention also relates to a synchronization device

  on receiving digital signals transmitted in packets, which is provided with a device for reading the transitions present in the received signals as well as a circuit for recovering the rhythm of the packets in line. It is characterized in that it comprises: a generator producing a first window signal of given width at intervals corresponding to the rhythm of the packets in line;

  a coincidence detector receiving the signals of the

  tif reading transitions as well as said window signal and producing at its output a coincidence signal; a circuit receiving the coincidence signal and producing a signal for decrementing the interval between the beginnings of two successive windows when said coincidence signal does not satisfy a given coincidence criterion, and maintaining said interval at a value equal to said rhythm; online packages in the opposite case; at least one circuit producing a signal representative of the synchronization.

  The invention will be better understood on reading the description

  which will follow given by way of nonlimiting example and with reference to the accompanying drawings and o: - Figure la represents a transcoding scheme during a transmission; FIGS. 1b and 1c show packets as used in digital transmissions; FIG. 2 represents a synchronization circuit of the prior art used in the case of a digital packet transmission;

  FIGS. 3a-3b and 3c illustrate the synchronization effected

  killed according to the invention, and implementing a window signal;

  FIG. 4 represents significant signals of the synchronization

  packetization in the case of a 1B-2T code;

  FIG. 5 represents a block diagram according to the invention

  tion; 1S - Figure 6a shows a schematic diagram of an embodiment of the device described in Figure 5; FIG. 6b represents a state diagram of a criterion of acquisition and loss of synchronization; FIG. 6 illustrates an embodiment of the formation circuit of an acquisition and loss of synchronization criterion mentioned in FIGS. 6a and 6b and which derives from a proposed scheme

  by the International Telegraph and Telephone Consultative Committee

  that (C.C.I.T.T.); FIG. 6d represents a state diagram illustrating the operation of the circuit described in FIG. 6c; FIG. 7 is a variant of FIG. 6a implementing a second window called a reduced window; FIG. 8 illustrates the position of said reduced window with respect to the first window; FIG. 9 represents a state diagram corresponding to

  a mode of implementation of a reduced window.

  FIG. 1a illustrates a transcoding operation, common in digital telephony, which is carried out on transmission in a module E, as well as an inverse transcoding operation performed on reception in a module R. The information presented in FIG. Input of module E is coded according to one. code C1. The function of the module E is to transcode this code into a code C2 which is adapted to transmission by a line or more generally by a transmission channel K. The function of the reception module R is to carry out the inverse transcoding of the code C2 for find the CI code which is usually a binary code. The choice of the C2 code is dictated by properties, the main ones of which are generally: - - compressing the bandwidth normally necessary for transmission; - remove the need for continuous transmission of the component; - contain information allowing the reconstitution of a clock (rhythm) and allowing unambiguous decoding;

  - intrinsically give an error detection.

  For example, the code 1B / 2T was studied by C. AUZET in his article "Study of a family of codes applicable to a low-speed digital transmission system" published in the "THOMSON-CSF Technical Review" (Vol 12 No. 3 - Sept. 1980 pages 615 to

643).

  In the case of a digital packet transmission, the - recovery of the rhythm of the packets in line is ensured by the presence of a transition at the beginning of packet. The start of packet transitions, or more generally the locking patterns, are produced in the module E, either with increasing the bit rate by systematic insertion of a transition or blocking pattern at the beginning of the packet, or without increasing flow

  binary using a particular self-synchronizing C2 code, that is,

  to say a code whose every transcoded word starts with a bit

  producing a transition at the beginning of the word, for example an impulse

  positive or negative for a n-level code. At the reception, the

  reading of such a fixed and repetitive element must allow the recovery of

  timing of online packets and playback timing.

  FIG. 1b thus illustrates a digital transmission by

  packets where packets are equidistant in time and

  start at the beginning of a synchronization pattern, for example a transition. Figure 'c represents a particular case of Figure 1b, o

  each packet, which has at its beginning a pattern of synchronization

  tion, the multiplexing of n channels numbered from 1 to n and whose digital signals appear successively. Such digital transmission in equidistant packets and comprising a

  Multiplexing is commonly performed in telephony.

  These types of transmission are generally carried out

  nat, that is to say following a procedure consisting of sending a series of information, such as a packet of digital information, to one end of the channel, to receive it from the other, then to transmit a another packet of information in the other direction and so on. Synchronization upon receipt of such packets is generally accomplished by retrieving the timing of on-line packets and selecting as the synchronization transition, from the first present transition to the beginning. of package. Such a synchronization is described in FIG. 2, where the signals coming from a line are subjected to a shaping operation in the circuit 1, then, in the circuit 2, to a reading operation of the transitions present in the line. . A timing recovery circuit 2 'receives the transitions read at 2 and transmits to the packet read circuit 5 a synchronized signal corresponding to the timing of the on-line transitions. The circuit 5 also receives the transitions shaped by the circuit 1. The packets read by the circuit 5 are transmitted to a decoder 6 whose function is to perform the reverse transcoding mentioned above during

  from the description of Figure la. The decoder 6 and a base of

  time 4 receive from circuit 2 'rhythm recovery a signal

  synchronized clock corresponding to the beginning of each trans-

  code. The output of the decoder 6 is connected to a decoder 8 of synchronization pattern. The synchronization pattern can be simply

  a transition present at the beginning of the packet.

  The time base 4, which is in general a counter whose count is equal, within a factor, to the number of bits corresponding to the rhythm of the packets in line, and which is reset by the circuit 2 'recovery of rhythm, produced at its output S a signal whose rhythm is that of the packets in line, as well as a

  signal (HTR) representative of the beginning and the end of a packet.

  The set of circuits 2 'and 4 thus allows the recovery of the

rhythm of online packages.

  The outputs of the decoder 8 and the time base 4 are introduced into a coincidence detector 3 whose output is connected to the input of a decision logic 3 '. The output of the logic 3 'resets the time base 4 when the coincidence between the synchronization pattern and the time base is present iteratively according to a criterion set in advance. In the case

  contrary, the criterion determines a sequence of loss of synchronization

  tion. Finally, if the code is not self-synchronizing, the output S of the time base 4 is also used to phase the

  synchronized clock signal for reading each word.

  Such a synchronization is sensitive to all pulses

  parasites present between packets and which disturb the recognition

  synchronization pattern. It is therefore likely to become out of sync easily in the presence of parasite rates online

quite weak.

  The present invention thus relates to a method and a device

  synchronization signal at the reception of digital signals transmitted by packet, and more particularly but not exclusively in the case of a transmission alternately, and to avoid poor synchronization or desynchronization on parasites, especially isolated or repetitive , present between the packets. The method and the device according to the invention are advantageously used in the case of a transmission in the alternate where the presence of a large gap between the packets makes it all the more likely

  incorrect synchronization on spurious pulses.

  The diagram of FIG. 3a illustrates the process according to the invention

  a window signal F of given width ú is generated in the stabilized phase at intervals a n corresponding to the rhythm of the packets in line which is recovered from a circuit receiving the transitions read on reception. This window, represented as a slot, has a transition that indicates its beginning and a transition that indicates its end. Any transition present in the signal received between the beginning and the end of the window constitutes a coincidence. It should be noted that the term window encompasses any signal or series of signals making it possible to achieve temporal coincidences with one or more transitions. The logic processing of these coincidence signals, according to a coincidence criterion, makes it possible to decide on the possible modification of the interval between two successive windows, so that it eventually ends up at the beginning of the packet. Thus, at the beginning of the reception 1S of packets represented in FIG. 3a and which are separated by constant intervals at n, the first window F of width t which is for example located in the first received packet will be followed by June second window F of width ú separated from an interval A n 'less than intervalledn, this operation proceeding from packet to packet as long as the transition (s) detected during the duration of a window do not match not to a given criterion. This constitutes a synchronization search step. The window F will thus progressively rise back to the beginning of the packet, preferably positioning itself so that the synchronization transition Ts present at the beginning of each packet is at the end of the window. The coincidence criterion mentioned above can be chosen such that it is satisfied when a synchronization transition Ts is present in a chosen part of the window F, for example at the end of this window. When the coincidence (s) detected during the duration of a window satisfy the chosen criterion of choice, the interval between this and the next window is maintained equal to the interval A n corresponding to the rhythm of the packets in line. This constitutes an acquisition step

  synchronization. After confirmation, possibly, the

  Chronization is acquired (maintenance stage). The use of such a window-implementing method makes it possible to ensure that the timing of the synchronization is always correct, since the transition serving to synchronize the reading of the packets must always satisfy the criterion mentioned above. As a result, if the criterion becomes no longer satisfied, possibly after confirmation, a new synchronization search step will take place and the interval between the successive windows will be modified until the synchronization is again acquired. A synchronization signal will be significant only during the step of

acquired synchronization.

  As a nonlimiting example, a usable coincidence criterion consists in detecting the position of the first transition present in the window. The next window signal will be generated in such a way that the end thereof is separated from the first one

  transition by an interval equal to the rhythm of the packets in line.

  Thus, all transitions detected in a position before the end of any window will cause a decrease in the interval between the windows and a rise thereof to the packet head. Such a synchronization is illustrated in FIG. 3b where the first transition detected in the window, whose width is an example of three elements and corresponding to the first received packet, is the transition T5 located 4 elements after the synchronization transition TS . In the next packet, the end of the

  window F is located at the fifth transition of the packet.

  The first transition detected in the window is the T3 transition.

  In the next packet, the end of the window F whose width corresponds to 3 elements, will be located at the third transition of the packet. In these circumstances, the first transition

  detected by the window this time will be the synchronization transition.

  TS. As a result, synchronization can be acquired from the next packet where the transition Ts will be located at the end of the

  window F or after confirmation performed according to a logical criterion.

  The following F windows will be separated by intervals A n

249839?

  corresponding to the rhythm of online packages.

  The case where the first generated window is in a packet has been considered above. In the opposite case, no transition is observed during the duration of the window, and it is therefore preferable rather than shortening the interval between two successive windows, waiting for the first transition present on the line.

  which, in the absence of disturbance, will be the synchronization transition.

  present at the beginning of a packet. This situation is illustrated in

  Figure 3, where the window F is between two successive packets.

  The first detected transition will be the transition Ts of the next packet and the next window will then be generated such that the end of the latter is separated from said transition Ts of the second packet by an interval at n corresponding to the rhythm of the packets in line. This configuration allows a very fast acquisition of,

the synchronization.

  We will now specify the parameters for determining the width of the window optimally in the case where a criterion relating to the position of a transition in the window is used. First of all, the width of the window can not be less than that of 2 elements in line, otherwise the detection of the first transition could obviously not allow the window to go up a package. On the other hand, it is preferable that the width of the window is greater than the number of absences from

  successive transitions that may occur in a packet.

  This window width ensures that, when the window is at the level of a packet, it will necessarily be detected at least one

  transition corresponding to a coincidence. However, this condition

  This does not necessarily ensure an optimal rise of the window along the package since a transition present at the window could nevertheless be located at the end of the window, and by chance coincidentally. To avoid this drawback, it is advantageous to give the window a width at least greater than 2 elements to the number of successive absence transitions that may exist in a packet. It will be certain that two transitions will be present at the window when it is located in a package, which will ensure

  back to each package until synchronization

  be acquired. In view of the description above, it will be understood

  that the larger the width of the window, the faster the acquisition of the synchronization by raising a packet and, on the other hand, the higher the sensitivity of the synchronization to parasitic pulses present in the window. From this point of view, the determination of the width of the window will be obtained by making a

  compromise between the speed of synchronization and its relative insensi-

  bility to parasites present on the line.

  According to a first variant, a coincidence criterion used

  sand consists of counting the number of transitions present during the duration of the window. If this number is greater than 1, the interval i_ between this window and the next window will be reduced by an amount corresponding to at least one element. If this number is equal to 1, the interval between the window and the following window will be maintained at a value corresponding to the rhythm of the packets in line. If this number is 0, proceed as in the case of Figure 3c. The choice of this criterion also allows the window to reassemble the packet until the synchronization transition T. is at the end of it. The conditions mentioned above with regard to the choice of the width of the window are valid in the case of this

  criteria, as they were in the case of the previous criterion.

  According to a second variant, the criterion of coincidence is the detection at the end of the window of a pattern of coincidence. If it is not

  not satisfactory, the interval between windows is changed.

  To avoid a desynchronization in the case where the transmission

  the process according to the invention comprises a synchronization detection operation when the criterion is intermittently satisfied or not at all, said operation consisting in producing again a synchronization search step, according to a criterion

decision logic.

  The process described above ensures fast synchronization

  and effective digital packet transmission, but

  it remains likely to become out of sync in the event that a parasite pulse is located at the window and before the start of the packet. A preferred embodiment of the invention then consists in generating a second window called reduced window whose beginning is the same as said window and which is shorter than an interval corresponding to an element and detecting the absence of transition in said window reduced. Only the

  iterative presence of a transition in reduced windows successively

  cessives produces a registration of the first window on the first detected transition. The resetting of the first window is thus postponed until the iterative presence of a transition in the reduced window makes it possible to think that it is the latter which is in reality the synchronization transition, that is to say that there was for example a drift of the synchronization pattern during the

  time. If transitions occur only intermittently

  tent or fugitive in the reduced window, there will be no change in the interval between the first successive windows, since the unstable character of these transitions indicates that they are due to parasites present on the line. It should be noted that this operation of generating a reduced window is only useful during the step of acquiring and maintaining the synchronization. Indeed, if we generate such a window during the so-called synchronization search step, the recovery of the packets by the first window may be very substantially slowed down. Also as an alternative, the method according to the invention comprises a logical decoding of the acquisition and / or maintenance of the synchronization which produces a decrease in the width È of the

  window F, preferably up to a single element.

  Means for carrying out the above method will now be described, with reference to a code IB / 2T by way of non-limiting example (words of a binary element transcoded in two

ternary elements online).

  FIG. 4 shows at α the shaped line signals corresponding to successive packets each comprising ten elements, and in b the transitions TR read. A ternary HT clock is represented in c, which corresponds to the rhythm of the transitions

  present online, that is to say that it presents separate transitions

  by an interval of an element. A binary clock is derived from the ternary clock T by a division operation by 2 (code IB / 2T) and thus corresponds to the rhythm of the ternary words, and its two possible phases are designated respectively by HB in d and HB in

  e. When synchronization is acquired, and where appropriate,

  In principle, the binary clock is reset to the time, in principle at the beginning of each packet, and continuously supplies the HB signal with the correct phase. A representative HTR signal from the beginning and the end of each

  packet is represented in f as an envelope signal.

  Finally, the BD decoded bits are represented in g. The three signals HB, HTR and BD are provided to the user which allows him to read all the binary information clockwise by the clock HB, the HTR signal determining the position of the beginning and the end of each packet. The window F is represented in h, positioned at the beginning of the packet (acquired synchronization), whereas in i is indicated the count of a counter used to produce the signal of

  window and the HTR signal as will be described later.

  FIG. 5 represents a shaping circuit 12 receiving the signals present in line and introducing them, on the one hand, into a circuit for reading on-line transitions 22, and on the other hand in a circuit 52 for reading the packets. The transitions TR read by the circuit 22 are introduced into a rhythm recovery circuit 42 as well as into a coincidence detection circuit 35. The circuit 42 produces a line clock signal (ternary clock HT) towards the circuit 52 for reading the packets. The circuit 42 produces, in the case of block codes, a word clock signal (binary clock HB) which is received by a decoder 62 and by a time base 43, which is generally constituted by a divider counter. This signal is deduced from the signal of the line clock by a dividing operation (by 2 in the case of a code I B / 2T). The transitions read in the circuit 52 are introduced into the decoder S5 62. The time base 43 receives the signals from the line clock HT or preferably from the word clock HB and introduces into a window generator 34 a signal whose periodicity, in steady state, corresponds to that of the packets. The coincidences detected during the duration of the window are introduced into a logic decision circuit 36 which, on the one hand, will produce a reset signal of the time base 43, and on the other hand a synchronization signal in the direction of the rhythm recovery circuit 42. As mentioned above, with reference to FIG. 2, the circuit 42 and the time base 43 constitute a circuit of

  recovery of the pace of online packages.

  Let us consider the case where the time base 43 is a counter realizing a division according to a ratio n, one is the number of elements corresponding to the interval between two starts of received packets, and which receives the signals of the line clock HT. The counter emits a pulse towards the window generator 34 when it reaches an account (n - p), p being the number of elements defining the width of the window F. In the absence of a delivery command to zero from the decision logic 36, the timebase transmits a control pulse to the window generator 34 at intervals corresponding to the packet spacing and the counter resets itself when reaches the count n, moreover simultaneously with the arrival of the synchronization transition. On the other hand, when the decision logic 36 transmits signals corresponding to a search configuration

  synchronization, that is, a transition is present

  before the end of the window, resetting the time base before it reaches account n, ie the account (n - q), will result in the following window being advanced

a corresponding account q.

  However, as shown in FIG.

  In the counter constituting the time base 43, the signals HB of the word clock are generated in the counter, the counter having in this case a division ratio equal to the number of words corresponding to the interval between two starts of received packets. In this case, the width of the window will be, unless there is a delay element in the window generator, equal to the number of elements constituting each word (2 in this case) or to a multiple of it. The end of the window thus corresponds to the beginning of a word when the word clock HB is synchronized. Thus, referring to the lines h and i of FIG. 4, a window F of two elements is generated when the counter reaches the count n-1 and ends when the latter reaches the count n, simultaneously with the counter. synchronization pulse. The envelope HTR signal ends when the counter reaches the count n = 5 equal to the number of words

of a package.

  FIG. 6a shows an embodiment of the diagram of FIG. 5 which, by way of example, has also been described in the case of the reception of ternary signals whose words comprise two elements (code IB / 2T). The circuit 22 for reading the transitions in

  line consists of a transition + and transitional detector 221 -

  whose output signals are introduced at the input of an OR gate 222. The circuit 42 comprises a divider counter 421 receiving the signals of a local clock H and which is reset by the signals present at the output of the door 222-. The division ratio of the divider counter is such that the output signals that it delivers constitutes a line clock (ternary clock HT), that is to say that

  its rhythm corresponds to that of the appearance of successive transitions

  in a package. Its resetting is a phasing compared to the transitions received. The divider by 2 counter referenced 422 receives the ternary clock HT signals and produces at its output word clock signals HB that is to say whose rate corresponds to that of the appearance of the words of a package. The packet reading circuit 52 comprises a parallel serial converter 521 which receives the line signals shaped by the circuit 13 and which introduces them sequentially at a rate given by the ternary clock HT into a memory 522. in memory word by word are then read at a rate corresponding to the word clock HB and are introduced sequentially into the decoder 62 where they are decoded at the same rate. The circuit 43 which constitutes a time base for the window generator 34 receives the binary clock signals HB supplied by the divider counter 422, at a divider counter 432 whose division ratio is such that it produces an output S 'of the signals whose periodicity corresponds to the rhythm of the packets in line. For example, if one places oneself in the case of a transmission with alternating o in the same direction, packets of 40

  words of two elements are separated by corre-

  At 88 words of two elements, the rate of appearance of the packets at the reception will correspond to 128 words of two elements, and consequently we will use a counter 432 which will divide by a ratio

  n = 128 the word clock signal HB.

  To produce a window of width 2p elements, the counter 432 will emit a control signal towards the window generator when its count reaches (128 - p), namely 127 in the case of a window with a width of 2 elements. Thus, the end of the window will correspond to the moment when the counter reaches the account 128 where it resets itself to zero. A circuit 35 'detects the first transition present in the window, for example, thanks to a latch circuit with two flip-flops. The outgoing signals of the circuit 35 'are introduced into the decision logic 36 at a

  circuit 362 for forming a synchronization criterion, preferably

  through an AND gate 361 which receives general

  window 34 (or divider 432) a signal of width at most equal to an element and representing the end of the window, this signal constituting a kind of auxiliary window since it aims to inform the criterion on the coincidence between a transition and the end of the window. It is thus ensured that the evolution of the criterion will take place according to the presence or absence of the first transition at the end of the window. On the other hand, the outgoing signals of the circuit 35 'are also introduced at the input of an OR gate 431 which is part of the circuit 43 and whose output 434 resets the divider counter 432. This loop makes it possible to perform the ascent

  a packet through the window when searching for synchronization.

  The circuit 362 produces at its output a signal representative of the loss of synchronization which is introduced at the input of an AND gate 363 which also receives the transitions detected at the output of the OR gate 222. The output of the AND gate 363 is connected to the other entrance of the

  OR gate 431 whose output resets the divider counter 432.

  This looping then allows, in case of loss or absence of synchronization,

  to reset the synchronization on the first transition

present online.

  The output of the AND gate 363 is, on the other hand, connected by a link 365 to the reset input of the circuit 362 for forming a loss of synchronization criterion. The output of the AND circuit 361 introduces, via a link 367, to the reset input of the divider counter 422, a synchronization signal performing a phasing of the "word" synchronization. On the other hand, the divider counter 432 transmits at 435 signals representative of the decoding of two data of its states towards a circuit 433 for forming an envelope signal HTR corresponding to the beginning and at the end of the reception. of a package. This signal is also, at least

  as for its rising edge, a signal representative of the synchronization

  tion. It can also be used as an authorization signal from the

  parallel serial converter 521.

  FIG. 6b represents an example of a criterion that can be used in the circuit 362. It goes without saying that the use of such criteria is common in the transmission technique and that, consequently, this criterion is given for illustrative purposes only. . The choice of such a criterion is in any case a compromise between

  speed and stability of synchronization.

  Position 2 corresponds to a lack of synchronization (search for synchronization). Position 4 looped on itself

  corresponds to an acquired synchronization (maintaining synchronization

  sation) after confirmation of the coincidence criterion in three successive S windows (2 - I + 3 t 4). The intermediate positions (1,

  3, 5, 6, 8) correspond to the acquisition of synchronization.

  This takes place either from a step 2 of synchronization search.

  sation, or from step 4. When at most two successive absences of coincidence occur, a new logic acquisition synchronization operation is implemented without changing the position of the window F. By cons, the loss of synchronization, thus the return to the position 2, and the authorization of resetting of the counter 432 on the first detected transition

  is caused for example by three successive absences from coinci-

dence.

  FIG. 6c is an embodiment of the circuit 362 for forming a loss of synchronization criterion, and which derives from a scheme proposed by the C.C.I.T.T. It consists of three flip-flops, and, P and B mounted in shift register. A line 366 introduces into the shift register an on-line packet rate clock generated from the counter 432 or the window generator 34. A line 365 connected to the output of the AND circuit 363 is used to reset the flip-flops. The line 367 introduces the output of the AND circuit 361 to the input of the counter ode so that at a transition detected at the end of the window, corresponds to a zero in the counter 4. The inverted output Zdu counter e (is introduced in the

  counter P, and the non-inverting output of the counter P is

  pick in the counter at '. The operation of the shift register

  then corresponds to the logic of Figure 6c.

  The following strategy will be adopted: there will be a loss of synchro-

  if there is no transition in three consecutive windows from steady state 011 (0 <= 0, A = 1, y = 1). This corresponds to the identification of the state 100, as can be seen in the diagram of FIG. 6d. There will also be a loss of synchronization and consequently a reset of the counter leading to a new search if, starting from state 000, there is no transition present in the next window. This corresponds to the state 1 0. The simultaneous decoding of these two states is realized when "(= 1 and a '= 0, either: S 5 or C + 6 1 This detection is consequently carried out by the inverter circuit OR 368 which receives Z at one of its inputs and at its other input and whose output 364 constitutes one of the inputs of the AND circuit 363. The circuit described in FIG. 6a has the drawback of resetting the divider counter 432 systematically in the presence of the first transition present in the window, the synchronization remains sensitive to any parasite present in the first part of the window, which has a slight drawback in practice.To avoid this phenomenon, is added to the device described in Figure 6a circuit 71 producing a second window called reduced window Fr whose beginning is the same as the first window but which is shorter than an element (see Figure 8). No. 72 (see FIG. 7) receives on-line transitions via a line 423 connected to the output of the OR circuit 222 of FIG. 6a and the reduced window signal Fr and detects their coincidences. The logic circuit 72 emits an output signal 74 only when at least one transition is

  present in a number of successive reduced windows Fr.

  This is achieved for example by incrementing the transitions present in the reduced window, a counter reset all k packets and by the absence of transition in the reduced window Fr. An inhibition circuit 73 receives the transitions present at the output of the circuit 35 for detecting the first transition in the window and authorizing their transmission to one of the inputs of the OR circuit 431 whose output resets the divider counter 432,

  in the presence of the output signal 74 from the logic circuit 72.

  The circuit described in Figure 7 makes the synchronization

  on any parasite, even present during the duration of the first window. However, the permanent commissioning of the inhibition circuit 73 is likely to disturb more or less the search for synchronization in the case where the first window is

  brought up along the successive packets.

  To avoid this drawback, the circuit 362 forming a

  synchronization criterion decodes a corresponding state, for example

  at a synchronization acquired (011 in the example of Figure 6d) and produced in this case, a validation signal transmitted by the

  line 76 and allowing the operation of the inhibition circuit 73.

  A status diagram of the operation with the window reduces

  is shown in FIG. 9 o the return to state 2 occurs only in the presence of 5 successive coincidences detected in the reduced window Fr, and only from the state 4 of maintenance

acquired synchronization.

  As a variant, it is also possible for a reduced window to be implemented or not, and when the synchronization is in its acquisition and / or maintenance phase, to reduce the width of the window F to a single element corresponding to the strict

  confirmation of the synchronization. For example, it is sufficient to detect

  ter states 1, 3, 5, 6, 8 and / or 4 (011 for the latter in the example of Figure 6d) and use this detection to switch the

  window generator on a suitable operating mode.

  The invention which has been more particularly described in the case

  IB / 2T code can be used with all types of codes envisaged

  whether the transmission is alternating or not. On the other hand, it also applies to all transmissions where the packets, of constant or variable length, are repetitive, that is to say that the recovery of the HTR envelope signal does not necessarily implement a local clock, but can be realized from the signals received themselves, in particular by direct recovery of the

rhythm of transitions.

Claims (21)

  A method of synchronizing the reception of digital signals transmitted in line by packets which comprises a phase of detection of the transitions received and a phase of recovery of the rhythm of the packets in line, characterized in that it comprises the following operations: generating signals of a first window (F) of given width at intervals corresponding to the rhythm of the on-line packets; b) detecting at least one transition possibly present in the received signals during the duration of each window (F) and determining if the transition or transitions detected during the duration of each window satisfy a given coincidence criterion; c) if the criterion is not satisfied, changing the interval (6 d) between the beginning of the window signal and the beginning of the next signal, this constituting a synchronization search step; d) if the criterion is satisfied, maintaining said interval <ôn) equal to said rhythm of the packets in line and producing a signal representative of the synchronization, this constituting a step   acquisition and maintenance of synchronization.   2. Method according to claim 1, characterized in that the   Changing the interval is a reduction of it.   3. Method according to one of claims 1 or 2, characterized in   that the given coincidence criterion consists in the presence of a transition at the end of the window signal, and that the modification of the interval (, dni) consists in positioning the following window so that the end of this one is separated from the first transition present in the preceding window by an interval A n   equal to the pace of online packages.   4. Method according to one of claims 1 to 3, characterized in   the step of acquiring and maintaining the synchronization comprises a step of logical confirmation of the synchronization leading to logical states respectively of acquisition and of maintain synchronization.   5. Method according to one of the preceding claims, characterized   Issued in that, when no transition is detected during the duration of a window, changing the interval consists of detecting the first transition present in the signal and producing a temporally separated window signal (F). of said first transition detected by an interval equal to the rate of the packets in line.   6. Method according to one of the preceding claims, characterized   characterized in that it comprises an operation of producing again a synchronization search step, when said coincidence criterion is satisfied only intermittently, or not at all.   7. Method according to one of the preceding claims, characterized   characterized in that it comprises, during the step of maintaining the synchronization, an operation of generating a second window called reduced window (Fr) whose beginning is the same as said window (F) and which is more short of an interval corresponding to an element and detecting at least one transition possibly present in iadite reduced window (Fr), the iterative presence of one or more transitions during a given number of times producing an offset of said first window (F) so that the end   the next window (F) is temporally separated from the first   re transition detected in the previous window (F) by an inter-   valle equals the pace of online packages.   8. Method according to one of claims 4 to 7, characterized in   what it involves a logical decoding of the acquisition and / or maintenance of the synchronization which produces a decrease of the   width of the window (F), preferably up to a single element.   9. A synchronization device for receiving digital signals transmitted in packets, which is provided with a circuit for reading the transitions present in the received signals as well as a circuit for recovering the rhythm of the packets in line, characterized in that it comprises: - a generator (34) producing a first window signal of given width at intervals corresponding to the rhythm of the S in-line packets; - a coincidence detector (35,35 ') receiving the signals of the transitions reading device and said window signal (F) and producing at its output a coincidence signal; a logic decision circuit (36) receiving the coincidence signal and introducing into the window generator a decrement signal of the interval between the starts of two successive windows when the coincidence signal does not satisfy a given coincidence criterion;   at least one circuit producing a signal (HB, HTR) representing 1S tative of synchronization.   10. Device according to claim 9, characterized in that it comprises a divider counter (432) receiving the signals- a circuit (42) for recovery of the rhythm of transitions in line and producing a control signal of said generator (34). ) when he reaches a given account equal to his division ratio minus one   number corresponding to the width of the window (F).   11. Device according to one of claims 9 or 10, characterized   in that said given coincidence criterion consists in the presence of a transition at the end of the window, in that said detector (35, 35 ') transmits at its output, only the first transition present in the window (F ) and in that said output is also connected to the reset input of said divider counter (432).   12. Device according to one of claims 10 or 11, characterized   in that the decision logic comprises a circuit (362) for forming a synchronization criterion whose input is connected to the output of said coincidence detector (35, 35 ') and which   produces a signal corresponding to a loss of synchronization   sation, said output being connected to a first input of a first AND circuit (363) whose second input receives the transitions of the received signals and whose output is connected to the reset input the divider counter (432).   13. Device according to claim 12, characterized in that said circuit (362) for forming a synchronization criterion comprises counters (o ", f, e) mounted in the form of a shift register with several positions each of which contains a state 0 or 1, and whose shift rate is controlled by a signal representing the rhythm of the packets in line, and at least one logic circuit (368) receiving at its input at least the states values of at least two positions and producing at its output at least one signal   corresponding to a loss of synchronization.   14. Device according to claim 13, characterized in that said positions are 3 in number, that the first (e) is incremented by the reciprocal of the output signal of the coincidence detector, the second (JS) is incremented by the inverse (<) of the first (c (), that the third (W) is incremented by the second (P), and that the logical decoding of of.y = 1 produces   said signal corresponding to a loss of synchronization.   15. Device according to one of claims 10 to 14, characterized   in that it comprises a second AND authorization circuit (361) receiving at its first input the output of the coincidence detector circuit (35, 35 ') and at its second input an auxiliary window signal representative of the end of the window F, and whose output is connected to the input of said logic circuit forming a criterion synchronization (362).   16. Device according to claim 12 to 15, characterized in that it comprises a generator (71) of a second window called reduced window (Fr) whose beginning is the same as said window (F) and which is shorter an interval corresponding to a transition and a logic circuit (72) detecting the transitions during the duration of said reduced window (Fr) and an inhibition circuit (73) disposed between the output of the coincidence detector (35,35 ' ) and the reset input of the divider counter (432), said muting circuit (73) receiving from the logic circuit (72) a non-enable signal (74) generated according to a given criterion.   17. Device according to claim 16, characterized in that said logic circuit (72) comprises a counter (C) whose rate corresponds to the rhythm of the packets in line and which is incremented in the presence of a transition in the reduced window, and which is reset in the opposite case, said counter producing at its output a signal of non-validation of the inhibition circuit when it reaches a predetermined count.   18. Device according to one of claims 16 or 17, characterized   in that the inhibition circuit (73) is validated by a signal   authorization produced by an output (76) of the circuit (362> of   a synchronization criterion.   19. Device according to one of claims 8 to 18, characterized   in that the width of the window is such that it is greater by at least one unit than the maximum number of successive absences of   transitions that may exist in a package.   20. Device according to claim 19, characterized in that the width of the window is such that it is equal to two more elements than the maximum number of successive absences of transitions.   likely to exist in a package.   21. Device according to one of claims 9 to 20, characterized   in that it comprises a logic decoding circuit for acquiring and / or maintaining the synchronization and a means for decreasing the width of the window (F) preferably to a single element   when said logic state is decoded.