SK128094A3 - Method for transmission and/or synchronization of at least one component of a multiplex signal - Google Patents

Abstract

The invention relates to a method for synchronizing at least one analog component of a multiplex signal comprising at least one digital data channel. At the emission, in a channel (IRNS) is inserted at least one additional channel (RDS) comprising digital information, and comprising patterns having a synchronization signal (SYN) allowing to set in phase at least one analog component as well as said digital information. At the reception, the synchronization signal (SYN) is detected and allows to synchronize said analog component and the digital information of the additional channel. The synchronization at the reception may comprise a step for generating a signal with a characteristic frequency from a wave form generator (WG).

Description

A method of transmitting synchronization of at least one component of a mullet signal

Technical field

The invention relates to a method of transmitting and / or synchronizing at least one component of a mu-plex signal comprising at least one digital data channel.

BACKGROUND OF THE INVENTION

Some modern transmission systems need to have precisely defined phases (synchronous FM, digital DAB) between 11 iplex signals at different transmission points.

Analog multiplex signals that are identical at different transmission points are reproduced such that the signal is transmitted integrally in the analogue form on the distribution network. This solution is simple, but it requires powerful analog transmission systems and to accurately phase signals eg. transmitted on the same frequency (in synchronous FM) must be converted to digital form.

Known digital transmission systems carry phase setting information by synchronization transmitted by the digital distribution system. However, this information is not sufficient to allow phase adjustment of all analog components of the transmitted mul tip signal.

SUMMARY OF THE INVENTION

The aforementioned drawbacks are largely overcome by a method of transmitting and / or synchronizing at least one analog component of a mullet signal comprising at least one digital data channel. The method is characterized in that it includes steps on the broadcast side to insert an additional channel through which digital information of a certain binary volume can be transmitted. Said additional channel comprises features, at least some of which carry a synchronization signal, allowing the phasing of at least one analog component as well as the said digital information.

The method includes a step on the receiving side, by means of which said synchronization signal can be used to synchronize at least one of said analog component and additional channel digital information.

In particular, the digital data is data of digitized acoustic signals when transmitted in FM frequency modulation, the digital information of the additional channel is FM multiplex information.

The additional channel digital information may be RDS information.

The additional channel digital information is transmitted in NRZ-M. The transcoding is performed so that the phase of the NRZ signal changes each time the value of the transmitted RDS data is equal to 1, which makes it possible to eliminate the phase uncertainty on the reception side.

The additional channel features have a multiple execution period of a plurality of analog components and a binary digital information transmission.

The at least one analog component may be a carrier frequency signal. The upstream synchronization step comprises the step of generating said carrier frequency signal by a waveform generator (sine wave) that is synchronized by said synchronization signal.

Said waveform generator is digital and is equipped with a first cyclic reading device from the waveform memory. The synchronization of the waveform generator consists in setting the first cyclic reading device to a certain position.

The method of the invention comprises the step of decoding at least some of the digital information to address the sectors of the second wine-shape memory. Each sector may be reduced by a second means of cyclic reading.

Said features may be part of blocks beginning with a synchronization signal.

The method comprises the step of storing the characters of each block in sequential shift memory, wherein the sync (N + p) -th block (where p is an integer greater than or equal to zero) activates a cyclic counter for a specific calculation that is an N-th read signal. block contained in the sequential shift memory.

These features may be placed in frames.

According to a preferred embodiment, the additional channel digital information is allocated to data blocks with a different number of bits than the nominal number of bits of the additional channel information block. The method according to the invention comprises, on the receiving side, a step of activating memory with a sequential sequencer, the packets of the received data are ranked in order to re-establish the continuity of the information stacks and blocks. For information blocks eg. 104 bits of RDS is a data block length equal to n x 16 ms (n is an integer), i.e. n x 19 bits of RDS.

The additional channel digital information may be arranged in blocks of data, and the method comprises an address signal associated with said synchronization signal. The address signal is a label for reading the elements of the additional channel digital information block. The length of the access channel data block need not be the same as the length of the access channel digital information block, and offsetting this offset is performed by the address signal. Also, the length of the blocks of the additional channel may vary and the address signal may compensate for the deviation caused by the different length of the blocks. The transmit power of the additional channel may be e.g. 2 kbit / s, which allows the transmission of blocks of digital information of the RDS additional channel.

The invention also relates to the use of a method as defined above in a synchronous network comprising a transmission control transmitter and several repeaters. The use is characterized in that said additional channel is generated until the beginning of the transmission so that at least one analog component is synchronized in the same way on all repeaters. The additional channel digital information may be inserted after the control transmitters.

Overview of the figures in the drawing

BRIEF DESCRIPTION OF THE DRAWINGS

fig fig fig fig fig

2a shows a flow diagram of the method according to the invention for AES / UER radio transmission,

2b: block synchronization and block creation,: method of selecting and transmitting RDS information: NRZ coding timeline to eliminate phase uncertainty,: general frame layout: compression and decompression system for audio data transmission, fig.7: example of a frame equipped with a modifying word forming 8a, 8b: device for including RDS data in the transmission header and associated timing diagrams, fig. 9a, 9b, 10a, 10b: device for selecting EPS data from AES / UER signal, associated timing diagrams, device for RDS waveform generation and associated timing diagram, FIG. 11: an apparatus for implementing the method of the invention with a frame label read, FIG. 12: an example of a repeater with an insertion device

DETAILED DESCRIPTION OF THE INVENTION

The digital transmission system includes a path for transmitting acoustic frequency signals to which associated channels are available to users. The circuit diagram of the circuit according to the invention is shown in FIG. 1. It uses an AES / UER interface (European Radio Union Technical Document 3250 and its Appendix 1).

The system may transfer all or part of the information from the interface. Suppose at least one entire user path and the most important bits of the acoustic frequency signal are tiplexed in the mul digital transmission network.

Audio-digital information is transmitted in the AES / UER standard. Added data, e.g. RDS data is tiplexed from the AES / UER interface on the mul user path. This user path is formatted according to the AES / UER standard. The formatting according to the invention is performed by a SYBG block synchronization generator and the data is interleaved in packets by an INS insertion circuit. which is commonly used and conforms to the AES / UER data entry protocol.

The transmitted digital information INF is input to the REC receiver and the CLE timer.

The receiver sends D data to the EM transmitter, which transmits it in AES / UER to the RD transmission network. The timer CLE sends the clock signal H to the transmitter EM and the clock signal SF 1 to the SYBG e-block generator. the G data rate generator and the INS advertising circuit.

A data generator, e.g. according to the RDS (Radio Data System) standard, designated SRDS, it receives an SF2 frequency signal from the generator G and generates DRDS data signals and CLRDS clock signals for the INS advertising circuit. The INS advertising circuit sends an SHDLC signal to the transmitter. which is arranged according to the HPLC framework (see above standard). The insertion technique is known and complies with the AES / UER standard.

On the receiving side, the block synchronization signal is extracted and serves to accurately identify significant binary transmission moments, and the information transmitted in packets is decoded to control generators that are synchronized by block synchronization. The signals coming from the RD network in the AES / UER standard are applied to the input of the RE reception circuit. where they are demultiplexed. A clock signal HREF is generated in the RE reception circuit. The RE reception circuit sends demultiplexed DT data signals to the MC microcontroller. The SYNDET synchronization detection circuit sends a SYN block synchronization signal to the MC. From the microcontroller MC, the WDT signals corresponding to the waveforms generated are routed to the waveform generator WG. The waveform generator WG produces a counting signal RD. which is embedded in the MC. The waveform generator WG produces signals (carrier frequencies, subcarriers, RDS signals) which are thus transformed and accurately synchronized, which are directly usable with the SYN block synchronization signal e.g. to broadcast in synchronous FM.

User paths from the AES / UER interface are independent of other transmission paths in this interface (audio-digital paths, signaling paths). One user bit is associated with each acoustic sample. If the sampling frequency is Fe, we have a transfer of Fe x kbit / s. The division of this binary transmission into blocks according to the invention is accomplished by restoring all the frequencies necessary to synchronize the subcarriers used to reconstruct e.g. multiplexu FM.

For transmission in synchronous frequency modulation, the RD transmission network shall, at precise phase ratios, combine a 19 kHz control frequency, a 38 kHz sub-carrier and a 19/16 kbit / s RDS information transfer.

On the broadcast side, the user path is divided into blocks at the beginning of which is block synchronization (Figs. 2a, 2b, 3).

Block synchronization makes it easy to identify the exact moment of binary transmission that is used to activate the WG waveform generator.

The control frequency of 19 kHz and both of the above subcarriers (38 and 57 kHz) present the total number of periods every 1/19 ms.

The RDS information presents the total number of bits (19) every 16 ms.

The synchronization serves to identify the exact moment of each sine of the control frequency and the subcarriers and to identify the specific bit in the n x 19 bits of the binary 19/16 kbit / s binary RDS information.

The block length is chosen to be a common multiple of 1/19 ms (control and subcarrier) and 16 ms (RDS). The length that best fits the characteristics of the entire system is 64 ms. Such a block is shown in FIG. 2a. If the sampling rate is 32 kHz, the block contains 2048 bits. The information can be multiplexed in accordance with the standard. The beginning of the blocks is identified (SB) by detecting at least 7 consecutive units followed by zero. This block start allows the waveform generators to be synchronized and to produce multiplex signals that are identical at all transmission points. Frame start also allows RDS data to be synchronized. The length of 64 ms selected above corresponds to 76 bits of RDS, allowing to insert first bits of 76 first bits of the first RDS frame 104 bits (26 x 4) into the next block remaining 28 bits of the first RDS frame and 48 bits of the second frame etc.

Typically, one block length is n x 16 ms, which corresponds to n x 19 bits of RDS. One or more P1P2 packets, etc., containing n x 19 bits are inserted into each block. In the example described, a single packet with 76 bits of RDS is inserted in each block (FIG. 2) and this packet is mul tipped by assigning to packets that are already in the multiplex and come from other applications. RDS data comes from the above SRDS data source. The data selection that takes place in the RE reception circuit allows demultiplexing the digital data embedded in each block and storing it in the MC's memory.

The sine wave generators WG are controlled by the SB block synchronization phase. In addition, the SRDS waveform generator must encode the same bit on the same phase and the time reference is generated by the binary transmission power.

As shown in FIG. 3, the RDS bits contained in the N block are sent over the length of the next N + 1 block. At the beginning of the block (N + 1), the RDS bits are. marked PNRDS. of the previous N block, stored in a first input / first output FIFO memory and sequenced. The FIFO memory capacity corresponds to the bits of the RDS p blocks. In this case, the bits are RDS. marked here PNRDS. block N located at the beginning of block (N _ + _ L) ·

The block synchronization allows to accurately identify the moment of output of the first bit from the N block and to move it at the exact moment, i. at the end of block synchronization. As shown in FIG. 3, the first bit of the RDS packet in block N is processed by the waveform generator WG from the beginning of the block (N 4-1). The RDS information processed in this way by the RDS block generator is the same with respect to the synchronization of the user path block throughout the network. In FIG. 3, it is also seen that the PNRDS data packet forming the first packet in the N block is read at a rate such that all 76 bits contained therein occupy the full length (64 ms) of the block (N + 1) and thereby create continuity RDS frameworks.

The RDS radio data signal uses a two-phase code that, in transmission 1, has a transition in the bit order. Thus, this system contains phase uncertainty. Therefore, in addition to the above, transcoding is performed on the broadcast side. It consists in converting RDS information to NRZ-M and is implemented in such a way that the phase of the NRZ signal is reversed whenever the value of the transmitted RDS data equals 1.

The clock signal H in the RDS 19/16 kHz standard is synchronized by the above block synchronizations, and the modulating RDS signal is the sum of the NRZ-M and clock s H signals.

In this way, phase uncertainty is eliminated.

Audi from the road are transferred to other multiplexes, which are eg. used for systems with lower transmission power (Fig. 5). In this case, it is necessary (Fig. 6) to perform AUDCOMP acoustic information compression and UICOMP user path compression in the usual way, before sending it together with other signals to the ST transmission system. e.g. to a 2 Mbit / s transmission system such as the G 704 of the French Post and Telecommunications Administration.

Before returning to the AES / UER standard, the signal is decompressed in a known manner in AUDEXP and user paths are decompressed (JIEXP.

The sequence of digital data is divided into frames containing the acoustic frequency information INF and the user bits UI. The beginning of the frame is identified by the VT security member. The frame contains a constant number of n bits, e.g. 6400 bits (Fig. 7). Thus, the INF information field of this frame includes acoustic information and UI user information. This set of information can be tiplexed with other data. The VT frame security member and the time stamp bit allow the information contained in the frame to be demultiplexed easily (Fig. 5). The UI user bits are arranged in an independent channel and are routed in the same way as the user paths from the AES / UER interface, but with less binary power (e.g., 2 kbits / s). This, in particular in the audio system, assumes that the RDSobs signal pulled in the frames carries only the mo10 of the RDS signal on the transmitting side. which leads to a significant change is carried out, if it is as described above, that the start of the power block blocks d i f i c i e.

Compression and decompression of acoustic frequency data is performed by various known algorithms (almost instantaneous compression, etc.). Also, user data can be compressed.

Block synchronization possible, under the same conditions case. The length is selected so that it controls a set of significant frequency signals (carrier frequencies, subcarriers, RDS frequencies) and that the first bit of each block is not always at the same location of the frame. In the example shown in FIG. 7 is 50 user bits U0 ...... U49 within 6400 bits. The beginning of the modifying bit member comes e.g. in U1 and repeats in the same position in other frames (if any).

Thus, the modifying member may serve as a signal to synchronize waveform generators for sine wave 19, 38 and 57 kHz, which are generated by a permanent memory containing the samples necessary to form the sine wave. The modifying member serves as a flag for reading from the permanent memory until the next modifying member arrives.

RDS information is largely repeatable. Arranged in four 26-bit frames that can be repeated every 104 bits, these 104 bits are considered as a full wave form read from memory at a suitable rate. In this case, the modifying members also serve as a read-out flag. The change of the RDS information can be performed at a slower transmission and is activated at the beginning of the 104-bit blocks once a new block has been created. These changes are made in 26-bit frames. A CRC redundancy check signal is placed in each 26-bit frame. Thus, binary transmission in the distribution network is reduced by transmitting only RDS information. that changes.

As shown in FIG. 8a and 8b, an AES / UER INF signal is received on the CLE timer circuit, and the timer produces a 32 kHz SF 1 signal fed to a data frequency generator G and a frequency divider DIV (2048 times) forming the above SYBG circuit. The frequency generator G generates a 19 kHz SF2 signal to the SRDS data generator RDS. The SF 1 signal is also routed to the MCI microcontroller (e.g., INTEL 8044), which forms the INS insertion circuit. The DIV frequency splitter divides the SF 1 signal 2048 times and produces a SYN synchronization signal every 64 races. SRDS Data Generator RDS produces DRDS data signals and a 19 kHz CLRDS clock signal. This allows the MCI microcontroller to produce a SHPLC signal according to the HPLC frame embedded in the AES / UER EM transmitter signals. It is recalled that the normalized HPLC frame includes a DR frame start tag, AD address, one octet of the CO control, INF information field. the CRC redundancy check bits and the DR 'end of the wing mark. The sync signal SYN is located in a block header in the form of a character containing at least seven consecutive units before zero. Each block can contain several frames.

SYN signals transmit 2048 bits blocks at a transfer rate of 32 kbit / s (Fig. 8b). The CLRDS signal transmits 76 RDS bits during the same time. The RDS frame may be located at the beginning of the block and is interleaved according to the AES / UER protocol.

The reception side synchronization is shown in FIG. 9a, 9b. 10a and 10b. Formatted signals from the digital network are transmitted by the EM transmitter and applied to the input of the RE receiver. The RE receiver circuit transmits a DT data signal and a HREF clock signal, which are routed to the SYNDET detection circuit inputs and to the SHIJU i

connected to the central unit! CPU MC2 (eg 8044 from INTEL). The CPU also receives the SYN sync signal generated by the SYNDET circuit.

The MC2 generates a reset RS signal and a WR write signal for the FIFO1 sequential memory. FIFO1 memory prevents the microcontroller from overloading, which does not have to track every bit of RDS signals.

The RDS user channel signals are routed from MC2 via BUS1 to FIFO1. The read signal RD receives the FIFQ1 and generates the DRDS signals of the RDS data and the EF signal. indicating to the MC2 that the memory is empty. The EF signal indicates that the memory has finished reading the previous block. Microcontroller MC2 generates a reset signal of both RS memory and FIFO1 and then a WR write signal. The microcontroller verifies that the SYN and EF signals arrive at the same time and otherwise resets the FIFO1 RS memory. Thus, the FIFO1 memory is only filled at the moment of its reading, and the MC2 holds the RDS bits. which are not yet stored in FIFQ1 memory. The MC2 microcontroller sends the DRDS signal of the RDS data to the DEC decoder. which generates a RD read CLRDS signal for FIFQ1 memory. The DEC decoder sends data and addresses via BUS2 to the DSP. The DSP receives a SYN sync signal from the SYNDET circuit and a FECH sampling frequency from the RE receiver (e.g., a multiple of HREF, especially 256 kHz for a 32 kHz HREF). The DSP sends digital RDS data to BUS3. The DEC decoder also includes programmable PROM memory. into which the waveforms are embedded. The following describes how to generate RDS wines.

The DSP signal processor (e.g., MOTOROLA 56001 microcontroller) is programmed to cyclically generate addresses, e.g. in the 12-bit AO .... Al1 code and cyclically addresses the 12 lowest weight bits of the PROM address. When the highest address is reached, the counter is reset. Also, the SYN sync signal resets the counter. Synchronization is accurate when both resets occur simultaneously. When reset, bit A11 changes the value. The change detection then allows the SY synchronization signal to be generated. which appears even when the SYN signal does not occur in every period. Also, bit A1 1 changes the value when the counter reaches half the maximum number. Thus, the SY signal has the same frequency as the RDS signal (timing diagram in Fig. 10b).

The weight-highest bits of the address A 2 are used to completely transform and phasing analog RDS signals (Fig. 10a) using RDS data. A13. A14 memory PROM. The CLK clock signals maintain the decoder speed at a frequency that is a multiple of 19 kHz and which corresponds to the read rate frequency in the programmable PROM. containing the shapes of sampled wines converted to digital form. The D1 type of the BI0 is fed from the precursor above with a high Al1 bit forming the SY signals, and the CLDRS signal is obtained from the inverted output of the BI0 (the gateway OU marked 30, whose input is connected to ground). This signal controls RD reading from FIPO1 memory. FIFO1 sends the DRDS data of the RDS data to the D data input of the D-type BO whose data Q output (point A) is connected to the D data input of the BI balance. whose output Q (point B) is connected in the same way to the balance B2, from the output Q of which the phase signal (0) leaves the input to the address A14 of the PROM (the highest weight bit).

The signals at points A and B enter the OU gate (ref. 10), whose output (point C) is routed to the input D of the balance B3. The B3 output (point E) is connected to B4. whose output Q (point F) is connected to input A1 (weight bit immediately lower than bit A14). The non-inverted output 2 of the scale B3 (point E) is coupled to the address input A12 (bit weighted lower than the bit AI3 of the PROM). Fig. 10 shows a timing diagram of the signals at points A, B, C, E and F and the phase signal (¢). The phase signal C ¢ 5) accurately distinguishes the phase in the code NR Z-M · mentioned in 14 of FIG. 4. The signals at points E and F (bit A1 '2 and A1 3 of the PROM memory) make it possible to make a selection between four possible waveforms (near phase) suitable for the reshaped analog RDS data signal. The samples corresponding to the restored RDS data curve are output from the PROM outputs DO ..... D7 (as shown in the lower part of Fig. 10b as an example, together with signal timing diagrams). To achieve file synchronization, it is sufficient for the DSP program to control a reader providing AO ....... A11 addresses for the intended calculation, e.g. to calculate 0 as soon as the synchronization signal SYN indicates the start time of the synchronization. Detection of the A11 bit (SY signal) and subsequent generation of the CLRDS signal activates the reading in the FIFO1 memory and thus portable synchronization of the RDS signal over time and without phase uncertainty.

Obviously, the described synchronization was complicated by an RDS signal containing data. In this case, it is necessary to perform address decoding without which it is not possible to address various files of the programmable PROM. The same method can be used to generate carrier frequency and subcarrier signals without decoding. In this case, it is sufficient for the DSP to activate the above-mentioned cyclic counter to reset or set a certain number) as soon as the synchronization signal SYN indicates the time of synchronization for these signals. Optionally, the cyclic counter can be set to a variable number, allowing other frequencies to be obtained. In this case, the SYN signal is followed by an address signal indicating the value to which the cyclic counter is to be set.

In the case of a 19 kHz synchronous FM network, 38 kHz and 57 kHz (RDS) subcarriers, the DSP cyclically controls several PROMs (or one larger capacity PROM) so that all signals (carrier frequency, subcarriers, and possibly the RDS signals) were in the same position at the time of synchronization with the SYN signal, e.g. to position even zeros.

Circuit SYNDET. shown in FIG. 11 is a shift register with eight outputs. The first seven outputs and the eight inverse enter the invert gate 2.0 · The functional relationship between the FIF01 memory and the DEC decoder is the same as described above. In contrast, the RDS data that is decoded to address the programming of the PROM (FIG. 10a) is taken from the MEM (which may be an arbitrary RAM selection of the MC2). Said memory can be refreshed with each modification of the RDS data (104 bits) and is read by a cyclic counter which is controlled by the MC2 microcontroller.

For example, the low bit rate utility channel r = 2 kbits / s comprises blocks of n = 1024 bits of 512 ms length, corresponding to a length of 608 bits of RDS. For example, if the SYN sync signal in the first block corresponds to a 0 value of the cyclic counter, then the next block must have a different value because 608 is not divisible by 104 (104 bits of RDS information stored in the MEM memory). The remainder of the division 608 to 104 is 88. Thus, the synchronization signal for the next block corresponds to a value of 88 cyclic counter, for the next 72 etc. Thus, an ADR address packet is attached to the SYN signal. which controls the MC2 microcontroller cyclic counter as the label arrives after the SYN signal. the trolley MC2 moves after receiving the SYN signal, decodes the address packet ADR in the DT data. which directly or indirectly provides a value to be written to the cyclic counter for the beginning of the next block. The SYN synchronization signal with the associated ADR address packet need not occur at the beginning of each block. Its function is to check the correct course of synchronization and therefore it can be irregularly included.

It is particularly preferred that the phase information is attached to the label. For example, this will allow you to directly check your balance

Because the ADR packet from the block. A microcontroller 16 of a signal such as an RDS signal.

In FIG. L2 is a repeater equipped with AES / UER REC receiver, REM transmitter. which transmits signals in the AES / UER standard to the RDS data input circuit. which is controlled by a CER 32 kHz timer.

According to the invention, it is necessary for the synchronous circuit to have the synchronization signal in the multiplex at the beginning of the transmission. The RDS data may be inserted at the beginning or in the repeater after the control transmitter, as shown in FIG.

12th

In this case, the DIV circuit is not required (Fig. 8a) since the AES / UER multiplex already contains a synchronization signal.

Claims (18)

PATENT 'NAPOKY t. A method of transmitting data and / or synchronizing at least one analog component of a mullet signal comprising at least one digital data channel, characterized in that on the broadcast side it comprises the step of inserting an additional channel suitable for transmitting digital information of a certain binary volume, , at least some of which carry a synchronization signal (SYN), allowing the phasing of at least one analog component as well as said digital information. 2. The method of claim 1, wherein the receiving side and using the synchronization signal (SYN) comprises the step of synchronizing at least one of said analog component and digital information of the added channel. 3. The method of claim 1, wherein the digital data is digital acoustic signal data transmitted in FM frequency modulation and the digital additional channel information is FM multiplex information. 4. The method of clause 3, wherein the additional channel digital information is RDS information. 5. A method according to any one of the preceding claims, wherein the additional channel digital information is transmitted in NRZ-M and the recoding is performed such that the phase of the NRZ signal is changed whenever the value of the transmitted RDS data is equal to 1, eliminate phase uncertainty on the revenue side. 6. A method according to any one of the preceding claims, characterized in that the features of the add-on channel have a multiple length of a period of several analog components and a binary digital transmission. 7. The method of any one of the preceding claims, wherein the at least one analog component is a carrier frequency signal and wherein the reception side synchronization step comprises the step of generating said carrier frequency signal by a waveform generator (WG). which is synchronized by said sync signal (SYN). 8. The method of claim 7, wherein said waveform generator (WG) is digital and is provided with a first waveform memory reader (PROM) means, wherein said synchronization of said waveform generator (WG) consists in the first means of cyclic reading to a certain position. 9. The method of any one of claims 1 to 8, comprising the step of decoding at least some of said digital information to address sectors of a second waveform memory (PROM), each sector being read by a second cyclic reading means. Method according to any one of the preceding claims, characterized in that said features are part of blocks beginning with a synchronization signal (SYN). 11. The method of claim 10, comprising the step of storing the characters of each block in a sequential shift memory (FIFO), wherein the synchronization signal (N + p) of the block (wherein p is an integer greater than or equal to 1) activates a cyclic counter for a specific calculation that is a read signal of the N-th block contained in the sequential shift memory (FIFO). 12th process by according to points 1 to 9, characterized framework. ú c i sa that stated features They are 13th process according to any of the previous points, z n a ignating s and 1 : ý m that digital Information The auxiliary channel is interleaved in the form of blocks containing a different number of bits than the nominal number of bits of the auxiliary channel information block, and comprises, on the receive side, a sequential shift memory (FIFO) memory activation step in which received data packets are sequenced to re-establish the continuity of the blocks of information. 14. The method of clause 13, wherein for blocks of information FDS bits 104, the length of the data blocks is n x 16 ms (n is an integer), i.e. n x 19 RDS bits. 15. The method of any preceding claim, wherein the additional channel digital information is arranged into data blocks and comprises an address signal (AD) associated with said synchronization signal (SYN). The address signal is a read-in-memory signal (MEM) of the additional channel digital information block. 16. The method of clause 15, wherein the length of the access channel data block is not the same as the length of the access channel digital information block and the offset is performed by address signal (AD). 17. The method of claim 16, wherein the length of the additional channel blocks is variable. 18. The method of item 16 or 17, wherein the transmit power of the additional channel allows the transmission of blocks of digital information of the RDS of the additional channel. 19. Use of a method according to any one of the preceding points in a synchronous network with a transmission control transmitter (EM) and multiple repeaters (REM), characterized in that said additional channel is generated in the transmission header so that at least one analog component is synchronized in the same way on all repeaters. Use according to clause 19, characterized in that the digital information of the additional channel is inserted after the transmission control transmitter.