FR2684825A1 - JUSTIFICATION PROCESS. - Google Patents

Abstract

The invention relates to a justification method usable for configuring frames when the frame consists of a fixed number of "bytes" of constant length. To achieve justification, with a device which is as simple and secure as possible, one or more "bytes" of the frame are used as justification opportunity "bytes" (Z) which, depending on the need for justification , contains either information bits (I), or stuffing bits without information.

Description

JUSTIFICATION PROCESS.

  The present invention relates to a method of justifying-

  tion used in frame composition when the frame

  includes a fixed number of "bytes" of constant length.

  This method is suitable for example for a justification carried out when a plesiochronous information signal of 139.264 Kbit / s is composed in a container VC-4 of the

  "SDH" (Synchronous Digital Hierarchy).

  Currently, the known method includes nine ran-

  which are identical with each other according to the way in which they are constituted and which

  consist of a path overhead -

  POH ") of a" byte ", twenty groups of binary information of twelve" bytes "(96 I), and a" byte "(W, X, Y, Z) placed at the beginning of each group for bits d information (I), stuffing bits (R), header bits

  ("overhead bits O"), justification opportunity bits -

  tion (S) and justification check bits (C).

  Figure 1 shows schematically a row of the door

  information, (i.e. a VC-4 container)

  of such a conventional SDH frame.

  2 - The legend accompanying Figure 1 shows that the "byte" Z contains a justification opportunity bit S which, depending on the need for justification, is either a bit

  of information, or a stuffing bit without information.

  A need for justification arises when the speed of an incoming information signal deviates from its nominal value by any variation, for example upwards, so that the bits which the composition unit does not process tend to accumulate in the buffer memory of said unit In such a case, the use of a justification bit enables the reading of this buffer memory at a speed slightly higher than normal, so that the degree of filling of the memory can

  be kept as constant as possible in the composition

  sition of a current SDH standard, the nominal speed 137.264 Kbit / s means that two of the "bytes" Z of the nine rows of the container VC-4 contain a bit of information, while the remaining seven are bits

without information.

  Thus, if the speed of an incoming information signal is greater than its nominal value, the frame comprises seven bit positions into which information can be inserted If the speed of a signal

  of incoming information is less than its nominal value

  nale, two bits of information can be removed from the

  frame using justification opportunity bits -

  tion and be replaced by bits without information.

  However, in a standard VC-4 composition the use of

  justification opportunity bits are problematic.

  Given the high signal speed, approximati-

  140 megabits / s, the use of justification opportunity bits requires a very fast or complex circuit for such justification bit by bit, especially

  when the SDH is also organized as a "byte".

  3 - The invention therefore more particularly relates to a new justification method making it possible to overcome

  this problem and perform a rationale with a dis-

positive much simpler.

  To this end, it proposes a justification method characterized in that, to perform the justification, one or more "bytes" of the frame are used as "justification bytes" (Z) which, depending on the need justification, contain either information bits (I), or padding bits without information.

  The opportunity justification bits are, preferably,

  rence, distributed one per row.

  In the case where the method according to the invention applies to the composition of a plesiochronous information signal of 139.264 Kbit / s, the invention is characterized in that in each row of the frame, one of the first "bytes "is used entirely as a" byte "of opportunity

  justification (Z) which, depending on the need for

  fication, contains either information bits (I) or stuffing bits without information, so that, at the nominal speed of the frame, the justification opportunity "bytes" (Z) in this row contain bits

  of information, and the "bytes" of justification opportunity

  tion (Z) of two rows contain bits without information

  mation. An embodiment of the invention will be described below,

  by way of nonlimiting example, with reference to the

  attached figures in which: FIG. 1 is a known composition diagram of a row of a VC-4 container of an STM frame; 4 - Figure 2 shows the row of Figure 1, composed according to the invention; Figure 3 shows the provision of justification opportunity "bytes" in counters.

VC-4.

  FIG. 2 shows an embodiment of the invention concerning the composition of a plesiochronous information signal of 140 megabits / second inside a row of a container VC-4 of frame STM-1 This diagram schematically shows that this composition completely corresponds to the known solution of FIG. 1 The only difference is that the "bytes" Z are now

  fully allocated to the supporting opportunity bits

  tion S, while in the known case of Figure 1, six of the "byte" Z bits have been assigned to information bits I, and only one to one justification opportunity bit S. Figure 3 shows how a justification opportunity "byte" is applied to the composition of a signal

  in a VC-4 container.

  Figure 3 shows the filling of the container in the case of a nominal speed, the "bytes" Z represented in gray (grayed out) being "bytes" containing information, and the "bytes" Z represented in white

  being stuffing "bytes" without information.

  The "bytes" containing information are, therefore, distributed in seven of the nine lines of the container VC-4, and

  the "bytes" Z which consist of bits without information

  tion are distributed in two rows.

  In the example in FIG. 3, these two rows correspond to

  lay in the third and eighth rows.

  - As shown in Figures 2 and 3, in accordance with the method according to the invention, the justification is not carried out

by bits but by "bytes".

  The implementation of the method is, therefore,

considerably simplified.

  In the example shown in FIG. 2, the bits C in the

  "bytes" X always indicate the use of the justification

  cation C = O indicates that in the row concerned, Z is a "byte" of information while C = 1 indicates that Z

is a "byte" without information.

  The composition illustrated in Figure 2 is remarkably

  simpler to carry out in the device than the composition

  tion shown in Figure 1 No bit rotation function is required in CMOS-oriented logic "byte" to move the limit of "byte" in response to the use of justification bits Now,

  the information is always in the form of "bytes"

  plets A simpler realization results in a safer treatment and a less expensive solution In addition, when the composition of FIG. 2 is used, the flicker problem generated by the justification before the octuple filtering is resolved, in comparison with the composition of Figure 1, because now the justification bits are in the form of

  eight-bit "bytes" and not as individual bits

  duels Since the justification frequency is 16 k Hz A, the flicker is effectively filtered by the phase lock of the desynchronizer In addition, as the phase changes of 24 IU caused by the pointers must be treated by the desynchronizer in all cases, no new requirements arise

  also for data buffer lengths

born.

6 2684825

  The invention is not limited to the preceding embodiment.

  as described: it can also be applied to

  other frame compositions or large flow rates

  There are problems with bit-by-bit justification. 7 -

Claims (3)

Claims   1 Justification method usable in the composition of frames when the frame comprises a fixed number of "bytes" of constant length,   characterized in that for justification one or more   frame "bytes" are used as   justification opportunity "bytes" (Z) which, depending on   tion of the justification need, contain either information bits (I) or stuffing bits without information. 2 The method of claim 1 wherein the frame consists of a number of identical rows with each other as regards how they are configured, characterized in that the justification "bytes"   of opportunity (Z) are distributed at the rate of one per ran-   aged. 3 Justification process that can be used when a 139.264 Kbit / s plesiochronous information signal is configured in an SDH (Synchronous Digital Hierarchy)   VC-4 container containing nine rows, which are identical   ticks with each other as to how they are configured and which in turn consist of a path header (POH) of one "byte", twenty groups of information bits of twelve "bytes" (96 I), and a "byte" (W, X, Y, Z) placed at the beginning of each group for information bits (I), stuffing bits (R), bits of header (0), bits   justification opportunity (S) and com- bits   justification command (C), characterized in that in each row of the frame one of the first "bytes" is used entirely as   justification byte (Z) which, depending on   justification need, contains either bits   information (I) or stuffing bits without information   8 - tion, so that for a nominal frame rate, the justification opportunity "bytes" (Z) of seven rows contain information bits and the justification opportunity "bytes" (Z) of two rows contain bits with no information.