CN101252403B - Realizing method of traffic transmission in light transmitted network - Google Patents
Realizing method of traffic transmission in light transmitted network Download PDFInfo
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- CN101252403B CN101252403B CN2008100008281A CN200810000828A CN101252403B CN 101252403 B CN101252403 B CN 101252403B CN 2008100008281 A CN2008100008281 A CN 2008100008281A CN 200810000828 A CN200810000828 A CN 200810000828A CN 101252403 B CN101252403 B CN 101252403B
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Abstract
The invention discloses an implementation method of the service transmission in an optical transmission network. The method includes the steps as follows: the service input unit and the service output unit are configured with the same system clock or the same source system clock; the service data received from the external is stored and adjusted by the service input unit according to the system clock; the adjusted service data, the frame head signal received from the external, the system clock and the generated adjustment indication information are encapsulated into a SDH frame signal; the SDH frame signal is transmitted to a core cross unit; the service output unit receives the SDH frame signal from the core cross unit; the service output unit outputs the adjusted service data in the SDH frame signal according to the adjustment indication information, the system clock and the service recovery clock. Based on the implementation method of the service transmission in the optical transmission network, the ODU service can be transmitted through the SDH device; various mapping modes are fulfilled; the implementation method is simple; the high quality service clock signal can be recovered.
Description
Technical field
The present invention relates to the optical-fiber network technical field, particularly relate to the professional implementation method that transmits in optical transport network.
Background technology
Demand along with development of science and technology and market, promoting the expansion of traffic capacity, the communication transmission technology has experienced several developing stage, from PDH (the PDH (Pseudo-synchronous Digital Hierarchy) plesynchronous digital hierarchy) technology at initial stage to SDH (all synchronous digital hierarchy of synchronous digital hierarchy) technology, arrive OTN (optical transfer network opticaltransport network) and WDM (wavelength division multiplexing wavelength divisionmultiplexing) technology then, the appearance of each new transmission technology, all be to be based upon on the basis of prior art, the product needed of new technology can with the existing product compatibility.Under the situation that the SDH network has existed in a large number, OTN product needed and the coexistence of SDH Web-compatible, the OTN business can transmit by the SDH network, and the SDH business can transmit by OTN is professional.In standard, defined the OTN business for this reason and be mapped in the SDH business and transmit, and the SDH business is mapped to the method that transmits in the OTN business.
In the G.707 standard of ITU-T, defined ODU (Optical Channel Data Unit-k opticalchannel data unit, the frame structure of data cell in the OTN standard) mapping enters the method among the SDH, VC4 in the SDH frame (virtual container virtual container, the 4th grade) mode of employing cascade, form cascaded series, the professional mode of mapping that adopts of ODU is put into cascaded series, transmits with the SDH trafficwise then.In standard, the ODU1 mapping enters cascaded series C-4-17C, and the ODU2 mapping enters C-4-68C.ODU1 is mapped to the concrete mapping mode of C-4-17C as figure, and wherein D represents valid data, and R represents fixing filling, and C represents to adjust chance, and CCCCC=00000 represents that S is valid data, and CCCCC=11111 represents that S fills in byte.In the terminal of business transmission, need from cascaded series, recover data service, recover the clock signal of original professional ODU1 simultaneously.Because professional discontinuous in capacity in mapping process, mapping simultaneously produces a large amount of Mapping jitters, and business recovery is caused difficulty.Because OTN Business Stream speed is very high, the speed of lowest speed ODU1 business has been 2.5Gbits/s, can't carry out single bit and carry out the speed adjustment when mapping is conciliate in mapping, but a whole byte adjusts, the so once adjustment shake that just brings 8 UI.According to the G..8251 definition, the OTN business requires very high to shake, in order to lower the jitter value of recovered clock, people have adopted many methods, as patent CN1848717A, need to reduce the jitter value of recovered clock, to satisfy index request through complicated circuit such as smoothing processing, two-stage FIFO.
The mapping mode that provides in the standard is a kind of general mode, is fit to all application scenarios, and professional recovered clock shake is bigger, needs to adopt the mode as patent CN1848717A to reduce the clock jitter value, the restoration methods complexity.Because mapping method is single; in some cases; in the SDH equipment as compatible OTN business; cross unit needs the M:N protection; in order to keep the same protected mode of the professional employing of SDH industry and OTN; cross unit is in full accord simultaneously; again can be smoothly from the SDH upgrading service under the OTN business model; if one the ODU1 business is mapped to 20 STM-1 (synchronous transport module Synchronous Transport Module level-N; the first estate) container levels joint group is realized then convenient, needs to adopt different mapping modes like this.
Summary of the invention
Make the present invention according to the problems referred to above, the purpose of this invention is to provide a kind of implementation method of professional transmission in optical transport network.
According to of the present invention in optical transport network the professional implementation method that transmits, may further comprise the steps: for professional input unit and professional output unit are provided with same system clock or homologous system clock; Professional input unit will be adjusted from the business datum storage of outside and to it according to system clock, adjusted business datum is packaged into the SDH frame signal with coming from outside header signal, system clock and the adjustment indication information that is generated, and the SDH frame signal is sent to the core cross unit; Professional output unit receives the SDH frame signal from the core cross unit, generates according to the adjustment indication information in the SDH frame signal and adjusts index signal, and generate the business recovery clock according to header signal and system clock; And professional output unit is according to adjusting index signal, system clock and business recovery clock with the adjusted business datum output in the SDH frame signal.
In addition, in the method, professional input unit will be realized by business datum being cached to the input fifo buffer from the business datum storage of outside according to system clock.
In addition, in the method, also comprise: adjusting module produces the adjustment indication information according to the capacity of input fifo buffer; Read business datum from input the fifo buffer according to system clock, and according to adjusting the business datum that indication information determines whether that mutiread goes out or reads an adjustment less; And with adjusted business datum from the input fifo buffer be sent to package module.
In addition, in the method, adjusted business datum is packaged into the SDH frame signal with the adjustment indication information that comes from outside header signal, system clock and generated is to encapsulate by the package module in the professional input unit to realize to professional input unit.
In addition, in the method, also comprise: after the core cross unit receives the SDH frame signal, adjusted business datum in the SDH frame signal and adjustment indication information are cached in the output fifo buffer at professional output unit.
In addition, in the method, it is to generate the adjustment index signal by the adjustment analytic unit in the professional output unit to realize that professional output unit generates the adjustment index signal according to the adjustment indication information in the SDH frame signal.
In addition, in the method, professional output unit is to generate the business recovery clock by the clock generating unit in the professional output unit to realize according to header signal and system clock generation business recovery clock.
In addition, in the method, clock generating unit in the professional output unit generates the business recovery clock and comprises: counter is according to header signal and system clock, the umber of pulse of the adjustment index signal in the frame time that adds up, and output count value; Accumulator adds up count value under evenly spaced impulsive condition, and the carry index signal pulse output that will add up and overflow; And phase-locked loop utilizes the pulse of carry index signal to generate the business recovery clock.
In addition, in the method, phase-locked loop utilizes the pulse of carry index signal to generate the business recovery clock to comprise: first frequency divider according to the carry index signal pulse system clock is carried out frequency division, and second frequency divider carries out frequency division to the business recovery clock; Phase discriminator carries out phase demodulation with the fractional frequency signal of first frequency divider and the output of second frequency divider, and identified result is sent to low pass filter; Low pass filter filters identified result, to generate voltage-controlled signal; And voltage controlled oscillator produces the business recovery clock according to voltage-controlled signal.
By above-mentioned aspect of the present invention, can realize that the SDH equipment that passes through of ODU business transmits, can satisfy various mapping modes, implementation method is simple, can recover high-quality business clock signal.
Other features and advantages of the present invention will be set forth in the following description, and, partly from specification, become apparent, perhaps understand by implementing the present invention.Purpose of the present invention and other advantages can realize and obtain by specifically noted structure in the specification of being write, claims and accompanying drawing.
Description of drawings
Accompanying drawing is used to provide further understanding of the present invention, and constitutes the part of specification, is used from explanation the present invention with embodiments of the invention one, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 shows the flow chart according to the implementation method that business transmits in optical transport network of the embodiment of the invention;
Fig. 2 shows according to STM-1 frame structure schematic diagram in the SDH standard of the embodiment of the invention;
Fig. 3 shows a plurality of STM-1 frame cascade structure schematic diagrames according to the embodiment of the invention;
The ODU1 that Fig. 4 shows according to the embodiment of the invention is mapped to VC4-17X level link composition;
Fig. 5 shows the device structure schematic diagram according to the embodiment of the invention;
Fig. 6 shows the mapping mode according to a kind of reference of the embodiment of the invention;
Fig. 7 shows the input unit structure chart according to the embodiment of the invention;
Fig. 8 shows the output unit structure chart according to the embodiment of the invention;
Fig. 9 shows the working timing figure according to the accumulator of the embodiment of the invention;
Figure 10 shows the frequency divider A work schematic diagram according to the embodiment of the invention; And
Figure 11 shows the frequency divider B work schematic diagram according to the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein only is used for description and interpretation the present invention, and be not used in qualification the present invention.
Fig. 1 shows the flow chart according to the implementation method that business transmits in optical transport network of the embodiment of the invention.
As shown in Figure 1, may further comprise the steps: step S102, for professional input unit and professional output unit are provided with same system clock or homologous system clock; Step S104, professional input unit will be adjusted from the business datum storage of outside and to it according to system clock, adjusted business datum is packaged into the SDH frame signal with coming from outside header signal, system clock and the adjustment indication information that is generated, and the SDH frame signal is sent to the core cross unit; Step S106, professional output unit receives the SDH frame signal from the core cross unit, generates according to the adjustment indication information in the SDH frame signal and adjusts index signal, and generate the business recovery clock according to header signal and system clock; And step S108, professional output unit is according to adjusting index signal, system clock and business recovery clock with the adjusted business datum output in the SDH frame signal.
In addition, in the method, professional input unit will be realized by business datum being cached to the input fifo buffer from the business datum storage of outside according to system clock.
In addition, in the method, also comprise: adjusting module produces the adjustment indication information according to the capacity of input fifo buffer; Read business datum from input the fifo buffer according to system clock, and according to adjusting the business datum that indication information determines whether that mutiread goes out or reads an adjustment less; And with adjusted business datum from the input fifo buffer be sent to package module.
In addition, in the method, adjusted business datum is packaged into the SDH frame signal with the adjustment indication information that comes from outside header signal, system clock and generated is to encapsulate by the package module in the professional input unit to realize to professional input unit.
In addition, in the method, also comprise: after the core cross unit receives the SDH frame signal, adjusted business datum in the SDH frame signal and adjustment indication information are cached in the output fifo buffer at professional output unit.
In addition, in the method, it is to generate the adjustment index signal by the adjustment analytic unit in the professional output unit to realize that professional output unit generates the adjustment index signal according to the adjustment indication information in the SDH frame signal.
In addition, in the method, professional output unit is to generate the business recovery clock by the clock generating unit in the professional output unit to realize according to header signal and system clock generation business recovery clock.
In addition, in the method, clock generating unit in the professional output unit generates the business recovery clock and comprises: counter is according to header signal and system clock, the umber of pulse of the adjustment index signal in the frame time that adds up, and output count value; Accumulator adds up count value under evenly spaced impulsive condition, and the carry index signal pulse output that will add up and overflow; And phase-locked loop utilizes the pulse of carry index signal to generate the business recovery clock.
In addition, in the method, phase-locked loop utilizes the pulse of carry index signal to generate the business recovery clock to comprise: first frequency divider according to the carry index signal pulse system clock is carried out frequency division, and second frequency divider carries out frequency division to the business recovery clock; Phase discriminator carries out phase demodulation with the fractional frequency signal of first frequency divider and the output of second frequency divider, and identified result is sent to low pass filter; Low pass filter filters identified result, to generate voltage-controlled signal; And voltage controlled oscillator produces the business recovery clock according to voltage-controlled signal.
Fig. 2 shows according to STM-1 frame structure schematic diagram in the SDH standard of the embodiment of the invention.
SDH (Synchronous Digital Hierarchy) (SDH) is the optical communication standard that International Telecommunication Association formulates, the structure of this standard basic grade frame STM-1 (STM:Synchronous transport module Synchronous Transport Module level-N the first estate) is 9 row, 270 row, the position of each row and column is bytes, totally 2430 bytes transmit 8000 frames each second.Frame structure as shown in Figure 2, preceding 9 classify the overhead byte of frame structure as, the back 261 is classified the virtual container byte as.The path overhead byte that 9 bytes are arranged in the 261 row virtual containers, overhead byte of every row.When the AU of SDH pointer value was certain fixed value, 9 path overhead bytes were arranged in the 10th row of frame structure, and all the other 260 row all are bytes of payload.When client's business (as PDH, Ethernet etc.) needs by the transmission of SDH network, client's business is mapped to the bytes of payload zone, form with the SDH frame transmits in the SDH network, takes out customer information at point of destination from the bytes of payload zone, recovers the original data message stream of client.
Fig. 3 shows a plurality of STM-1 frame cascade structure schematic diagrames according to the embodiment of the invention.The ODU1 that Fig. 4 shows according to the embodiment of the invention is mapped to VC4-17X level link composition.
Be described below in conjunction with Fig. 3 and Fig. 4.In the communication transmission technology by the SDH network to OTN net transition stage, in order to realize that SDH network and OTN network can be compatible, international standard has been formulated two kinds of mapping modes, a kind of is the SDH frame signal with the identity map of client signal to ODU frame (signal frame of OTN network), another is the ODU signal with the identity map of client signal to the SDH frame, realizes that any network in two kinds of networks can both transmit the signal of another network.When the ODU frame need be mapped in the SDH frame structure, because the Business Stream speed of ODU frame is big, ODU1 is 2.499G bits/s, ODU2 is 10.037G bits/s, ODU3 is 40.319G bits/s, and the payload area rate in the SDH frame structure has only 139M bits/s, and basic frame structure can't capacity ODU service rate.In order to improve the size of container, adopt the multiframe cascade system, improve the size of master container.SDH frame structure cascade system such as Fig. 3, when n SDH frame carried out cascade, the mode that each SDH frame adopts byte to interleave was lined up, and forms the frame structure of one 9 capable 270*n, and container capacity is brought up to n doubly, to hold the service signal of higher rate.When the ODU1 business was mapped among the SDH, an ODU1 Business Stream was mapped in 17 SDH frame cascaded series.International standard provides the mapping mode that a kind of ODU1 is mapped to 17 SDH cascaded series, as Fig. 4.Be mapped to byte in the container by information byte D, fixedly fill in byte, bit R, adjust control C bit and adjust chance byte S and form.Effective business information content is deposited in the information byte position, and the invalid information of filling in is deposited in R byte and bit position, is fixed value.Adjust control bit and be the control indication information, the content of chance byte is adjusted in indication.Adjusting bit employing majority vote principle for per 5, is 1 o'clock as 3 bits, thinks that all adjust control bits is 1; As 3 bits is 0 o'clock, thinks that all adjust control bit is 0.The content of adjusting chance byte S is by adjusting control information C decision, when adjusting bit C and be 1, adjust chance byte S and all be invalid, fix fill in byte; When adjustment bit C was 0, adjusting chance byte S was effective business information content.By adjusting control information C and adjusting chance byte S, can control the available capacity size of container neatly, adapt to little deviation and swing between SDH container speed and the ODU service rate.
Fig. 5 shows the device structure schematic diagram according to the embodiment of the invention.
In application, transmission equipment provides various interface usually, realizes the transmission of other business.In SDH equipment, the business of handling is the SDH frame, when equipment need transmit other business, equipment provides various interface veneer (or unit), at the input interface place business information is mapped to the SDH frame, just be packaged into the SDH frame structure, realize processing capacities such as intersection by SDH equipment, send to output interface then.Fig. 5 is a SDH device structure schematic diagram, is the equipment of treatment S DH business, and the device core processing unit is a cross unit, finishes Path selection and the control of the next SDH frame signal of each input unit to output unit.In order to realize the transmission of other business, equipment provides variety of interface units, as OTN (ODU) service board.At input interface unit the ODU business is mapped in the SDH frame, sends to the output interface unit after the SDH device processes, output unit recovers business information, and sends.When ODU is professional when transmitting in just by a SDH equipment, an input interface unit input in the professional slave unit of ODU through intersecting the back from the output of another one output unit, and recovers business.Incoming traffic unit and outgoing traffic unit are the Service Processing Units in the same equipment.When the ODU service needed transmits by the SDH network, the ODU business is mapped to the SDH business at an equipment input unit of network boundary, by sending in the network after the equipment cross processing, business information transmits in the SDH network with the form of SDH frame, handle by destination device at last, send to output unit, recover business datum by output unit.In the professional mode that transmits by the SDH network of ODU, the input unit of handling the ODU business and output unit are respectively in different equipment.
Fig. 6 shows the mapping mode according to a kind of reference of the embodiment of the invention.Fig. 7 shows the input unit structure chart according to the embodiment of the invention.Fig. 8 shows the output unit structure chart according to the embodiment of the invention.
As shown in Figure 6, it comprises: the input fifo module, under business clock control, the incoming traffic data flow cache in FIFO, is realized the incoming traffic caching function; Adjusting module according to the full state of sky of input FIFO, produces and effectively adjusts index signal, and whether decision produces is once adjusted, and mutiread goes out the data of a byte from FIFO; Package module is read business datum from input FIFO, be encapsulated in the SDH frame, and according to adjusting indication, the business datum of a byte of mutiread is encapsulated into and adjusts the chance byte location during with adjustment, generates and adjusts control byte, finishes the frame structure encapsulation.
As shown in Figure 7, comprising: the output fifo module under system clock, is cached to effective business datum byte in the frame structure among the output FIFO; Adjust analysis module, the adjustment control byte in the analysis frame structure produces and effectively adjusts index signal, simultaneously, is effectively adjusting under the index signal, and the effective traffic data byte of adjusting the chance byte is cached among the output FIFO; Counter module under system's frame head signal controlling, is counted the number of effectively adjusting in the frame, and is provided effective adjustment number at postamble; Accumulator module, under the control of pulse uniformly, the adjustment number that constantly adds up, when accumulated value surpassed the mould value, adding up of a system clock cycle of output overflowed the increase index signal; Frequency divider A and frequency divider B module, frequency divider A directly carries out frequency division to recovered clock.Frequency divider B carries out frequency division to system clock, need count the increase signal when frequency division; Phase discriminator is differentiated the phase difference size between the index signal behind two frequency divisions, provides phase difference signal; Low pass filter carries out low-pass filtering to phase difference signal, and the filtering high fdrequency component obtains the control signal of DC component; Voltage controlled oscillator, control signal are directly controlled voltage controlled oscillator, produce uniform clock signal, and this clock signal is exactly the business recovery clock, and clock frequency is determined by control signal.
Be described in detail in conjunction with Fig. 6, Fig. 7 and Fig. 8.
In invention, the method that the ODU business is mapped to the SDH container has no requirement, and can adopt the method for standard, also can adopt other mapping methods, as the mapping mode of Fig. 6.In some equipment, in order to realize that SDH business and ODU have unified capacity processing, N:M mode at cross unit, also an ODU1 business can be mapped in 20 SDH frame cascaded series and go, article one, the ODU2 business is mapped in 80 SDH frame cascaded series and goes, and an ODU3 business is mapped in 320 SDH frame cascaded series goes.No matter how the ODU business is mapped in the container of SDH, and is mapped to the cascaded series what SDH form, and in a SDH frame period 125us, an ODU1 business has 39043 bytes.In mapping scheme, it is consistent with adjustment chance byte quantity to adjust control information, and each is adjusted control information and determines to adjust a chance byte accordingly.Consider that adjusting is the twocouese adjustment, i.e. positive justification and negative justification.Positive justification is the adjustment of business clock speed less than equipment clock speed, and negative justification is the adjustment of business clock speed greater than equipment clock speed.Adjusting control and debug machine when realizing the twocouese adjustment can byte quantity will double.When the adjustment chance byte of 18 bytes, folk prescription relates to 9 and adjusts the chance byte when adjusting, therefore the SDH cascaded series has 39043-9=39034 information byte at least, and the actual minimum capacity of container is 39034 information bytes, and heap(ed) capacity is a 39034+18=39052 information byte.When single direction had 9 adjustment information bytes, clocking error was 9/39043*10^6=230.52ppm, and the deviation of maximum 230.52 ppm is satisfied between SDH network clocking and the ODU network clocking in mapping, promptly-230.52ppm～+ frequency deviation between the 230.52ppm.When needs satisfy between bigger SDH network clocking and the ODU network clocking frequency deviation, need more to adjust control and adjust the chance byte.
When the OTN business sends to SDH equipment, at first the OTN business is received processing, obtain the ODU frame data, there is ODU frame data clock that business datum is cached among the input FIFO.Input FIFO provides fast sky and speed index signal to adjusting module, and adjusting module produces and adjusts index signal valid_c according to the state information of FIFO, is used for adjusting the speed that reads business datum from FIFO.When signal valid_c is effective, gets a data byte in adjustment chance byte location mutiread, otherwise do not read a data byte.Package module is used to generate the SDH frame structure, and business datum is mapped to the container data byte location.When adjusting, generate effective control information in adjustment control information position, deposit business datum at adjustment chance byte location simultaneously.When not adjusting, the adjustment control information is an invalid content, adjusts the chance byte location for filling in content.Mapping mode can adopt the SDH cascaded series (capacity is greater than the professional byte of ODU) of variety of way and all size.When realizing mapping, adjusting module, package module all adopt the system clock of equipment, and this clock is the system clock of equipment and the system clock that professional output unit adopts homology.When input unit and output unit were on same equipment, the system clock of two unit was same system clocks; When input unit with output unit on different equipment the time, the system clock of two equipment all extracts the same clock source on the network.The SDH network is a synchronizing network, and online all devices all extracts a clock source, and whole network equipment is in synchronous regime, and the system clock that has guaranteed online any two equipment all is a homology.
Package module is finished the mapping of business datum and the encapsulation of SDH frame structure, sends to the device processes unit then, as cross unit.Send to the destination after the processing unit processes.The destination may be on this equipment, an other equipment that also may be on network.In the destination, untie the SDH frame of encapsulation, take out the business datum byte, under system clock, the business datum byte is cached among the input FIFO.In buffer memory business datum byte, will adjust control information and send to the adjustment analysis module, whether effective, provide effective adjustment control index signal valid_c pulse if analyzing the adjustment control information.Under the control of adjusting control index signal valid_c, the adjustment chance byte of correspondence also is cached among the output FIFO.When the adjustment control signal was effective, what adjustment chance byte location was deposited was effective business datum byte, needed get up with other business datum bytes buffer memory together.
Counter is counted adjusting control index signal valid_c under the control of professional frame head, counts the number of effectively adjusting in the frame time, and provides count results num at postamble.Each frame update of count results once constantly provides and effectively adjusts number of times in each frame time.
Fig. 9 shows the working timing figure according to the accumulator of the embodiment of the invention.
Accumulator adds up to adjusting frequency n um under the control of uniform pulse.Uniform pulse is produced by system clock, and pulse duration is a system clock cycle, and the time interval between the adjacent pulse is fixed, and is the uniform train of impulses.In the mapping mode definition, if adjustment control number maximum in the frame is n, then umber of pulse is n in the time interval of a frame, just in the time interval of a frame, adjustment control information maximum in the number of pulses of uniform pulse and the mapping mode equates, also equals to adjust the chance byte.For the mapping mode of Fig. 6, always have 18 in the frame and adjust control information and adjust the chance byte, then uniform pulse has 18 uniform pulse numbers in the time of a frame.Accumulator is an accumulator that mould is n, and n is total number of framing control control, also equals the overall pulse number of pulse signal in the frame time.Under the control of pulse signal, constantly exchange Integer n um and add up, when accumulation result greater than, when equaling mould value n, accumulator overflows and produces the carry signal add of a pulse, accumulation result deducts n simultaneously, remainder is deposited in the accumulator, in order to adding up next time.If the result of one-accumulate does not reach n, then directly preserve accumulation results, in this case output carry signal pulse add not.When mapping, because frame structure, payload area can only be arranged in the position of adjustment control information in a frame of design, and evenly spreads out as far as possible, but in the entire frame structure, all the time can not be even fully.Owing to reasons such as clock jitters, adjusting control information effectively also may not be even when shining upon simultaneously, and effective adjustment information also may not be even during recovery.In the present invention, by counter and the accumulator under uniform pulse control, change uneven effective adjustment information into approximate effective uniformly adjustment the, i.e. carry signal add.Fig. 9 is that a mould is the working timing figure of 8 accumulator, produces uniform pulse pulse by system clock sys_clock, and the count results num to the upstream under pulse signal constantly adds up, and each accumulation result is placed among the counter.When accumulation result reaches 8 and when overflowing, the carry signal add of a pulse of input is placed on remainder among the counter.The num value is 3 in the time of a frame, represents to have in the frame three effectively to adjust, and through adding up of accumulator 8 times, common property is given birth to and overflowed for 3 times, export 3 and is similar to uniform carry pulses.Under normal operation, the speed size that writes the speed of data and recovered clock reading of data from fifo to output among the fifo is consistent, and fast empty and state completely soon can not appear in fifo.When starting working or the system clock of input unit and output unit homology not, exist under the situation of frequency difference, output FIFO can occur writing full or read the sky phenomenon, therefore will export the fast sky of FIFO and soon completely index signal also give accumulator.When fast sky appearred in output FIFO, accumulator can regular minimizing should be worked as the spill over add of output, reduces the frequency of recovered clock, has so just reduced from the speed of FIFO reading of data, avoids FIFO the sky phenomenon to occur reading.When fast expiring appearred in output FIFO, accumulator can regularly increase spill over add, increases the frequency of recovered clock, has so just strengthened from the speed of FIFO reading of data, avoids FIFO full phenomenon to occur writing.
Figure 10 shows the frequency divider A work schematic diagram according to the embodiment of the invention.Figure 11 shows the frequency divider B work schematic diagram according to the embodiment of the invention.
Be described in detail in conjunction with Figure 10 and Figure 11.
Clock frequency division module A carries out frequency division to recovered clock, produces the frequency-dividing clock of a low speed.Figure 10 has provided the course of work schematic diagram that recovered clock is carried out 10 frequency divisions, and under the recovered clock effect, counter constantly adds 1, and when when 0 count down to 4, the sub-frequency clock signal level reverses once, so just export the clock signal of one 10 frequency division.Clock frequency division module B carries out frequency division to system clock, and A is different with clock frequency division module, and clock frequency division module B needs to consider carry signal add when carrying out frequency division.When the add signal was effective, fractional frequency signal will be carried previous system clock cycle.Figure 11 has provided the course of work schematic diagram that system clock is carried out 12 frequency divisions.Under the system clock effect, counter constantly adds 1 counting.When add was effective, counter then added 2 computings, otherwise counter carries out add-one operation.When counter when 0 is added to 5, the counter-rotating of clock signal level.If counter is added to 4, and add is also effectively the time, and the clock signal level also carries out reverse turn operation.The ratio of frequency division multiple equals the ratio of business clock and system clock frequency between clock frequency division module A and the clock frequency division module B.For example ODU1 traffic criteria speed is 239/238*2.488320Gbits/s, when if system clock is 2.488320G bits/s, then the ratio of the frequency division multiple of the frequency division multiple of frequency divider A and frequency divider B is (239/238*2.488320): (2.488320)=239: 238.
Two clock signals behind the frequency division send to phase discriminator, and phase demodulation goes out the phase place difference of two clock signals, give low pass filter then and carry out filtering, filter out the control signal of DC component, and the control voltage-controlled oscillator (VCO) produces recovered clock.
Recovered clock reads the business datum byte from output FIFO, this traffic spike is exactly the Business Stream signal of input, has quality height, the low characteristics of shake.
In output unit, system clock of system clock of analysis module, counting module, accumulation module and frequency division module clock B, the system clock of this system clock and input unit is the same system clock, or two system clocks of homology.
The present invention provides the method that transmits the OTN business by the SDH network, equally also is suitable for the method that transmits the SDH business by the OTN network.
In sum, by the present invention, can realize that the SDH equipment that passes through of ODU business transmits, can satisfy various mapping modes, implementation method is simple, can recover high-quality business clock signal.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. a professional implementation method that transmits in optical transport network is characterized in that, may further comprise the steps:
For professional input unit and professional output unit are provided with same system clock or homologous system clock;
Described professional input unit will be adjusted from the business datum storage of outside and to it according to system clock, adjusted business datum is packaged into the SDH frame signal with coming from outside header signal, described system clock and the adjustment indication information that is generated, and described SDH frame signal is sent to the core cross unit;
Described professional output unit receives described SDH frame signal from described core cross unit, generates according to the described adjustment indication information in the described SDH frame signal and adjusts index signal, and generate the business recovery clock according to described header signal and described system clock; And
Described professional output unit is exported the described adjusted business datum in the described SDH frame signal according to described adjustment index signal, described system clock and described business recovery clock.
2. the professional implementation method that transmits according to claim 1 is characterized in that, described professional input unit will be realized by described business datum being cached to the input fifo buffer from the business datum storage of outside according to system clock.
3. the professional implementation method that transmits according to claim 2 is characterized in that, also comprises:
Adjusting module produces described adjustment indication information according to the capacity of described input fifo buffer;
From described input fifo buffer, read described business datum according to described system clock, and determine whether that mutiread goes out or read the business datum of an adjustment less according to described adjustment indication information; And
Described adjusted business datum is sent to package module from described input fifo buffer.
4. the professional implementation method that transmits according to claim 3, it is characterized in that it is to encapsulate by the described package module in the described professional input unit to realize that described professional input unit is packaged into the SDH frame signal with adjusted business datum with the adjustment indication information that comes from outside header signal, described system clock and generated.
5. the professional implementation method that transmits according to claim 1 is characterized in that, also comprises:
, after described core cross unit receives described SDH frame signal, described adjusted business datum in the described SDH frame signal and adjustment indication information are cached in the output fifo buffer at described professional output unit.
6. the professional implementation method that transmits according to claim 1, it is characterized in that it is to generate described adjustment index signal by the adjustment analytic unit in the described professional output unit to realize that described professional output unit generates the adjustment index signal according to the described adjustment indication information in the described SDH frame signal.
7. the professional implementation method that transmits according to claim 1, it is characterized in that described professional output unit is to generate described business recovery clock by the clock generating unit in the described professional output unit to realize according to described header signal and described system clock generation business recovery clock.
8. the professional implementation method that transmits according to claim 7 is characterized in that the clock generating unit in the described professional output unit generates described business recovery clock and comprises:
Counter is according to described header signal and described system clock, the umber of pulse of the described adjustment index signal in the frame time that adds up, and output count value;
Accumulator adds up described count value under evenly spaced impulsive condition, and the carry index signal pulse output that will add up and overflow; And
Phase-locked loop utilizes the pulse of described carry index signal to generate described business recovery clock.
9. the professional implementation method that transmits according to claim 8 is characterized in that, described phase-locked loop utilizes the pulse of described carry index signal to generate described business recovery clock to comprise:
First frequency divider according to described carry index signal pulse described system clock is carried out frequency division, and second frequency divider carries out frequency division to described business recovery clock;
Phase discriminator carries out phase demodulation with the fractional frequency signal of described first frequency divider and the output of described second frequency divider, and identified result is sent to low pass filter;
Described low pass filter filters described identified result, to generate voltage-controlled signal; And
Voltage controlled oscillator produces described business recovery clock according to described voltage-controlled signal.
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| CN2008100008281A CN101252403B (en) | 2008-01-22 | 2008-01-22 | Realizing method of traffic transmission in light transmitted network |
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| CN2008100008281A CN101252403B (en) | 2008-01-22 | 2008-01-22 | Realizing method of traffic transmission in light transmitted network |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102201810A (en) * | 2010-03-23 | 2011-09-28 | 奇景光电股份有限公司 | Device and method for controlling clock recovery |
| CN102833063B (en) * | 2012-08-24 | 2015-08-19 | 烽火通信科技股份有限公司 | The implementation method of client traffic Clock Extraction in a kind of OTN network |
| CN103684727B (en) * | 2012-08-31 | 2018-03-23 | 中兴通讯股份有限公司 | A kind of method for synchronizing time and device of optical transfer network asynchronous network |
| CN107566925B (en) * | 2016-06-30 | 2021-12-31 | 中兴通讯股份有限公司 | Data transmission method and device |
| CN110445568B (en) | 2016-12-23 | 2021-04-20 | 华为技术有限公司 | Clock transmission method and related equipment |
| CN110808808A (en) * | 2019-11-13 | 2020-02-18 | 天津光电通信技术有限公司 | Method for extracting signal clock from OTN |
| CN114598620B (en) * | 2022-02-17 | 2024-01-30 | 杭州晨晓科技股份有限公司 | Operation circuit |
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| CN1791278A (en) * | 2004-12-14 | 2006-06-21 | 华为技术有限公司 | Synchronous optical network and optical transmission network uniform dispatching system and its method |
| CN1921461A (en) * | 2005-08-26 | 2007-02-28 | 北京格林威尔科技发展有限公司 | Transmission method of circuit business in passive optical network based on Ethernet |
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