CN100459598C - Transmission method of circuit business in passive optical network based on Ethernet - Google Patents
Transmission method of circuit business in passive optical network based on Ethernet Download PDFInfo
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Abstract
The invention relates to a method for transmission service on inactive optical network based on Ethernet. Wherein, it comprises that separating line clock and circuit service data from each circuit service signal at E1/T1 format; driven by line clock, writing circuit service data into buffer circuit; driven by local clock, reading circuit service data from buffer circuit, and packing the circuit service data and relative source address and target address into MAC frame; multiplexing the MAC frames into one path to be sent to opposite terminal; the opposite terminal receives MAC frame, to decomplex that extracting circuit service data from each path to be written into buffer circuit; based on the state of buffer circuit, using local clock to return the return clock same as the sending clock; driven by return clock, reading the circuit service data of buffer circuit to process. The invention can meet the telecommunication service quality of time delay and time delay vibration.
Description
Technical field
The present invention relates to communication technical field, be specifically related to Circuit Service effective method of transmission in based on the EPON (EPON, Ethernet Passive Optical Network) of Ethernet.
Background technology
Circuit Service comprises business such as primary group, quadratic gropup, tertiary group, for example E1/T1 of primary group etc.Circuit-switched service is to propagation delay time and delay variation sensitivity, and the existing packet switching network can not satisfy the requirement of traditional circuit business to time delay and shake.How Circuit Service effectively transmits in Packet Based Network, and especially the effective transmission in the EPON system is a urgent problem.
Because the EPON system bearing is Ethernet service, so realize that in the EPON system it is in existing EPON technical standard that the Circuit Service transmission has very big difficulty, actual conditions, does not all relate to the problem that Circuit Service inserts.
In the packet switching network, provide aspect the Circuit Service, studying at present more in the world is to realize the Circuit Service transmission at three layers on ISO model (IP layer), there has been corresponding product to occur in this respect abroad, but this mode realizes complexity, packaging efficiency is not high yet, and fatal weakness is the service quality (QoS, Quality of Service) that present stage can not guarantee Circuit Service fully.
Circuit Services such as EPON carrying E1/T1 can adopt the scheme that Circuit Service is mapped directly to physical layer transmission, but so, be pure ethernet frame no longer just on the physical layer, can't be compatible with traditional ethernet environment, this will certainly influence the range of application of EPON.
Once proposed " method that a kind of Circuit Service transmits " in the applicant's one piece of application for a patent for invention formerly on the EPON based on Ethernet, the main thought of this method is that the data with Circuit Service map directly in the ethernet frame that transmits in EPON; After this ethernet frame is delivered to the opposite end, therefrom recover original data flow and clock again, realize the transparent transmission of Circuit Service in EPON with this.
But this method is owing to the Circuit Service frame sends so that 500us is regularly unified, Bandwidth Dynamic Allocation algorithm to EPON has proposed higher requirement, in order to guarantee that the constant flow of Circuit Service data will consume certain bandwidth more, not good to the burst service discharge characteristic support of Ethernet.In addition, the clock synchronization scheme of system is comparatively simple in this method, but precision also needs further raising.
Summary of the invention
In view of this, the method that the object of the present invention is to provide a kind of Circuit Service on EPON, to transmit based on Ethernet, realize the transmission problem of circuit-switched service in the EPON system, satisfy the time delay and the delay variation requirement of Circuit Service, and solve the synchronization timing problem.
The invention provides the method that a kind of Circuit Service transmits based on above-mentioned purpose on the EPON based on Ethernet, on the Ethernet passive optical network that is applied to form by OLT, ODN and a plurality of ONU, this method comprises the signal transmission to the down direction of ONU by OLT, and is transmitted to the signal of the up direction of OLT by ONU;
This method comprises at down direction:
A1) the Circuit Service Signal Separation to every road E1/T1 form of entering OLT goes out line clock and Circuit Service data, under the driving of described line clock the Circuit Service data is write buffer circuit and carries out buffer memory;
A2) under the driving of OLT local clock, from buffer circuit, read the Circuit Service data according to the bandwidth that obtains, the Circuit Service data are encapsulated in the mac frame together with corresponding source address and destination address, each road mac frame are multiplexed into lead up to ODN and send to ONU;
A3) after ONU received mac frame, decomposition-reduction was a multichannel, every road is extracted the Circuit Service data respectively write in the buffer circuit;
A4) according to the state of buffer circuit, in the moment of receiving the Circuit Service frame, after the largest buffered data volume is shone upon through exponential function with the difference of the theoretical center value of presetting, as numerical control oscillator frequency deviation controlled quentity controlled variable, local clock is reverted to the recovered clock consistent with clock originator, under the driving of this recovered clock, the Circuit Service data that read in the buffer circuit are handled;
Comprise at up direction:
B1) the Circuit Service Signal Separation to the E1/T1 form that enters ONU goes out line clock and Circuit Service data, and the Circuit Service data are written into buffer circuit and carry out buffer memory under the driving of described line clock;
B2) ONU is at every turn when obtaining Frame transmission bandwidth, determine to send the frame length of mac frame according to the Circuit Service data volume of buffer memory in the buffer circuit, and the Circuit Service data of storing in the buffer circuit are encapsulated in the mac frame together with corresponding source address and destination address, each road mac frame is multiplexed into leads up to ODN and send to OLT;
B3) after OLT received mac frame, decomposition-reduction was a multichannel, every road is therefrom extracted the Circuit Service data respectively write in the buffer circuit;
B4) according to the state of buffer circuit, in the moment of receiving the Circuit Service frame, after the largest buffered data volume is shone upon through exponential function with the difference of the theoretical center value of presetting, as numerical control oscillator frequency deviation controlled quentity controlled variable, local clock is reverted to the recovered clock consistent with clock originator, under the driving of this recovered clock, the Circuit Service data that read in the buffer circuit are handled.
Source address described in this method step A2, the B2 and destination address are after the link of system configuration Circuit Service, source address, destination address and their mapping relations of this link be kept at respectively among OLT and the ONU,
OLT or ONU according to the link that current transtation mission circuit business datum is adopted, find the source address and the destination address of this link in this locality when the encapsulation mac frame.
Reading the Circuit Service data described in this method step A2 from buffer circuit is earlier the Circuit Service metadata cache to be read the Circuit Service data after the time in an encapsulation cycle.
Encapsulation described in this method step A2 and the B2 is that the Circuit Service data are carried out the encapsulation of quasi periodicity ground.
The described encapsulation process of this method is the ethernet frame structure of employing standard, when the Circuit Service data encapsulation is gone into the load bearing unit of Ethernet, has added the data cell of redetermination, is used for frame losing protection, the frame head checking treatment of Circuit Service frame.
Local clock recovery process is the state according to buffer circuit described in this method step A4 and the B4, utilizes digital phase-locked loop to recover the recovered clock consistent with clock originator with local clock.
Largest buffered data volume described in this method step A4 and the B4 is the inherent variability of source end clock and phase-locked loop centre frequency with the difference of the theoretical center value of presetting.
Local clock recovery process described in this method step A4 and the B4 is further carried out loop filtering to the inherent variability that obtains behind the inherent variability of determining source end clock and phase-locked loop centre frequency.
Described numerical control concussion process comprised when local clock described in this method step A4 and the B4 recovered: based on the fractional frequency division technology of multimode frequency division formation, frequency division hockets between predefined higher limit N and N+1 or N and N-1, can obtain a frequency dividing ratio between N and N+1 or N and N-1, obtain needed frequency with this.
Described numerical control concussion process further comprised when local clock described in this method step A4 and the B4 recovered: each input frequency difference is all corresponding cycle that frequency dividing ratio changes, frequency dividing ratio of each cyclomorphosis.
ONU described in this method step B2 when obtaining Frame transmission bandwidth, farthest obtains the Circuit Service data of storing in the buffer circuit at every turn.
In the described encapsulation process of this method step A2 and B2 further the mac frame of Circuit Service data be set to the highest transmission priority.
From above as can be seen, Circuit Service provided by the invention has been taken all factors into consideration following two kinds of situations in method the present invention of transmitting on the EPON based on Ethernet: the purpose of EPON bearer service is to realize the transparent transmission of Circuit Service between far-end ONU and the local side OLT; Then compatible bad in physical layer place in circuit business, and can not guarantee the QoS of Circuit Service in IP layer place in circuit business, propose two layers of transmission circuit business.
Method two layers of transmission circuit business of the present invention, promptly the Circuit Service data encapsulation is become the ethernet frame (circuit data mac frame) of standard at transmitting terminal, the unified transmission of other ethernet frames with bearing data service, up direction relies on the dynamic bandwidth allocation algorithm of differentiated service priority, down direction relies on the priority query of differentiated service, thereby ensures that preferential transmission of Circuit Service guarantees its QoS quality; At receiving terminal, the circuit data mac frame is carried out decapsulation handle, recover circuit data.The inventive method adopts based on the adaptive method of digital phase-locked loop and realizes the synchronous of Circuit Service.In the receiving end of one way link, by monitoring the state that receives buffer circuit, obtain the phase demodulation output of source end and local clock, through the smoothing processing of loop filtering circuit, control digital controlled oscillator output clock recovered.
The method that the present invention adopts can be guaranteed the service quality of Circuit Service, and the technical performance index of Circuit Service interface can satisfy domestic and international related specifications requirement.Method of the present invention can be applicable in the system of EPON system and other Ethernet datas business and Circuit Service comprehensive transmission, and, in any network based on Ethernet of method for synchronous of the present invention can be provided, also can both use technical scheme of the present invention.
Description of drawings
Fig. 1 is the system block diagram of TDM Over EPON;
Fig. 2 is the structured flowchart of E1/T1 Circuit Emulation Unit of the present invention;
Fig. 3 is the structured flowchart of adaptive clock recovery module of the present invention;
The schematic flow sheet that Fig. 4 transmits on based on EPON for downstream circuitry business of the present invention;
The schematic flow sheet that Fig. 5 transmits on based on EPON for upstream circuitry business of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, technical solution of the present invention is elaborated.
It is to be finished jointly by the service access port of user side and the service port of local side that Circuit Service inserts, there is a kind of corresponding relation in these two ports, the corresponding different Circuit Service of different corresponding relations connects, and like this, local side just can dispose easily and connect.For a Circuit Service,, can distribute ethernet source address and destination address respectively according to the relation of professional two end points.
At transmitting terminal, the Circuit Service data that enter among the EPON are write buffer circuit, by paracycle circuit data is carried out ethernet medium MAC layer (MAC, Media Access Control) encapsulation, after encapsulation, the Circuit Service data are fitted in the data field of ethernet mac frame.After comprising the processing of ethernet mac frame through the PON module of Circuit Service data, arrive transmit port, send to receiving terminal through transmission line.
At receiving terminal, comprise of the processing of the ethernet mac frame of Circuit Service data by the PON module, be forwarded to destination interface, carrying out decapsulation then handles, the Circuit Service data extract that is encapsulated in the ethernet mac frame is come out, write the caching process circuit, the shake that data transfer procedure is introduced is carried out smoothly; Last according to the Circuit Service clock synchronous with transmitting terminal, and corresponding Circuit Service codes and standards is exported data continuously.Thereby realize the transparent transmission of Circuit Service in EPON.
The method that Circuit Service of the present invention transmits on based on EPON is to transmit the Circuit Service data on the Ethernet passive optical network of being made up of optical line terminal, optical distribution network and a plurality of optical network unit, comprise by the signal of optical line terminal and transmitting, and transmit by the signal of optical network unit to the up direction of optical line terminal to the down direction of optical network unit.
Referring to shown in Figure 1, be the system block diagram of TDM Over EPON.The OLT side mainly comprises: E1/T1 Interface circuit 101, E1/T1 simulation unit 102, E1/T1 simulation unit Multiplexing module 103 and PON interface core control circuit 104; The ONU side mainly comprises: E1/T1 Interface circuit 101, E1/T1 simulation unit 102, E1/T1 simulation unit Multiplexing module 106 and PON interface core control circuit 105.
Wherein, for E1/T1 Interface circuit 101, E1/T1 simulation unit 102, identical in OLT side and ONU side.For E1/T1 simulation unit Multiplexing module 103 and 106, in the module 103 of OLT side, comprised the timing control circuit of down direction transtation mission circuit traffic frame; And in the module 106 of ONU side, not having corresponding circuit, similar functions is finished by the Dynamic Bandwidth Allocation module that is included in the PON interface core control circuit 105.For PON interface core control circuit 104 and 105, the integrated OLT part of Multi-point Control Protocol module in the module 104 of OLT side, the OLT part of Dynamic Bandwidth Allocation module, a submodule such as multiport bridge; The integrated ONU part of Multi-point Control Protocol module in the module 105 of ONU side, the ONU of Dynamic Bandwidth Allocation module partly waits submodule.The PON interface core control circuit 104 of OLT side and the connection between the E1/T1 simulation unit Multiplexing module 103 have been passed through a multiport bridge and have been realized, and are direct-connected between the PON interface core control circuit 105 of ONU side and the E1/T1 simulation unit Multiplexing module 106.
Referring to shown in Figure 4, below introduce in detail and the present invention is based on this system Circuit Service E1 or T1 Signal Processing process.
Down direction:
Step 11. enters the processing of the Circuit Service E1/T1 signal of OLT through E1/T1 Interface circuit 101, convert the ambipolar High Density Bipolar 3 of single channel (HDB3) line code to HDB3 code signal that the two-way unipolarity is represented, export E1/T1 simulation unit 102 to.
Step 12.E1/T1 simulation unit 102 is dressed up mac frame with the Circuit Service data set that receives and is sent to E1/T1 simulation unit Multiplexing module 103.
The structure of E1/T1 simulation unit 102 comprises referring to shown in Figure 2: HDB3-＞NRZ module 201, send buffer circuit 202, framing processing module 203, separate frame processing module 204, receive buffer circuit 205, NRZ-＞HDB3 module 206, adaptive clock recovery module 207, configuration management interface 208 and alarm identification module and warning processing module.
Wherein, HDB3-＞NRZ module 201 is used for the HDB3 encoded signals that the two-wire that the circuit interface conversion generates is represented is handled, and extracts line clock and data-signal; Then, under the control of this line clock, the data flow of Circuit Service will be written to by serial and send buffer circuit 202.
Sending buffer circuit 202 is used for the data flow of serial input is carried out buffer memory; The clock of its reading of data is provided by framing processing module 203, and the data mode that reads is 8 parallel bit bytes; Transmission buffer circuit 202 for the ONU side also provides the information of buffer status to the corresponding dynamic bandwidth allocation module.
Separating frame processing module 204 is used for carrying out the decapsulation processing from the Circuit Service frame that PON interface core control circuit 104/105 receives.At first whether the frame that identification is received according to target MAC (Media Access Control) address is the frame of this link, and the unmatched frame of condition is abandoned; Then information such as qualified frame extraction data field byte sequence number are carried out the frame losing protection and handle, the active data load is deposited in receive buffer circuit 205.
Receive buffer circuit 205 and be used for the Circuit Service data of receiving are carried out buffer memory, the information of buffer status outwards is provided simultaneously.Receive the recovered clock signal that clock uses adaptive clock recovery module 207 to generate of reading of buffer circuit 205, the serial data of reading is passed to NRZ-＞HDB3 module 206.
NRZ-＞HDB3 module 206 is used for the serial data stream of receiving is encoded, the HDB3 that the sign indicating number type is represented for the two-way unipolarity; Pass to the conversion that E1/T1 Interface circuit 101 is finished level through coded data.
Adaptive clock recovery module 207 is key components of clock recovery, the present invention is based on the basic principle of digital phase-locked loop, time delay jittering characteristic when professional in conjunction with transfer circuit among the EPON, in adaptive clock recovery module 207, designed to innovation the loop filter that satisfies the Circuit Service performance requirement, make adaptive clock recovery module 207 clock recovered satisfy the requirement of Circuit Service QoS index, the concrete structure of this module 207 and function will be described in more detail below.
In addition,, also be provided with alarm identification module and warning processing module in the Circuit Emulation Unit, be respectively applied for the fault in the circuit is discerned and carried out alarming processing according to the customary means of prior art.
Described step B specifically comprises:
A. two-way HDB3 code signal at first enters HDB3-＞NRZ module 201, extracts a route road clock signal and one road NRZ (NRZ) encoded data signals.
B. under the driving of resulting line clock, described data-signal is written into the form of serial data stream and sends buffer circuit 202 and carry out buffer memory, waits for that framing sends.
C. framing processing module 203 begins to assemble the mac frame that contains the Circuit Service data in the moment of authorized signal.The source and destination MAC Address of this mac frame offers framing processing module 203 according to pre-configured source and destination mac address information by configuration management interface 208 by network management system; Fill in the data field of mac frame from sending the Circuit Service data that buffer circuit 202 is read; After finishing, the mac frame assembling sends to E1/T1 simulation unit Multiplexing module 103 immediately.
Wherein, the mandate of assembling beginning is constantly for OLT, being to be controlled by OLT side E1/T1 simulation unit Multiplexing module 103, is earlier Circuit Service data one of buffer memory in sending buffer circuit 202 to be encapsulated cycle time in principle, then the Circuit Service data is carried out the encapsulation of quasi periodicity ground.Specifically comprise: according to sending the buffer status information that buffer circuit 202 provides, E1/T1 simulation unit Multiplexing module 103 is judging that local clock arrives all after dates of predefined transmission, all E1/T1 in this OLT send the authorization signal of initial transmission respectively, until arriving framing processing module 203.
The ethernet frame structure of standard has been used in the encapsulation that mac frame adopted; when the Circuit Service data encapsulation is gone into the data field of mac frame; handle for the ease of situation frame losing; can further add the data field of privately owned definition in the back, length/type territory of mac frame; comprise fields such as data field byte sequence number, Header-Error-Check in this zone, be used for the processing such as frame losing protection, frame head verification of Circuit Service frame.
The frame length of each Circuit Service Frame that sends is variable, the transmission cycle of ifs circuit business data frame becomes big, the frame length that sends is also elongated thereupon, and each transtation mission circuit business data frame will all send sending the data of storing in the buffer circuit as far as possible.
The source address of described pre-configured mac frame and destination address are operating personnel during for the link of system configuration E1 Circuit Service, the mapping relations of the source and destination address that will be linked by network management system are kept at respectively in the local storage of OLT side and ONU side, and can set up, delete, inquire about the mapping relations of the source and destination address of preserving and operation such as modification by network management system where necessary.When carrying out the mac frame encapsulation, framing processing module 203 directly extracts corresponding data and uses from the register of this locality.
For the allocated bandwidth mechanism of down direction,, can introduce the mechanism of rate limit in order to limit the bandwidth that a certain CU is crossed; Business (as E1) quality in order to guarantee high priority is provided with the priority query at different business simultaneously, thereby the business that guarantees high priority obtains enough bandwidth and time delay assurance.Preferably, no matter the distribution that whether has Dynamic Bandwidth Allocation mechanism to participate in bandwidth further is set, the ethernet mac frame that has encapsulated the Circuit Service data all has the highest transmission priority.The delivery time of E1 module down direction Frame has the clock control of OLT this locality, periodically sends the E1 Frame.So mainly on the queuing buffer memory, the propagation delay time that the E1 Frame has been controlled in the strictness of EPON system changes in the introducing of the delay variation of descending E1 Frame, thereby has reduced the level and smooth difficulty of output clock jitter.
Step 13.E1/T1 simulation unit Multiplexing module 103 will be multiplexed into one tunnel output from the multichannel mac frame that each E1/T1 Circuit Emulation Unit 102 receives.
And E1/T1 simulation unit Multiplexing module 103 also produces the transmission authorization signal and sends to each E1/T1 Circuit Emulation Unit 102 respectively.
Step 14.PON interface core control circuit 104 is finished the transmission of descending mac frame to ONU by optical distribution network (ODN).
Step 15. is in the ONU side, and PON interface core control circuit 105 receives mac frame by ODN, and wherein the Frame that contains Circuit Service is sent to E1/T1 simulation unit Multiplexing module 106.
Step 16.E1/T1 simulation unit Multiplexing module 106 is assigned to corresponding E1/T1 Circuit Emulation Unit 102 respectively after multiplexing mac frame is together decomposed.
E1/T1 Circuit Emulation Unit 102 among the step 17.ONU extracts business datum from the mac frame of receiving, under the driving of recovered clock, send to E1/T1 Interface circuit 101 after business datum encoded.
This step specifically comprises:
A) separate after frame processing module 204 receives the mac frame that contains the Circuit Service data, therefrom extract the Circuit Service data, and be written to and receive buffer circuit 205 and carry out buffer memory.
B) receive buffer circuit 205 and in real time information such as store status are passed to adaptive clock recovery module 207.
C) adaptive clock recovery module 207 is based on the digital phase-locked loop principle, the state output that receives buffer circuit 205 is converted into the phase demodulation output of far-end clock and local recovery clock, obtain and the local recovery clock of far-end clock, and guarantee that the output jitter characteristic of recovered clock reaches requirement with frequency.
D) under the driving of the recovered clock that adaptive clock recovery module 207 is exported, the data that receive in the buffer circuit 205 are read out, and send to NRZ-＞HDB3 module 206 and encode, and export E1/T1 Interface circuit 101 to through coded data.
After the HDB3 code signal of after step 18.E1/T1 interface circuit 101 is handled the two-way unipolarity being represented converts the ambipolar HDB3 line code of single channel to, export the EPON external equipment to.
Below the principle that adopts the adaptive clock recovery method to recover source end clock in the described step b) is elaborated.
The structure of adaptive clock recovery module 207 comprises referring to shown in Figure 3: phase demodulation output module 301, loop filtering module 302, digital controlled oscillator module 303 and frequency divider 304.
Receive buffer circuit 205 as the memory block that receives data, the inflow of its data and outflow are respectively to carry out under the effect of source end clock and local clock.Though it is not the clock signal of source end that reception buffer circuit 205 writes the clock signal of data, but the speed that writes data is relevant with the frequency of source end clock, and the variation tendency that therefore receives data volume in the buffer circuit 205 has just reflected the phase place difference of two clocks.
Phase demodulation output module 301 is used for the phase place difference of clock is quantized, and this differing is converted into the controlled quentity controlled variable of representing input clock and phase-locked loop self natural frequency difference.This controlled quentity controlled variable just can be controlled digital controlled oscillator module 303 and produce the clock signal consistent with input clock frequency.The sample point of this quantification is chosen at the moment after last byte of Circuit Service frame writes buffer circuit, because should be the data cached peaked moment that reaches this moment, actual value and theoretical maximum with this moment compare, and both differences just reflect the trend of clock jitter.
Loop filtering module 302 is carried out smoothly the controlled quentity controlled variable of phase demodulation output module 301 outputs by filtering, reduces because the delay variation of introducing in the transmission circuit traffic frame process.If do not carry out this smoothing processing, will there be bigger shake in the recovered clock signal, directly influence the performance of Circuit Service.The method of described filtering has a lot, adopt in the present embodiment based on amplitude limit disappear tremble filter method the compound filter mode to obtain more performance.
Digital controlled oscillator module 303 is under the driving of local crystal oscillator, and the principle of utilization fractional frequency division is constantly adjusted the mould value of distributing and obtained required frequency.The input of digital controlled oscillator module 303 is frequency difference controlled quentity controlled variables, the difference that its output frequency of digital controlled oscillator module and the centre frequency of himself need be offset is told in this input, this controlled quentity controlled variable is converted into the action period of different frequency division mould values in digital controlled oscillator module 303 inside, obtain the frequency of needs in the mode of continuously smooth.
The frequency of digital controlled oscillator module 303 outputs enters frequency divider 304, through different allocation process, distributes to above-mentioned three modules 205,301,302 and uses.When whole loop entered lock-out state, the clock recovered frequency was consistent with source end clock frequency, and it is constant that phase difference is tending towards.
Clock recovery process based on above-mentioned adaptive clock recovery module 207 comprises the steps:
A) represent the data of source clock frequency to be written into to receive buffer circuit 205, clock recovered from receive buffer circuit 205 sense data to NRZ-＞HDB3 module 206; Simultaneously, receive buffer circuit 205 store status is sent to phase demodulation output module 301.
Here, the variation tendency that receives data volume in the buffer circuit 205 has been represented the phase place difference of source clock and local recovery clock.
B) phase demodulation output module 301 is according to the store status that receives buffer circuit 205, the largest buffered amount departs from the difference of preset reference point in the acquisition reception buffer circuit 205, this difference has been represented the phase error between the input and output clock, then this difference is quantized, promptly be converted into the frequency deviation controlled quentity controlled variable of digital controlled oscillator, this controlled quentity controlled variable has been represented the instantaneous frequency difference between the loop center frequency of incoming frequency and adaptive clock recovery module 207.
Because system realizes the restriction of precision, use frequency deviation in a big way of narrow numeric representation to change, linear mapping relations will cause the two ends of frequency deviation controlled quentity controlled variable span that bigger clock output jitter is arranged.Therefore, the present invention preferably is designed to exponential function with phase characteristic, makes digital controlled oscillator 303 carry out that the jittering characteristic that reaches unanimity is arranged when recovered clock generates.If the frequency of input has exceeded the frequency-tracking scope of phase-locked loop, the frequency deviation controlled quentity controlled variable of phase demodulation output can maintain a maximum, can not guarantee that loop enters lock-out state.
C) the phase demodulation output result of 302 pairs of phase demodulation output modules of loop filter module 301 input carries out filtering and disappears and tremble.
In the ideal case, stable if input clock keeps, behind loop-locking, the result of phase demodulation output also can be stabilized in a certain numerical value.But because the influence of the transmission characteristic of EPON itself, must additional time delay shake on the E1 frame of receiving.These shakes all can be reflected on the result of phase demodulation output, if do not add restriction, gently then shake are delivered on the output clock, and are heavy then phase-locked loop can't be locked.Therefore, generally loop filter module 302 will be set after the phase demodulation output, the identified result of process filtering drives digital controlled oscillator module 303 again and produces the clock frequency that needs.The implementation method of loop filter module 302 is varied, all is in essence to realize a wave digital lowpass filter, is limited in the shake of accumulating on the identified result.
Loop filter module 302 preferred employing amplitude limits of the present invention disappear and tremble filter method, and implementation procedure is as follows:
A filtering counter is set, each phase demodulation output valve and current filtered effective value is compared:
If phase demodulation output valve=current effective value, then counter remains unchanged;
If phase demodulation output valve＞current effective value, then counter adds 1, and whether judges current Counter Value more than or equal to predefined higher limit N, if, then current effective value is added 1, and with counter O reset; Otherwise, do not change current effective value, proceed to judge;
If phase demodulation output valve＜current effective value, then counter subtracts 1, and whether judges current Counter Value smaller or equal to predefined lower limit-N, if, then current effective value is subtracted 1, and with counter O reset; Otherwise, do not change current effective value, proceed to judge.
Like this, the phase demodulation output valve surpassed continuously former effective value N time after, effective value just changes, and the amplitude of change is 1, thereby avoids effective value frequently to be changed, and plays the effective smoothing effect of input value.
D) core of digital controlled oscillator module 303 is exactly a multi-modulus frequency divider, by clocklike changing frequency dividing ratio, obtains the frequency output of a fractional frequency division.
The way that digital controlled oscillator module 303 produces different frequency is to use (n-1) and n cycle to replace the mode of frequency division, and x time (n-1) frequency division and y time n frequency division hocket, and comprehensive result obtains a fractional frequency division ratio between (n-1) and n.The clock frequency that obtains the both positive and negative deviation for convenience, this programme use (n-1), n and three mould frequency dividers (n+1) as frequency synthesizer.Add the use that subtract pulse is controlled different frequency division mould values by generation in the design.The advantage of this programmable frequency divider be realize simple, controllable frequency wide ranges, but when changing frequency division mould value, once sudden change takes place output clock phase, therefore the change cycle of preferably this mould value will try one's best evenly, changes slow as far as possible.
The clock of digital controlled oscillator module 303 outputs produces the timing signal that each module needs through necessary frequency dividing circuit, and the byte pulse of reading of E1 is connected on the buffer circuit, constitutes the loop of a closure.
Referring to shown in Figure 5, up direction:
Step 21. enters the processing of the Circuit Service E1/T1 signal of ONU through E1/T1 Interface circuit 101, converts single channel HDB3 line code to HDB3 code signal that the two-way unipolarity is represented, input E1/T1 simulation unit 102.
Step 22.E1/T1 simulation unit 102 is dressed up mac frame with the Circuit Service data set that receives and is sent to E1/T1 simulation unit Multiplexing module 103.
Detailed process in E1/T1 simulation unit 102 comprises:
A '. two-way HDB3 code signal at first enters HDB3-＞NRZ module 201, extracts a route road clock signal and one road NRZ (NRZ) encoded data signals.
B '. under the driving of resulting line clock, described data-signal is written into transmission buffer circuit 202 with the form of serial data stream, and the data-signal of importing is carried out buffer memory, waits for that framing sends.
C '. framing processing module 203 begins to assemble the mac frame that contains the Circuit Service data in the moment of authorized signal.The source and destination MAC Address of this mac frame offers framing processing module 203 according to pre-configured source and destination mac address information by configuration management interface 208 by network management system; Fill in the data field of mac frame from sending the Circuit Service data that buffer circuit 202 is read; After finishing, the mac frame assembling sends to E1/T1 simulation unit Multiplexing module 103 immediately.
The said process substantially all corresponding step with down direction is identical, and different is that for the allocated bandwidth of up direction, the present invention adopts Dynamic Bandwidth Allocation (DBA) mechanism.ONU obtains to send the bandwidth of E1 Frame in each DBA cycle, the E1 module sends bandwidth authorizing in acquisition and just begins framing constantly, and will send the whole framing of data in the buffer memory as possible and send, because system has adopted quasi-periodic DBA scheme, so the frame length of E1 frame is variable.The EPON default excursion in DBA cycle, also just define the frame length scope of E1 frame.
Specifically comprise: at the up direction of ONU to OLT, the EPON system requirements uses the distribution mechanism of dynamic bandwidth.For ONU, OLT earlier sends to ONU by the allocated bandwidth frame with the initial delivery time information of appointment, after the PON interface core control circuit 105 of ONU is judged the moment that local clock arrives described OLT appointment, all E1 in this ONU send the authorization signal of initial transmission, by E1/T1 simulation unit Multiplexing module 106 this authorization signal is distributed to each E1/T1 simulation unit 102 among the OLT, until arriving framing processing module 203.
Here adopt the advantage of E1 Frame frame length variable solutions to be, can send the shortest principle control frame length of data stand-by period in the buffer memory, change the delay variation that brings to the E1 Frame to eliminate the DBA cycle effectively according to making.Because the receiving end of E1 simulation unit receives in the buffer memory in the data capacity in assessment, with maximum as foundation, and peaked appearance can only be after receiving an E1 Frame, if it is big that the DBA cycle becomes suddenly, it is big that the E1 frame frame length of receiving also will and then become, make after receiving the E1 Frame differentiation constantly, the maximum of intercepting and capturing data in institute's buffer memory can also maintain previous level, vice versa.By these measures, can eliminate the DBA cycle and change the shake that the E1 subsystem is increased.
Step 23.E1/T1 simulation unit Multiplexing module 106 will be from system the multichannel mac frame that receives of each E1/T1 Circuit Emulation Unit 102 be multiplexed into one tunnel output.
Step 24.PON interface core control circuit 105 is finished the transmission of mac frame by optical distribution network (ODN).
Step 25. is in the OLT side, and PON interface core control circuit 104 sends to E1/T1 simulation unit Multiplexing module 103 by the reception that ODN finishes mac frame.
Step 26.E1/T1 simulation unit Multiplexing module 103 is assigned to corresponding E1/T1 Circuit Emulation Unit 102 respectively after the mac frame that receives is decomposed.
Simultaneously, will send authorized resolution to each E1/T1 Circuit Emulation Unit 102.
E1/T1 Circuit Emulation Unit 102 among the step 27.OLT extracts business datum from the mac frame of receiving, under the driving of recovered clock, send to E1/T1 Interface circuit 101 after business datum encoded.
After the HDB3 code signal of after step 28.E1/T1 interface circuit 101 is handled the two-way unipolarity being represented converts the ambipolar HDB3 line code of single channel to, export the EPON external equipment to.
In a word, the present invention is in order to reduce the shake of E1 clock output, guarantee the E1 signal transfer quality, employing based on the adaptive clock recovery method of the principle design of digital phase-locked loop before clock output, carry out last assurance on the whole, the part that can introduce shake in system adopts loop filtering, thereby reduces the index request of adaptive clock recovery part, reduces and realizes difficulty.In addition, the DBA algorithm has guaranteed that the E1 Frame in time obtains the transmission bandwidth that needs, the E1 Frame adopts the frame structure of variable length to adapt to this allocated bandwidth mechanism, eliminated the data frame transfer time delay that the DBA algorithm may bring effectively and changed the influence that E1 clock output jitter is brought.Down direction does not have DBA mechanism, does not just have this influence, but has brought the harm of bandwidth resources competitions yet.In this case, the transmission priority of different queue has been controlled in strictness of the present invention, guarantees the preferential transmission route of E1 Frame, and this scheme is limited in the propagation delay time variation of descending E1 Frame in certain scope, has finally guaranteed the shake index of output clock.
The above only is preferred embodiment of the present invention, in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is not equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1, the method on EPON, transmitted of a kind of Circuit Service based on Ethernet, on the Ethernet passive optical network that is applied to form by OLT, ODN and a plurality of ONU, this method comprises the signal transmission to the down direction of ONU by OLT, and by the signal transmission of ONU to the up direction of OLT, it is characterized in that
Comprise at down direction:
A1) the Circuit Service Signal Separation to every road E1/T1 form of entering OLT goes out line clock and Circuit Service data, under the driving of described line clock the Circuit Service data is write buffer circuit and carries out buffer memory;
A2) under the driving of OLT local clock, from buffer circuit, read the Circuit Service data according to the bandwidth that obtains, the Circuit Service data are encapsulated in the mac frame together with corresponding source address and destination address, each road mac frame are multiplexed into lead up to ODN and send to ONU;
A3) after ONU received mac frame, decomposition-reduction was a multichannel, every road is extracted the Circuit Service data respectively write in the buffer circuit;
A4) according to the state of buffer circuit, in the moment of receiving the Circuit Service frame, after the largest buffered data volume is shone upon through exponential function with the difference of the theoretical center value of presetting, as numerical control oscillator frequency deviation controlled quentity controlled variable, local clock is reverted to the recovered clock consistent with clock originator, under the driving of this recovered clock, the Circuit Service data that read in the buffer circuit are handled;
Comprise at up direction:
B1) the Circuit Service Signal Separation to the E1/T1 form that enters ONU goes out line clock and Circuit Service data, and the Circuit Service data are written into buffer circuit and carry out buffer memory under the driving of described line clock;
B2) ONU is at every turn when obtaining Frame transmission bandwidth, determine to send the frame length of mac frame according to the Circuit Service data volume of buffer memory in the buffer circuit, and the Circuit Service data of storing in the buffer circuit are encapsulated in the mac frame together with corresponding source address and destination address, each road mac frame is multiplexed into leads up to ODN and send to OLT;
B3) after OLT received mac frame, decomposition-reduction was a multichannel, every road is therefrom extracted the Circuit Service data respectively write in the buffer circuit;
B4) according to the state of buffer circuit, in the moment of receiving the Circuit Service frame, after the largest buffered data volume is shone upon through exponential function with the difference of the theoretical center value of presetting, as numerical control oscillator frequency deviation controlled quentity controlled variable, local clock is reverted to the recovered clock consistent with clock originator, under the driving of this recovered clock, the Circuit Service data that read in the buffer circuit are handled.
2, method according to claim 1, it is characterized in that, source address described in steps A 2, the B2 and destination address are after the link of system configuration Circuit Service, and source address, destination address and their mapping relations of this link are kept at respectively among OLT and the ONU
OLT or ONU according to the link that current transtation mission circuit business datum is adopted, find the source address and the destination address of this link in this locality when the encapsulation mac frame.
3, method according to claim 1 is characterized in that, reading the Circuit Service data described in the steps A 2 from buffer circuit is earlier the Circuit Service metadata cache to be read the Circuit Service data after the time in an encapsulation cycle.
4, method according to claim 1 is characterized in that, encapsulation described in steps A 2 and the B2 is that the Circuit Service data are carried out the encapsulation of quasi periodicity ground.
5, method according to claim 1; it is characterized in that described encapsulation process is the ethernet frame structure of employing standard, when the Circuit Service data encapsulation is gone into the load bearing unit of Ethernet; the data cell that has added redetermination is used for frame losing protection, the frame head checking treatment of Circuit Service frame.
6, method according to claim 1 is characterized in that, local clock recovery process is the state according to buffer circuit described in steps A 4 and the B4, utilizes digital phase-locked loop to recover the recovered clock consistent with clock originator with local clock.
7, method according to claim 6 is characterized in that, largest buffered data volume described in steps A 4 and the B4 is the inherent variability of source end clock and phase-locked loop centre frequency with the difference of the theoretical center value of presetting.
8, method according to claim 7 is characterized in that, local clock recovery process described in steps A 4 and the B4 is further carried out loop filtering to the inherent variability that obtains behind the inherent variability of determining source end clock and phase-locked loop centre frequency.
9, method according to claim 8, it is characterized in that, described numerical control concussion process comprised when local clock described in steps A 4 and the B4 recovered: based on the fractional frequency division technology of multimode frequency division formation, frequency division hockets between predefined higher limit N and N+1 or N and N-1, can obtain a frequency dividing ratio between N and N+1 or N and N-1, obtain needed frequency with this.
10, method according to claim 9, it is characterized in that, described numerical control concussion process further comprised when local clock described in steps A 4 and the B4 recovered: each input frequency difference is all corresponding cycle that frequency dividing ratio changes, frequency dividing ratio of each cyclomorphosis.
11, method according to claim 1 is characterized in that, ONU described in the step B2 when obtaining Frame transmission bandwidth, farthest obtains the Circuit Service data of storing in the buffer circuit at every turn.
12, method according to claim 1 is characterized in that, in the described encapsulation process of steps A 2 and B2 further the mac frame of Circuit Service data be set to the highest transmission priority.
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| CN101252403B (en) * | 2008-01-22 | 2011-12-07 | 中兴通讯股份有限公司 | Realizing method of traffic transmission in light transmitted network |
| CN101577600B (en) | 2008-05-09 | 2013-04-24 | 华为技术有限公司 | Time synchronization method, system and optical network equipment for passive optical network system |
| CN102237942B (en) * | 2011-06-29 | 2014-11-19 | 北京阳光金力科技发展有限公司 | Clock regulation method and device for multi-channel transmission platform (MCTP) |
| CN102412923B (en) * | 2011-11-18 | 2016-05-25 | 烽火通信科技股份有限公司 | A kind of method that realizes clock synchronous between OLT and ONU in EPON system |
| CN103916160A (en) * | 2012-12-28 | 2014-07-09 | 北京中电华大电子设计有限责任公司 | UWB MAC layer circuit supporting point-to-point communication |
| CN103490841A (en) * | 2013-09-25 | 2014-01-01 | 科大智能（合肥）科技有限公司 | Clock recovery method based on distributed frame header in multi-path E1 multiplexing system |
| CN104468015B (en) * | 2014-12-12 | 2017-03-08 | 成都朗锐芯科技发展有限公司 | A kind of network clocking recovery system based on TDM |
| CN105739289B (en) * | 2016-03-18 | 2017-10-17 | 山东交通学院 | A kind of pulse interval measuring method and circuit based on integrated phase detection discriminator |
| CN113115132B (en) * | 2021-03-01 | 2022-06-03 | 烽火通信科技股份有限公司 | Method and device for recombining frames in OLT (optical line terminal) |
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