FI89757B - FOERFARANDE FOER ATT UTFOERA EN ANSLUTNINGSUTJAEMNING - Google Patents

Description

89757

The present invention relates to a method for performing interface smoothing in connection with frame mapping, wherein the frame consists of a fixed number of constant-length bytes.

The method of the invention is suitable, for example, for performing connection equalization, for example, when mapping a 139,264 kbit / s plesiochronous information signal to an SDH (Synch-10 ronous Digital Hierarchy) VC-4 container. The known method comprises nine rows identical in mapping mode, which in turn consist of a one-byte route header (PÖH), twenty 12-byte information bit groups (96 I) and 15 bytes (W, X, Y, Z) placed at the beginning of each group. , for padding (R), header (0), interface smoothing capability (S), and interface smoothing control bits (C). A schematic view of one of the 20 rows of the information part of such a frame according to a conventional SDH hierarchy, i.e. the so-called VC-4 container, is shown in Fig. 1.

From the notations related to Fig. 1, it can be seen that a bypass bit B is included in the byte Z, which, depending on the need for connection equalization, is either an information bit or a padding bit without information. The need to use interface equalization arises when the speed of the incoming information signal deviates from its nominal value to some extent, for example upwards, whereby bits that are not recorded to be mapped tend to accumulate in the buffer of the unit performing the ma-hold. In this case, the use of the interface-30 sausage bit makes it possible to decompress this buffer at a slightly higher speed than usual, whereby the filling level of the buffer can be kept as constant as possible. In mapping according to the current SDH standard, the nominal line rate of 139,264 kbit / s means that two of the nine rows of bytes Z of the VC-4 container 35 contain the information bit 2 f, -7 z n - / v, the remaining seven being bits without information. Thus, if the speed of the incoming information signal is above its nominal value, there are seven bit positions in the frame in which information can be included. If the speed of the incoming information signal is below its nominal value, then two information bits can be removed from the frame using the interface equalization opportunity bits and replaced with bits that do not contain information.

10 However, the problem with standard VC-4 mapping is the use of interface equalization option bits. Due to the high signal rate, about 140 mega-bits / s, the use of interface equalization bits requires very fast or complicated circuit solutions to perform such bit-based equalization, especially when the SDH is otherwise byte-based.

It is therefore an object of the present invention to provide a new method for performing connection equalization, by means of which method the above-mentioned problem is eliminated and it is possible to perform connection equalization by means of a much simpler apparatus. This is achieved by the method according to the invention, which is characterized in that for connection equalization one or more bytes of the frame are reserved as equalization possibility bytes (Z) which, depending on the equalization requirement, contain either information bits (I) or non-information fill bits. Preferably, one equalization byte is placed in each row. When applying the method according to the invention to the mapping of a 139264 kbit / s plesiochronous information signal, it is kek-. 30 is characterized in that in each row of the frame one of the initial bytes is reserved entirely as an equalization possibility byte (Z), which, depending on the need for equalization, contains either information bits (I) or non-information padding bits, with a nominal rate of seven. The equalization bytes (Z) of the 35 rows contain information bits and the interface equalization bytes (Z) of the two rows contain bits without information.

The method according to the invention will now be described in more detail in connection with one exemplary embodiment with reference to the accompanying drawing, in which Figure 1 shows a prior art mapping diagram of a STM-1 frame VC-4 container, Figure 2 shows a line of Figure 1 mapped according to invention 10 and Figure 3 shows connection alignment options placement in VC-4 containers.

Figure 2 shows an application of the method according to the invention from mapping a plesiochronous in-15 information signal at 140 megabits / second to one row of a VC-4 container of an STM-1 frame. This schematic diagram shows that the mapping method corresponds in schematic structure completely to the known solution shown in Fig. 1. The only difference is that the bytes Z are now entirely reserved for the interface equalization bits S, whereas in the known case according to Figure 1, six of the bits in the byte Z were reserved as information bits I and only one as the interface equalization bit S.

Figure 3 shows how the connection equalization capability is applied to the mapping of the information signal to the VC-4 container. Figure 3 shows the filling of a container in the case of a nominal line speed, in which case the shaded Z-bytes are information-containing bytes and the unshaded or white Z-bytes are information-free fillable -30s. The bytes containing information are then placed in seven rows of the nine rows of the VC-4 container, and the bytes Z, which are filled with bits without information, are placed in two rows. These two lines are the third and eighth lines in the example of Figure 3. As can be seen from Figures 2 and 3, in the method according to the invention, the alignments are no longer performed bit by bit but byte-by-byte. This greatly simplifies the practical implementation of the method. As shown in Figure 2, the C-bits in bytes X further indicate the use of equalization. C 5 = 0 indicates that Z in that line has an information byte, and C = 1 indicates that Z is a non-information byte.

Mapping such as that shown in Figure 2 is considerably simpler to implement on the device itself than mapping 10 as shown in Figure 1. Byte-based CMOS logic does not require a bit-rotating function at all, which shifts the byte boundaries as equalization bits are used. Now the information is always in whole bytes. Simpler implementation also means safer operation and a cheaper solution. However, the smoothing-induced jitter before filtering increases eightfold with the mapping method of Figure 2 compared to the mapping mode of Figure 1 because the alignment bits now appear in eight bit bytes instead of single bits, but as the equalization frequency becomes 16 kHz ± Δ, the jitter is effectively filtered in desynchronization. Moreover, when the desynchronizer has to deal with the 24 UI phase jumps caused by the pointers in any case, there will also be no new requirements for the lengths of the data buffers.

The method according to the invention for performing connection equalization has been illustrated above in connection with one exemplary embodiment. It is understood, however, that such a method protects the interface equalization. 30 can be applied to many other mapping applications where high speeds cause problems in providing interface smoothing on a bit basis.

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Claims (3)

A method for performing connection equalization in connection with frame mapping, wherein the frame consists of a fixed number of bytes of standard length, characterized in that for the connection equalization one or more of the frame bytes is reserved as the equalization possibility byte (Z), which, depending on the equalization need, contains the information. (I) or fill pieces without information. 2. A method according to claim 1, wherein the frame consists of a number of mapping modes among identical rows, characterized in that in each row an equalization exchange (Z) is placed. 15 A method for performing connection equalization when mapping a 139,264 kbit / s plesiochronic information signal in SDH's (Synchronous Digital Hierarchy) VC-4 container, which comprises nine tiles in the mapping method among identical rows, which in their side consists of a one byte path header (PÖH), twenty twelve byte information bytes (96 I) and one byte located at the beginning of each group (W, X, Y, Z) for information (I), fill (R), heading (O) , the connection equalization opportunity (S) and the connection equalization check bits (C), characterized in that in each row of the frame one of the initial s bytes is reserved entirely as a equalization possibility byte (Z), which, depending on the equalization need, contains either information (or information) fill bits without information, where at nominal speed equalization bytes (Z): 30 pi seven rows in a frame contain information bits and connection equilibrium bytes (Z) pi two rows contain bits without information. in