GB2260469A

GB2260469A - Justification method

Info

Publication number: GB2260469A
Application number: GB9221191A
Authority: GB
Inventors: Reino Urala; Jouko Katainen; Bo Loennqvist
Original assignee: Nokia Telecommunications Oy
Current assignee: Nokia Oyj
Priority date: 1991-10-08
Filing date: 1992-10-08
Publication date: 1993-04-14
Anticipated expiration: 2012-10-08
Also published as: DE4233805B4; GB9221191D0; FI89757B; GB2260469B; FR2684825B1; DE4233805A1; FI914746A; FR2684825A1; FI89757C; FI914746A0

Abstract

A justification method to be used in frame mapping when the frame consists of a fixed number of bytes of constant length. For carrying out justification with an apparatus which is as simple and reliable as possible, one or more bytes of the frame are assigned as justification opportunity bytes (Z), which, depending on the need for justification, contain either entirely information bus (I) or entirely stuff bits without information. <IMAGE>

Description

---1 n 1 Justification method 3 4,- -) The present invention pertains to a

justification method to be used in frame mapping when the frame consists of a fixed number of bytes of constant length.

The method of the invention is suitable e.g. for justification carried out for instance when a plesiochronous information signal with 139,264 kbit/s is mapped into a container VC-4 of the SDH (Synchronous Digital Hierarchy). The known method comprises nine rows, which are identical with one another as regards the way in which they are mapped and which consist of a path overhead (POH) of one byte, 20 information bit groups of 12 bytes (96 1), and a byte (W, X, Y, Z) placed at the beginning of is each group for information bits (I), stuff bits (R), overhead bits (0), justification opportunity bits (S) and justification control bits (C). Figure 1 schematically shows one row of the information portion, i.e. a container VC-4, of such a conventional SDH frame.

The legend of Figure 1 shows that the byte Z contains a justification opportunity bit S, which, depending on the need for justification, is either an information bit or a stuff bit without information. A need for justification arises when the speed of an incoming information signal deviates from its nominal value to some extent, e.g. upwards, whereby bits that the mapping unit does not manage to map tend to accumulate in the buffer of said unit. In such a case the use of a justification bit enables reading of this buffer with a speed slightly higher than usual, whereby the degree of fullness of the buffer can be kept as constant as possible. In mapping of the current SDH standard, the nominal speed 137,264 kbit/s means that two of the bytes Z of the nine rows of the container VC-4 contain an information bit, whereas the remaining seven contain bits without infon-nation. Therefore.

2 if the speed of an incoming information signal is above its nominal value, the frame comprises seven bit positions into which information can be inserted. If the speed of an incoming information signal is below its nominal value, two information bits may be removed f rom the frame by utilising justification opportunity bits and be replaced by bits without information.

However, in VC-4 mapping according to the standard, it is the use of justification opportunity bits that is problematic. owing to the great speed of the signal, approx. 140 megabits/s, the use of justification opportunity bits requires a very fast or complicated circuit arrangement for such bitwise justification, especially as the SDH is otherwise byte-organised.

The object of the present invention is thus to provide a novel justification method with which said problem is obviated, and justification can be carried out with a considerably simpler apparatus. This is achieved with the method of the invention, which is characterised in that for justification one or more bytes of the frame are assigned as justification opportunity bytes (Z), which, depending on the need for justification, contain either information bits (I) or stuff bits without information. Justification opportunity bytes are preferably placed one in each row. When the method of the invention is applied in mapping of a plesiochronousinformation signal with 139,264)tbitls, the invention is characterised in that in each rav of the frame one of the bytes placed at the beginning of the qroups is entirely assigned as a justification opportunity byte M, which, depending on the need for justification, contains either information bits (I) or stuff bits without information, whereby with the nominal speed in the frame the justification opportunity bytes (Z) of seven rows contain information bits and the justification opportunity bytes (Z) of two rows contain bits without information.

Z_ i 3 In the following the method of the invention will be described in more detail by means of one exemplifying embodiment with reference to the accompanying drawingsin which Figure 1 is a prior-art mapping diagram of one row of a container VC-4 of an STM (Synchronous Transport Module) frame; Figure 2 shows the row of Figure 1 mapped according to the invention; and Figure 3 shows the disposition of justification opportunity bytes in containers W-4.

Figure 2 shows an embodiment of the invention concerning mapping of a plesiochronous information signal with 140 megabits/second into one row of an STM-1 frame container W-4. This diagram shows that as regards the is diagrammatic structure, this mapping fully corresponds to the known solution of Figure 1. The only difference is that the bytes Z are now entirely assigned to the justification opportunity bits S, whereas in the known case of Figure 1, six of the bits of the byte Z were assigned as information bits I, and only one as a justification opportunity bit S.

Figure 3 shows how a justification opportunity byte is applied in mapping of an information signal into a container W-4. Figure 3 shows filling of the container in the case of nominal speed, the shaded bytes Z being bytes containing information, and unshaded or white bytes Z stuff bytes without information. Bytes containing information are thus placed in seven out of the nine rows of the container W-4, and the bytes Z which are stuffed with bits without information are placed in two rows. In the example of Figure 3, these two rows are the third and the eighth row. As shown by Figures 2 and 3, in the method of the invention justification is not carried out by bits but bytewise. The realisation of the method therefore becomes considerably simpler. As shown by Figure 2, the C 4 is bits in the bytes X still indicate the use of justification. C = 0 indicates that in the row concerned Z is an information byte, and C = 1 indicates that Z is a byte without information.

Mapping as illustrated in Figure 2 is markedly simpler to realise in the apparatus than mapping as shown by Figure 1. No bit-rotating function is required in the byte-oriented CMOS logic f or moving the byte boundary in response to the use of justification bits. Now information is always in whole bytes. Simpler realisation also means more reliable operation and a less costly solution. On the other hand, the mapping of Figure 2 causes flickering which before filt-ering is eight times stronger than the flickeering caused by the mapping of Figure 1, because in the nta,,:pirr,r of Figure 2 the justification bits are in bytes of eight bits and not asindividual bits, but since the justification frequency is 16 kHz A, flickering is effectively filtered in the phase lock of the desynchroniser. Moreover, as the phase changes of 24 Unit Intervals caused by the pointers are to be handled in the desynchroniser in any case, no new requirements arise for the lengths of the data buffers either.

The justification method according to the invention was illustrated above by means of one exemplifying embodiment. It is however to be understood that such a justification method bytewise as described may be applied in other mapping embodiments where great speeds cause problems in bitwise justification.

1

Claims

1. A justification method to be used in frame mapping when the frame consists of a fixed number of bytes of constant length, c h a r a c t e r i s e d in that f or justification one or more bytes of the frame are assigned as justification opportunity bytes (Z), which, depending on the need for justification, contain either information bits (I) or stuff bits without information.

2. A method according to claim 1 when the frame consists of a number of rows identical with one another as regards the way in which they are mapped, c h a r a c t e r i s e d in that justification opportunity bytes (Z) are placed one in each row.

3. A justification method to be used when a plesiochronous information signal with 139,264 kbit/s is mapped into an SDH (Synchronous Digital Hierarchy) container VC-4 comprising nine rows, which are identical with one another as regards the way in which they are mapped and which in turn consist of a path overhead (POH) of one byte, 20 information bit groups of 12 bytes (96 1), and a byte (W, X, Y, Z) placed at the beginning of each group for information bits (I), stuff bits (R), overhead bits (0), justification opportunity bits (S) and justification control bits (C), characterised in that in each row of the frame one of said bytes placed at the beginnings of the groups is entirely assigned as a justification opportunity byte (Z), which, depending on the need for justification, contains either information bits (I) or stuff bits without information, whereby with the nominal speed in the frame the justification opportunity bytes (Z) of seven rows contain information bits and the justification opportunity bytes (Z) of two rows contain bits without information.

4. A justification method substantially as hereinbefore described with reference to Figs. 2 and 3 of the accompanying drawings.