FR2670937A1 - MATRIX ELECTROOPTIC SCREEN WITH ACTIVE CONTROL WITH INTEGRATED TEST SYSTEM. - Google Patents

Abstract

Active control matrix electrooptical screen, characterized in that the lines (L1 to LN) and columns (C1 to CN) of the addressing conductor matrix are connected to a system of test circuits (R1, R2, R3, R4) mounted on the same substrate as said matrix. Application, in particular, in liquid crystal displays.

Description

SCREEN MATRIX EIJCTROOFTIC SCREEN
ACTIVE INTEGRATED TEST SYSTEM
The present invention relates to active control matrix electrooptic screens, more particularly the screens in which each image point is defined at the intersection of two orthogonal conductor networks called lines and columns, at least by a capacitor made by an electro-optical element. It preferably relates to screens in which the optical element is a liquid crystal and more particularly those which comprise in series with the capacitor an active control element made according to the thin-layer technology. However, the present invention can also be used. to apply to other types of electro-optical screens having the same characteristics, especially to screens that can be made on a substrate for the manufacture of semiconductor components.

 This type of matrix screen is, in general, made up of a very large number (greater than 100) of rows and columns made by metal deposition on the substrate enclosing the electro-optical elements or on a layer of insulating material. For the screen to work properly, these lines and columns must not have any faults. Thus, they must be continuous and not give rise to short circuits, especially at crossings. To verify these two conditions, external test machines are currently used which make it possible to apply certain tensions to the lines and columns of the screen to be tested. These types of machines are impractical to implement and require a very large number of connections.

 The present invention aims to overcome the disadvantages of external test machines and to provide a solution for simply testing the continuity of rows and columns.

 Accordingly, the subject of the present invention is an active control matrix electro-optical screen, characterized in that the rows and columns of the addressing conductor matrix are connected to test circuits made on the same substrate as said matrix.

 In this case, the test circuits are integrated, that is to say made at the same time as the lines and the active element of the matrix, and it has no more problems of connection, which makes it possible to realize very easily the tests concerning the continuity of lines and columns and the absence of short circuit by simply applying a voltage to the input of these different circuits.

According to a preferred embodiment, the test circuits consist of two shift registers with
N stages connected to the N rows of the matrix and two N 'shift registers connected to the N' columns of the matrix. Preferably, the shift register is made using static or dynamic D flip-flops.

 According to another characteristic of the present invention, in the case of actively controlled matrix circuits, the test circuits are made at the same time as the control elements of the matrix. Preferably, the test circuits are made using layer-thin technology.

 Other features and advantages of the present invention will appear on reading the description of various embodiments made with reference to the accompanying drawings in which - Figure 1 is a schematic view of a matrix electro-optical screen comprising transistors of As an active control element according to the known art to which the present invention can be applied - FIG. 2 is a schematic view of an embodiment of a matrix screen with integrated test circuits according to the present invention. FIGS. 3A and 3B are respectively a block diagram and a timing diagram of a first embodiment of a shift register that can be used in the present invention - FIGS. 4A and 4B are respectively a block diagram and a timing chart of a second embodiment of a shift register that can be used in the present invention - FIGS. 5A and 5B are respectively A block diagram and a timing diagram of a third embodiment of a shift register that can be used in the present invention are shown. FIGS. 6A, 6B and 6C are diagrams and curves explaining the operation of the present invention.

 The present invention is explained below with reference to a matrix screen with liquid crystal cells.

 It is obvious to those skilled in the art that it can be implemented to make cell matrix screens using technologies other than liquid crystal.

 As shown diagrammatically in FIG. 1, a screen allowing the implementation of the present invention consists of two orthogonal networks of lines Li, L2, ...

LN and columns C1, C2, C3, C4, ..., CN '. At the intersection of each line and each column is connected an image point formed of an active switching element T and a capacitor
C. In the embodiment shown, the active switching element T is constituted by a transistor made by thin-film technology or TFT for Thin Film Transistor (in English). In general, the number N of lines and N 'of columns is very important, often greater than 100 and can even be up to 1000. In addition, for the screen to work, the lines and columns must have neither cut nor In accordance with the present invention, it is therefore provided on the same substrate as the substrate for making thin-film transistors T, a number of test circuits which are connected directly to the different columns and to the different lines. . Preferably, these test circuits are manufactured at the same time as the transistors T, as will be explained in more detail below.

According to a preferred embodiment shown in FIG. 2, the test circuits consist of shift registers Ri, R2, R3, R4 connected directly to the rows and to the columns. In more detail, the registers R1 and R3 which are connected to each column C1, C2, C3,
CN 'are registers with N' stages of which each stage is connected to a column. Similarly, the shift registers R2 and
R4 which are connected to the lines LI to LN are N-stage shift registers, each stage of which is connected to a line, as shown in FIG. 2. In this case, to carry out a test, a sequence of signals to operate the selected register, the other registers being set to OV and either the level of the voltages at the output of each stage is examined, or the current consumption on the supply conductors is measured, as will be explained in more detail below.

Preferably, each stage of the shift registers
Ri, R2, R3, R4 is constituted by a flip-flop D which can be a static or dynamic D flip-flop. In the following will be described with reference to Figures 3 to 5, different embodiments of registers using flip-flops D. These registers will be described using four flip-flops. However, it is obvious to those skilled in the art that these registers will be made with N or N 'flip-flops depending on the number of columns or rows.

 In FIG. 3A, there is shown a static shift register consisting of four flip-flops D 1, 2, 3, 4 synchronized to a clock state. In this case, the flip-flops 1, 2, 3, 4 are connected so that the outputs Q, Q of a flip-flop are respectively connected to the inputs D, D of the next flip-flop. In addition, in order to obtain the synchronization on a clock state, the flip-flops 1 and 3 receive on their clock input the signal H while the flip-flops 2 and 4 receive on their clock input the signal H. In this case, one obtains on the outputs D of the different flip-flops, the pulses DI, D2, D3, D4 represented on the timing diagram of FIG. 3B. These pulses are maintained during a clock period H or H.

 In FIG. 4A, there is shown a static shift register consisting of four flip-flops D 1 ', 2', 3 ', 4' synchronized on a clock edge. In this case, the clock inputs of the four flip-flops D receive the same clock signal H '. As shown in FIG. 4A, the series connected flip-flops D are synchronized on the falling edge of the clock signal H 'and switch according to the clock signal H'. In this case, on the outputs D, the pulses D1, D2, D3, D4 represented on the timing diagram of FIG. 4B are obtained.

 FIG. 5A shows a third embodiment of a shift register that can be used in the present invention. In this case, the D 1 ", 2", 3 ", 4" flip-flops are two-phase dynamic flip-flops. The Q output of a flip-flop is connected to the input D of the next flip-flop and pulses j 1, 2 out of phase of T are applied to the corresponding inputs of the flip-flops. Thus, on the outputs S1, S2, S3, S4, the pulses S1, S2, S3, S4 represented on the timing diagram of FIG. 5B are obtained.

 The operation of the test circuits according to the present invention will now be explained with reference to FIGS. 6A, 6B and 6C. FIG. 6A shows a four-column and four-line liquid crystal display having a cut-off at the third column and a short-circuit between the fourth and third lines.

On the other hand, the test circuits consist of shift registers R1, R2, R3, R4 formed of static D flip-flops synchronized on a clock edge. The registers
R2, R3, R4 are grounded while the register R1 receives a sequence of signals VDD, Vss> H, Do allowing its operation. When Do is applied to the register, we successively obtain on the columns connected to the outputs S1, 1; S2>1; S3, l; S4,1 the pulses represented on the timing diagram of FIG. 6B as a function of the clock pulse
H.

 To test for cuts and / or short circuits in columns and lines, the supply current is monitored on VDD or Vss on the four registers.

 If the operation is normal, a current I2 is detected due to the difference in voltage between the activated output of the register R1 (VDD) and the non-activated output of the register R3. If there is a break, a lower current I1 is detected and if there is a short circuit, a higher current I3 is detected.

A temporal analysis of the current, as shown in FIG. 6C, makes it possible to know the faulty track.

 The screen can also be tested by operating one of four registers and detecting the signal with a tip test at the other end.

As described in French patent No. 87 07941 in the name of THOMSON-CSF, the registers R1, R2, R3, R4 formed of the D flip-flops shown in FIGS. 3 to 5 can be produced using a layer-thin technology, that is, that is to say a technology identical to that used to make the control transistors T of the liquid crystal screen. As a result, the shift registers used to form the line and column test circuits can be made at the same time as the transistors T using this layer-thin technology. The technology for making thin-film transistors is well known to those skilled in the art and will not be redescribed here. Indeed, to implement this technology, one skilled in the art can refer in particular to the article of the technical journal THOMSON-CSF, Vol. 18 n04
December 1986 or other journals.

 On the other hand, the test circuits, namely the registers R1, R2, R3 and R4, can be located in a specific place on the substrate which makes it possible to cut them at the end of the final phase of the production of the 'screen.

Claims (6)

 Electroactive matrix screen with active control, characterized in that the lines (L1 to LN) and the columns (C1 to CN ') of the matrix of addressing conductors are connected to test circuits (R1, R2, R3, R4) made on the same substrate as said matrix.  2. Screen according to claim 1, characterized in that the test circuits consist of two registers (R2, R4) with N stages connected to the N rows of the matrix and two N 'shift registers (R1, R3) connected to the N' columns of the matrix.  3. Screen according to claim 2, characterized in that each stage of the shift register is constituted by a flip-flop D static or dynamic.  4. Screen according to any one of claims 1 to 3, characterized in that the test circuits are made at the same time as the control elements of the matrix.  5. Screen according to any one of claims 1 to 4, characterized in that the test circuits are made using a layer-thin technology.  6. Screen according to any one of claims 1 to 5, characterized in that the test circuits are positioned at a location to cut said circuits from the rest of the screen after its final phase of realization.