FR2616270A1 - Network of predeposited transistors, method of producing this network and an electronic circuit by means of this network - Google Patents

Abstract

The invention relates to a network of thin-film transistors made of amorphous or polycrystalline silicon. According to the invention, the transistors of such a network, deposited on an amorphous or polycrystalline substrate 1 (glass, metal, polymer), are predeposited and covered with a passivation layer 10. They are grouped together on the substrate 1 according to their dynamic and static properties. In order to produce a circuit, the passivation layer 10 is etched in order to give access to the sources 11, drains 12 and gates 3 of the selected transistors. A metal layer is deposited and then etched in order to provide the interconnections 13, 14. Application to integrated circuits having a low operating speed, 1 < 10 MHz, but having a large size, for display panels or so-called "memory-type" electronic funds-transfer cards.

Description

ARRAY OF PREPOSED TRANSISTORS, METHOD
OF REALIZATION OF THIS NETWORK, AND CIRCUIT
ELECTRONICS MADE BY MEANS OF THIS NETWORK
The present invention relates to a network of thin film transistors, pre-deposited on a substrate, the material of which is not monocrystalline. This array of field effect transistors is comparable to the pre-diffused circuits produced in conventional technologies on substrates and materials such as silicon, and the last level of metallization is produced at the request of the user: the transistors of the circuit have various geometries which make it possible to choose the gain, the power or the speed of operation for example, according to the envisaged use. The invention also relates to the process for producing a network of transistors in thin layers.

 Thin film transistors are known, and they are currently used either as discrete elements for the addressing of so-called pixel image points in flat liquid crystal screens or X image sensors or in logic circuits of flip-flops and registers å shift have been made. Their main interest lies in the integration of the multiplexing functions on the same substrate as the screen or the sensor.

 However, other applications can be envisaged using circuits based on thin film transistors.

They have limited operating speeds, less than 1
MHz if they are made of amorphous silicon, and less than 10
MHz stlls are made of polycrystalline silicon, this speed limitation being due to the low electronic mobility in the materials used. But this technology has the advantage of being able to be deposited at low temperature, that is to say around 250 to 800 degrees centigrade, in large areas, up to 30 x 30 cm2 and on various substrates such as glass, metals, polymers such as polyimides, or other substrates. The applications are therefore very specific, a typical example being the memory card comprising an integrated circuit.

 The object of the invention is to produce complex and varied electronic circuits from a single component, which is an array of thin film transistors.

The originality lies on the one hand in the use of thin-film transistors on various substrates, and on the other hand in the fact that the transistors have varied geometries and therefore that the basic functions can be optimized as a function of each. application: inverter, follower, rocker, etc. One can thus privilege, according to the sought objective, either the operating speed or the static performances such as the operating levels for each individual function.

 We will agree to call these networks of thin-film transistors "pre-deposited circuits": indeed, we cannot call them "pre-diffused" like circuits on monocrystalline silicon since there is no diffusion, nor "pre-implanted" like circuits on III-V materials since there is no layout.

 The method essentially concerns field effect transistors and it makes it possible to optimize specific circuits very quickly and to study their performance as a function. performance of individual transistors.

 It has two stages. During the first stage common to all the circuits, the individual transistors are produced with varied geometries and a spatial arrangement allowing their optimal use during the second stage.

In this second step, the circuits are individualized and the transistors are chosen from those which are deposited in the network of transistors according to their geometry, that is to say the characteristics which are expected of them. These transistors are then connected to each other by means of a metallic interconnection.

More precisely, the invention relates to a network of predisposed predisposed # on a substrate, comprising a plurality of individual field effect transistors, each transistor being isolated or connected to other transistors by a bus, this network being characterized in what
- the substrate is made of a non-monocrystalline material>
- The transistors are of the thin layer type, the layers of semiconductor materials constituting them being amorphous or polycrystalline.

The invention will be better understood from the detailed description of the manufacturing process, which will then be illustrated by a few examples of circuits, these descriptions being based on the appended figures which represent
- Figures 1 to 6: steps of the process for producing a thin film transistor according to the invention
- Figure 7: symbolic representation of a field effect transistor at the end of the first manufacturing step
- Figure 8: symbolic representation of a field effect transistor at the end of the second manufacturing step
- Figures 9 and 10: electrical diagram of an inverter, and its realization in circuit according to the method of the invention
- Figures 11 and 12: electrical diagram of an RS flip-flop and its construction according to the invention
- Figures 13 and 14: electrical diagram of a dynamic shift register and its realization according to the invention
- Figures 15 and 16: electrical diagram of a D scale and its realization according to the invention.

 The presentation of the various stages of the production process will make it possible to better understand, by following, the structure of the predistored thin-film transistor circuits. This process will be explained on the basis of the example of a single thin film transistor, but it is understood that it relates to the production of complex circuits comprising a large number of transistors deposited on a large substrate.

 FIG. 1 represents the first operation necessary to produce a thin film transistor. The substrate 1 is a substrate such as a glass plate, a polymer sheet such as polyvinil chloride or polyimide, a steel sheet or other ceramic substrates whose common point is that they are not monocrystalline, such as silicon or gallium arsenide on which integrated circuits are generally manufactured.

If necessary, this substrate is covered with a layer of buffer silica 2 to make it insulating on the surface or to prevent impurities from the substrate from diffusing into the layers deposited subsequently. This is then covered by a first metal layer, shown in dotted lines, in which an etching, carried out by known methods, makes it possible to isolate the gate 3 from the future field effect transistor.

 On the grid 3 and the insulated face of the substrate is deposited, as shown in FIG. 2, a first insulating layer 4, the transistors produced are therefore Mosfets or Misfets.

Then is deposited a layer 5 of amorphous silicon, unintentionally doped, that is to say having a type of impurity n of the order of 1016 at / cm3 On this layer 5 not intentionally doped is then deposited a layer 6 of silicon heavily doped amorphous, with boron or phosphorus for example, so as to give this layer a p or n type doping. By heavily doped, it is understood that there are of the order of 100 to 10,000 ppm of impurities in the gas deposition phase. These different layers cover the whole of the wafer on which the future integrated circuits are manufactured and the next operation consists in carrying out a mesa etching to delimit, in 7, the individual transistors.

 Layers 5 and 6 constitute the active layer of the field effect transistor, and the following operation represented in FIG. 3 consists in depositing a second metallic layer 8, which is etched either directly above the gate 3 of the future transistor. field effect, either so as to give rise to an overlap between the layer 8 and the gate 3. The two parts of the metallization 8 will constitute the source and drain electrodes of the transistor. The following operation consists in attacking the layer 6 of highly doped amorphous silicon, wherever it is no longer covered by the metal layer 8, or with the photosensitive resin which has made it possible to etch the metal layer 8. The width of this etching defines the length of the transistor channel. When the metallization 8 has been deposited, it has covered the entire surface of the wafer during manufacture: at the same time as the channel is etched above the grid, this metallization is engraved according to the contour 9 which corresponds to the mesa which had been engraved according to the contour 7 of FIG. 2. But one can also engrave according to a contour which will be more interesting during the second step.

 The transistor being thus formed, an insulating layer 10 is deposited on the assembly, as shown in FIG. 4. The transistor of FIG. 4 can constitute the outcome of the first manufacturing step and the wafers supporting networks.

transistors thus protected by an insulating layer 10 can be stored while awaiting the definition of the circuit to be manufactured, according to the user's specifications.

The first phase of the second step is represented in FIG. 5. The transistors chosen, from among the plurality of those which have been produced in the pre-deposited network of transistors, to make an individualized circuit, are masked in an appropriate manner and the surface layer is pierced to take the source and drain contacts on the metallizations 8, respectively at 11 and 12, as well as on the metallisatlons 3 of grids. Then, as shown in FIG. 6, a third metal layer makes it possible to make interconnections 13 and 14 with the said sources and drains, and with the gate 3 already produced originally on the substrate, under the transistor network.
FIG. 7 gives a schematic representation of a transistor as it is at the end of the first step, that is to say in FIG. 4. This transistor has three regions or metallizations of gate, source, and drain , and we will agree for the simplification of the figures which follow to represent this transistor in the form of a rectangle, equivalent to the two metallizations of source and drain, crossed by a line which symbolizes the grid
FIG. 8 represents the same transistor as that of FIG. 7, but after interconnection, that is to say in the state of FIG. 6. In the same way, it will be appropriate to represent this transistor connected to other components on the circuit in the form of a rectangle crossed out by a line, with crosses symbolizing the connection on the source, grid and drain metallizations.

 The following figures, from 9 to 16 represent various known electrical functions, and their realization in the form of a transistor circuit in thin layers pre-deposited.

 Thus, FIG. 9 represents an inverter, of a well known type, constituted by a field effect transistor supplied from a voltage VDD through another transistor whose gate is connected to the drain. In FIG. 10, this inverter is produced by connecting two field effect transistors to each other. A certain number of transistors which are not shown with an interconnection in this figure can be used for other functions according to the wiring which they will receive.

The thin film transistors are preferably aligned, and it is convenient to provide a series of buses which allow on the one hand the inputs and outputs of the complex circuits produced, on the other hand the power supply and the ground, as well as buses which can be used to avoid interconnection crossings for example.

Figure 11 shows an electrical diagram of a scale
Known RS: supplied between a VDD voltage and ground, it has two inputs R (reset) and S (set) and outputs Q and
Q Figure 12 gives the realization according to a circuit of
pre-deposited thin film transistors.

Figure 13 gives the diagram of a register element to
dynamic shift, realized in circuits' of transistors
pre-deposited according to figure 14. This includes a
greater number of transistors than those represented in
Figure 13 because a shift register is a repetitive circuit.

It can be observed in FIG. 14 that, between the transistors in
thin layers pre-deposited, are placed linear metallic interconnection elements, identified at 15. These
interconnection elements facilitate the final interconnection of the
network of pre-deposited transistors, according to the specifications of
the user.

FIG. 14 also makes it possible to note that in a network of transistors in thin layers pre-deposited, it is
possible to group transistors in the same regions
having the same specifications. For example the transistors at
level marked 16 may have a width to length ratio
of grid equal to 100, those of levels 17 and 18 have a ratio
equal to 20, and those of level 19 a ratio equal to 5. We can
again group the transistors according to the power, and
make large transistors in a region of the circuit
surface that dissipate strong power, and in others
regions of large transistors (example w / l = 500)
which will serve as the signal output interface.

Finally figure 15 represents the electric diagram of a
flip-flop D synchronized on a falling edge, and Figure 16
gives the interconnection drawing of the transistors of a circuit
pre-assigned to carry out this rocker D.

The thin film transistor circuit according to the invention
allows circuits to be produced on demand at low cost and
reduced deadlines. It also makes it possible to optimize circuits.

specific and to produce them in small series from
individual transistors of various geometries, deposited on a
single substrate, not monocrystalline, and completed thanks to a level of additional metalilations serving as interconnections.

The invention is more particularly intended for the production of complex but low-cost circuits, and on substrates which are of any material, except, in the case of monocrystalline silicon or of materials of the III-V monocrystalline group, such as l gallium arsenide for example. The invention is intended for the production of bank cards, or more generally for electronic payment, as well as for the production of display devices produced in thin layers. In the latter case, for example for active matrix liquid crystal flat screens, the circuit will be deposited on the periphery of the glass substrate on which the array of electrodes and transistors for controlling the screen is located. The circuit transistors will thus be produced at the same time as the screen control transistors.

Claims (8)

 1. Network of transistors pre-deposited on a substrate, comprising a plurality of individual field effect transistors, each transistor being isolated, or connected to other transistors by a bus, this network being characterized in that  - the substrate (1) is made of a non-monocrystalline material,  - The transistors are of the thin layer type, the layers of semiconductor materials (4, 5, 6) constituting them being amorphous or polycrystalline.  2. Array of transistors according to claim 1, characterized in that the layers of semiconductor materials (4, 5, 6) constituting each transistor are made of silicon.  3. Array of transistors according to claim 1, characterized in that the substrate (1) is made of an amorphous material such as glass or organic polymer, or polyamide.  4. Network of transistors according to claim 1, characterized in that the substrate (1) is made of a polycrystalline material such as metal covered with a layer (2) of silica or silicon nitride, or ceramic.  5. Array of transistors according to claim 1, characterized in that the transistors deposited on the substrate (1) have different geometries, and are grouped according to their dynamic and static performance, in groups having the same length / width of gate ratios.  6. Network of transistors according to claim 5, characterized in that an electronic circuit is personalized from this network of transistors by depositing interconnection metallizations (13, 14) between the transistors chosen as a function of their dynamic performance and static.  7. Method for producing a network of transistors pre-deposited on a substrate, comprising the following steps  a) on an amorphous or polycrystalline substrate (1), having at least one insulating surface layer (2), deposition of a first metallic layer, masking and etching of said layer to produce the grids (3) of field effect transistors ,  b) successive deposits of a first insulating layer (4), made of silica or silicon nitride, then of a first layer of amorphous silicon (5), not intentionally doped, and of a second layer of amorphous silicon (6), heavily doped n or p type  c) etching, in the three previous layers (4, 5, 6), of a mesa (7) to delimit the individual transistors,  d) deposition of a second metallic layer (8), then etching of said layer (8) to define (9) the source and drain contacts of the transistors, and etching directly above the grid (3) of the second layer of amorphous silicon (6) pbur define the channel of the transistors,  e) depositing a second insulating passivation layer (10), made of silica or silicon nitride or polyimide type resin.  8. A method of producing an electronic circuit, from a network of pre-deposited transistors according to claim 7, comprising the following steps  a) masking of the transistors chosen from the plurality of transistors of the network, and etching of the second insulating layer (10) to access (11, 12) the metallizations of the grid in the first metallic layer (3), and of source and drain, in the second metallic layer (8),  b) depositing a third metallic layer, masking and etching of said layer to define the interconnections (13, 14) between transistors.