FR2611940B1 - Systeme de commande d'acces memoire - Google Patents
Systeme de commande d'acces memoireInfo
- Publication number
- FR2611940B1 FR2611940B1 FR888802787A FR8802787A FR2611940B1 FR 2611940 B1 FR2611940 B1 FR 2611940B1 FR 888802787 A FR888802787 A FR 888802787A FR 8802787 A FR8802787 A FR 8802787A FR 2611940 B1 FR2611940 B1 FR 2611940B1
- Authority
- FR
- France
- Prior art keywords
- control system
- access control
- memory access
- memory
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4770187 | 1987-03-04 | ||
JP4770287 | 1987-03-04 | ||
JP4770487 | 1987-03-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2611940A1 FR2611940A1 (fr) | 1988-09-09 |
FR2611940B1 true FR2611940B1 (fr) | 1990-11-16 |
Family
ID=27293052
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR888802787A Expired - Fee Related FR2611940B1 (fr) | 1987-03-04 | 1988-03-04 | Systeme de commande d'acces memoire |
Country Status (2)
Country | Link |
---|---|
US (1) | US4965764A (fr) |
FR (1) | FR2611940B1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0442116A3 (en) * | 1990-02-13 | 1993-03-03 | Hewlett-Packard Company | Pipeline method and apparatus |
CA2106271C (fr) * | 1993-01-11 | 2004-11-30 | Joseph H. Steinmetz | Architecture de memoires premier entre premier sorti a un et a plusieurs etages pour synchroniseurs de transfert de donnees |
US6021471A (en) * | 1994-11-15 | 2000-02-01 | Advanced Micro Devices, Inc. | Multiple level cache control system with address and data pipelines |
GB2491156B (en) * | 2011-05-25 | 2019-08-07 | Advanced Risc Mach Ltd | Processing pipeline control |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3900836A (en) * | 1973-11-30 | 1975-08-19 | Ibm | Interleaved memory control signal handling apparatus using pipelining techniques |
US4317168A (en) * | 1979-11-23 | 1982-02-23 | International Business Machines Corporation | Cache organization enabling concurrent line castout and line fetch transfers with main storage |
US4345309A (en) * | 1980-01-28 | 1982-08-17 | Digital Equipment Corporation | Relating to cached multiprocessor system with pipeline timing |
US4392200A (en) * | 1980-01-28 | 1983-07-05 | Digital Equipment Corporation | Cached multiprocessor system with pipeline timing |
US4546430A (en) * | 1983-07-13 | 1985-10-08 | Sperry Corporation | Control unit busy queuing |
-
1988
- 1988-03-03 US US07/168,888 patent/US4965764A/en not_active Expired - Fee Related
- 1988-03-04 FR FR888802787A patent/FR2611940B1/fr not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US4965764A (en) | 1990-10-23 |
FR2611940A1 (fr) | 1988-09-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
GB2202977B (en) | Computer system having direct memory access | |
GB2193017B (en) | Improved memory access system | |
EP0444601A3 (en) | Memory access control | |
DE3851445D1 (de) | Durch Direktspeicherzugriff gesteuertes System. | |
DE68918714D1 (de) | Spurzugangsregelsystem. | |
DE68925048D1 (de) | Direktspeicherzugriffssteuerung | |
BE894205A (fr) | Systeme de securite a multiples niveaux d'acces | |
DE68927015D1 (de) | Direktspeicherzugriffssteuerung | |
FR2645298B1 (fr) | Controleur d'acces direct en memoire | |
FR2644260B1 (fr) | Dispositif de commande d'acces en memoire pouvant proceder a une commande simple | |
EP0282248A3 (en) | Block access system using cache memory | |
KR970008600B1 (en) | Memory access system | |
EP0409330A3 (en) | Memory access control circuit | |
FR2632102B1 (fr) | Systeme de controle, notamment de controle d'acces a un lieu prive | |
DE69031529D1 (de) | Speichersteuerungssystem | |
DE3855284D1 (de) | Direktspeicherzugriffssteuerung | |
EP0415433A3 (en) | Main memory control system | |
FR2611940B1 (fr) | Systeme de commande d'acces memoire | |
FR2607282B1 (fr) | Dispositif de commande d'acces a une memoire | |
GB2234611B (en) | Memory system | |
DE69224489D1 (de) | Speicherzugriffssteuerung | |
FR2611936B1 (fr) | Systeme de commande de correction d'erreur pour memoire de commande | |
FR2656455B1 (fr) | Circuit de precharge d'un bus de memoire. | |
FR2623355B1 (fr) | Systeme de television a acces controle | |
FR2611938B1 (fr) | Systeme de commande d'acces en memoire |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |