FR2572574B1 - Cellule de memoire de registre a decalage - Google Patents

Cellule de memoire de registre a decalage

Info

Publication number
FR2572574B1
FR2572574B1 FR858515912A FR8515912A FR2572574B1 FR 2572574 B1 FR2572574 B1 FR 2572574B1 FR 858515912 A FR858515912 A FR 858515912A FR 8515912 A FR8515912 A FR 8515912A FR 2572574 B1 FR2572574 B1 FR 2572574B1
Authority
FR
France
Prior art keywords
memory cell
register memory
offset register
offset
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR858515912A
Other languages
English (en)
Other versions
FR2572574A1 (fr
Inventor
Arthur M Cappon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Publication of FR2572574A1 publication Critical patent/FR2572574A1/fr
Application granted granted Critical
Publication of FR2572574B1 publication Critical patent/FR2572574B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G11C19/186—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET using only one transistor per capacitor, e.g. bucket brigade shift register
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018535—Interface arrangements of Schottky barrier type [MESFET]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018535—Interface arrangements of Schottky barrier type [MESFET]
    • H03K19/018542—Interface arrangements of Schottky barrier type [MESFET] with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
FR858515912A 1984-10-29 1985-10-25 Cellule de memoire de registre a decalage Expired - Fee Related FR2572574B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/665,486 US4651333A (en) 1984-10-29 1984-10-29 Shift register memory cell having a transmission gate disposed between an inverter and a level shifter

Publications (2)

Publication Number Publication Date
FR2572574A1 FR2572574A1 (fr) 1986-05-02
FR2572574B1 true FR2572574B1 (fr) 1991-07-19

Family

ID=24670306

Family Applications (1)

Application Number Title Priority Date Filing Date
FR858515912A Expired - Fee Related FR2572574B1 (fr) 1984-10-29 1985-10-25 Cellule de memoire de registre a decalage

Country Status (4)

Country Link
US (1) US4651333A (fr)
JP (1) JPS61107600A (fr)
FR (1) FR2572574B1 (fr)
GB (1) GB2166313B (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4825409A (en) * 1985-05-13 1989-04-25 Wang Laboratories, Inc. NMOS data storage cell for clocked shift register applications
US4965863A (en) * 1987-10-02 1990-10-23 Cray Computer Corporation Gallium arsenide depletion made MESFIT logic cell
US4805139A (en) * 1987-10-22 1989-02-14 Advanced Micro Devices, Inc. Propagating FIFO storage device
US4970413A (en) * 1987-10-28 1990-11-13 Gigabit Logic VBB-feedback threshold compensation
US5008905A (en) * 1988-06-20 1991-04-16 Hughes Aircraft Company Universal shift register employing a matrix of transmission gates
JPH047618A (ja) * 1990-04-24 1992-01-13 Mitsubishi Electric Corp 信号伝送回路
US7920668B2 (en) * 2007-01-05 2011-04-05 Chimei Innolux Corporation Systems for displaying images by utilizing vertical shift register circuit to generate non-overlapped output signals

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4833341B1 (fr) * 1968-06-05 1973-10-13
GB1370120A (en) * 1972-12-06 1974-10-09 Plessey Co Ltd Electrical information storage aray
US4441198A (en) * 1980-06-26 1984-04-03 Matsushita Electric Industrial Co., Ltd. Shift register circuit
JPS57116424A (en) * 1981-01-13 1982-07-20 Toshiba Corp Parallel-to-serial converting circuit
US4394769A (en) * 1981-06-15 1983-07-19 Hughes Aircraft Company Dual modulus counter having non-inverting feedback
US4469962A (en) * 1981-10-26 1984-09-04 Hughes Aircraft Company High-speed MESFET circuits using depletion mode MESFET signal transmission gates
GB2120029B (en) * 1982-05-12 1985-10-23 Philips Electronic Associated Dynamic two-phase circuit arrangement
JPS5992494A (ja) * 1982-11-19 1984-05-28 Hitachi Ltd シフトレジスタ
US4558235A (en) * 1983-08-31 1985-12-10 Texas Instruments Incorporated MESFET logic gate having both DC and AC level shift coupling to the output

Also Published As

Publication number Publication date
FR2572574A1 (fr) 1986-05-02
JPS61107600A (ja) 1986-05-26
JPH0378719B2 (fr) 1991-12-16
GB8526433D0 (en) 1985-11-27
US4651333A (en) 1987-03-17
GB2166313A (en) 1986-04-30
GB2166313B (en) 1989-04-05

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Legal Events

Date Code Title Description
ST Notification of lapse