FR2535129A1 - CIRCUIT-GENERATOR OF PULSES OF CADENCE - Google Patents

Abstract

A. CIRCUIT-GENERATOR OF CADENCE PULSES. B. CIRCUIT CHARACTERIZED BY A FIRST GROUP OF ELEMENTS 11, 13 AND A SECOND GROUP OF ELEMENTS 22, 24, AS WELL AS AN INVERTER I THAT RECEIVES THE START SIGNAL O, THE ELEMENTS 11, 13 ... PROVIDING THE SIGNALS OF OUTPUT V, WILL FROM INPUT SIGNALS O, O. C. THE INVENTION APPLIES TO ALL CIRCUITS REQUIRING A GENERATOR OF POLYPHASE CADENCE SIGNALS.

Description

"Circuits-t-clock pulse generator"

  The present invention relates to a circuit-gener-

  A clock pulse generator in the form of a shift resistor, and more particularly the invention, provides a frequency of clock pulses (ie, to the register).

  pk 7 p d i * e 52 l Polyphase pulse rate, used

  bind poor (: crimander a l Load Transfer Device

  suscepttble dCtrc z-ntrainé, by a timing of

tr Of 1 'n S by: i t.

  The three polyphase rates are designed to provide a load-transfer device provided for controlled timing with a timer. In this case, such clocking is required. cck'sdc p it d disosit? ransfoe'li dc load fleure 1, we have iropusnse

Pese 'J 11' V each having a

  However, these Luso S are applied to the device of the IARGE not to mention parts that are conveniently separated from one-to-one range between two, or successors. In addition to the maximum yield of the transient, it is necessary to

  the width of Il Impulsion and the

  ? 5 terval i e can be modi fied by these lm-

  terns of the outside world without

  proud 1 time + nerval between flanks

  amounts or descendants of each group of two

successive phases V 1, V 2, V 3 "'

  An impulse generator circuit has already been proposed.

  designed to create polyphase rate pulses.

  Sees; this circuit consists of a shift register

as shown in Figure 2.

  In the circuit of FIG. 2, the blocks 1, 2, 3 each have a switching element S and a capacitive element C; these blocks are connected in series

  with each other and the tension obtained at the point of

  switching element S and the capacitor element

  citif C is applied to an inverter I; these blocks are connected in cascade to form a set of stages so that the output of the inverter I of one of them is coupled according to a series connection on the switching element S and the capacitive element In addition, the output of the inverter Io is connected in series connection to the switching element S and the capacitive element C in the block corresponding to V 1 in the first stage and a signal d is applied to the inverter IO 'The switching elements S of the circuit blocks 1, 3, 5 corresponding to the odd order stages are controlled to be blocked or switched on by a first time signal e 1 while the switching elements S of the blocks circuit 2, 4, 6 corresponding

  even-order stages are controlled-to be

  blocked by a second time signal 2.

  In more detail - the switching element

  S consists of an insulated gate-effect field-effect transistor whose gate receives the first or the second time signal 1 or 2. Each of the inverters I0 and I is formed of a solid-state transistor. an E-isolated gate field, and an insulated gate field-effect transistor of depletion type D, whose gate and source are connected to the drain of the field effect transistor E

  field-effect transistor E receives the start-up signal

  O or the junction point voltage of the switching element S and the capacitive element C and the drain of the field effect transistor E is used as a terminal

Release.

  Each of the first and second time signal

  el and e 2 is formed of positive pulses having a period

  of constant cycle; the period during which

  each pulse goes to the high level for which the

  The switching element S is conductive in the signal of

  time does not coincide with the period of each

  pulse at the high level during which the switching element S is made conductive for the time signal e 2 as represented by the timing diagrams of FIG. 3 This means that the time signals 1 and

  e 2 have different phases The start signal 0.

  is formed of positive pulses with a cyclical period

  that sufficiently longer than the cyclical period 't 3 of each of the first and second time signals el and é 2; the period of each positive pulse going to a level> 5 su high and forming the start signal e O contains one of the periods of the pulses forming the first eign: l of time t 1 Without this circuit, the field effect transistor

  ú of the inverter Io is made conductive and so the

  output voltage of the inverter I goes to the ground voltage during the pulse period of the start signal DO 'In the pulse period of the start signal do, if, the first voltage signal e 1 increases Up to the high level starting from the low level, the switching element S of the circuit block 1 of the first stage becomes conductive and the voltage across the capacitive element C in the block 1 goes to the ground level, so that the field effect transistor E constituting the inverter I of the block 1 is blocked and thus the voltage of

  output Vi of block 1 passes to the source of voltage

  4 VDC 'This condition is preserved after the fall

  from the first time signal e 1 to the low level in par-

  both of the high level and the switching element S of the block 1 is blocked until the moment when the first time signal 1 increases again up to the high level starting from the low level Before the first time signal 51 increases again to the high level starting from the low level, if the second time signal e 2 increases to the high level starting from the low level, the switching element S of the block 2 of the second stage becomes conductive and the voltage across the capacitive element C of the block 2 goes to a level substantially equal to the level of the voltage source + VCC, so that the field effect transistor E constituting the inverter I

  of block 2 of the circuit becomes conductive and so the

  output of block 2 goes to ground voltage.

  Then when the first time signal ê 1 increases again to the high level from the low level, the switching element S of the block 1, at the

  during the first stage, becomes a new driver.

  At this time, as the field effect transistor E for-

  the inverter Io is blocked and the output voltage of the inverter I 1 passes at the voltage source + VDC, the voltage across the capacitive element C of the block 1 goes to a level practically equal to the level of the voltage source + VCC; the field effect transistor E forming the inverter I of the block 1 becomes conductive and thus the output voltage V 1 'of the block 1 goes to the ground voltage At the same time, the switching element S of the block 3 of the third At this moment, the switching element S of the block 2 is blocked and the voltage of the capacitive element C of the block 2 remains conserved and takes a level practically equal to the level

  of the voltage source + Vcc although the voltage of output

  In addition, since the field effect transistor E forming the inverter I of the block 2 is conducting and the output voltage of the block 2 goes to the ground voltage, the voltage on the ground the capacitive element C of the block 3 goes to ground level and this is why the field effect transistor E forming the inverter I of the block 3 is blocked, so that the output voltage V of the block 3 to a level almost equal to the level of the voltage source + VCC 'After that, the circuit works continuously from

  the same way as that described above and the

  s Nuns output VI ', V', V o having periods

  respective high level, and which do not

  not between two output signals appearing successively 3, soot? provided by the blocks 1, 3, 5 of the circuit carresponeant respectively to the first, third, r: cin CM, th floors, and constituting ipulsions d = 2 cadeince polyphasees -However, as it follows, I flure 3 the period of each of these pulses V '3 V ,, V is fixed to coincide with the neriode c jmp rse between a rising flank and the flank

  next time of the first time signal e 1 c & i-is

  say the cyclic period Il 3 of the first time signal e ,; so there is no time interval between two

successive signs.

  it is thus desirable to create pulses

  polyphase currents, with a time interval of

  As between two pulses provided by the generator and pulses corre- sponding above, it is then necessary to derive the output voltages VY V, _ -? blocks i, 5 corresponding to the first, third floor This means that the output voltages are connected to the fourth block to give

  pclyphased cadence pulses.

  However, when using such a circuit-

  pulse generator in which the output voltages

  of each fourth block are derived to obtain polyphase rate pulses, to generate N-phase cadence pulses, the generator circuit

  pulses must have {l + 4 (n 1)} blocks and each

  that block consists of the switching element S,

  the capacitive element C and the inverter I; this represents

  feels a significant number of circuit elements In addition,

  under these conditions, as at the same time the width of the

  pulsation of each of the N-phase rate pulses and a time interval between the rising or falling flanks of two successively occurring pulses are determined by the cyclic period 3 of the first time signal, and it is impossible to

  change the pulse width of each of the impulse

  N-phase cadence without changing the interval of

  time separating the rising or falling flanks

  two successive pulses.

  The object of the present invention is to create a cadence pulse generator circuit realized under

  the form of a shift register, remedying the incon-

  discloses known solutions for providing polyphase rate pulses having a time interval between each successive two pulses using a relatively small number of circuit elements. Another object of the invention is to create a shift register cadence pulse generator.

  to provide polyphase rate pulses.

  and the width of the pulses produced as well as the duration of the interval between two successive pulses without changing the time interval between

  respectively the rising flanks or the falling flanks

  two successive pulses, while using

  a relatively simple configuration circuit.

  For this purpose, the invention relates to a circuit

  pulse generator consisting of a series of blocks connected one after the other to have a multi-stage configuration, each of the second blocks corresponding to the even order stages which are not

  not used to provide an exit impulse and se-

  component of a switching element, a capacitance

  citif connected in series on the switching element, and an inverter which receives the voltage of the junction point of the switching element and the capacitive element, and the other second stages corresponding to the odd-order stages used for providing the output pulses and which are composed of a switching element and a capacitive element connected in series on the switching element as well as a NOR gate which receives the voltage of the junction point of the element switching and capacitive element and one of two time signals. The present invention will be described in more detail with the aid of the accompanying drawings, in which: FIG. 1 represents timing diagrams of a

  fire of examples of polyphase clock pulses

  nied by a clock pulse generator circuit

according to the present invention.

  FIG. 2 is a diagram of a pulse generator according to the prior art giving impulses

polyphase cadence.

  FIG. 3 represents timing diagrams of

  polyphase pulses and the time signals, these chrono-

  grams to explain the operation of the circuit-

  pulse generator according to FIG.

  FIG. 4 is a diagram of one embodiment of

  generation of a pulse generator circuit

according to the present invention.

  FIG. 5 shows timing diagrams of polyphase pulses and time signals used to explain the operation of the embodiment.

of Figure 4.

  DESCRIPTION OF A PREFERENTIAL EMBODIMENT

THE INVENTION

  Figure 4 shows an example of a circuit-

  pulse generator of cadence according to the invention A

  Figure 4, the elements and signals which correspond to

  to those of Figure 2 bear the same references.

  In this example, the first blocks 11, 13, and the second blocks 22, 24 are connected alternately in

  series to form a set of floors Each of the first

  first blocks 11, 13 is composed of the switching element

  S and the capacitive element C connected in series with respect to each other and a NOR gate (NAND) N The switching element S is controlled by the first time signal el for to be conductive or blocked; the NOR gate, N receives the voltage of the junction point of the switching element and the capacitive element and the first time signal 9 $ 1 Each of the second blocks 22, 24 is composed of the switching element S and the capacitive element C connected in series with each other and the inverter I The switching element S is controlled by the second time signal e, to be conductive and blocked and the inverter I receives the voltage of the junction point of the switching element S and of the capacitive element C One of the first blocks 11, 13 and one of the second blocks 22, 24 corresponding to two successive stages are connected so that the output of the NOR gate, N or the inverter I is connected to the series connection of the switching element S and the capacitive element C In addition, the output of the inverter Ib is connected to the series connection of the switching element S and the capacitive element C of the first block Il of the first

  floor; the start signal e O is applied to the invert

10.

  In more detail, the switching element

  each of the first and second blocks 11, 22, 13, 24 is formed by an enriched insulated gate field effect transistor whose gate receives the first or the second time signal e 1 or f 2 The inverter i and each of the inverters I of the second block 22, 24 of the even-order stages are formed by an Ef and E-gate transistor with an E enriched gate and a

  field-effect transistor with insulated gate with depletion

  the gate and the source are connected to the drain of the field effect transistor E The gate of the field effect transistor E receives the start signal e O or the ensior X of the junction point of the element of switching <Ut of the capacitive element C and the drain of the transistor to

  efet -lefield E is used as output terminal Cha-

  one of the NOPR gates of the first blocks 11, 12 of

  etanie d Odd order is formed of a couple of transistors

  Eiffet goups with an insulated gate El and E 2, the ports of which are connected to one another and whose drains are read; I and the other, as well as an insulated gate field-effect transistor D whose gate and source are connected to the drains of the field-effect transistors F common branches. The output voltage of the switching point S and the capacitive capacitor C to the pores of the field effect transistor E 2 are as follows:

  first signal of cadence it 'In addition, the point of junc-

  of the drains of the field effect transistors E 1 and

  F is used as the output terminal.

  in the circuit thus produced as shown in FIG. 5, the output voltage A of the inverter IO

  pass or level of the mass during the period of the impulse

  start signal: In the period of the

  start signal pulse &, when the first

  time signal e 1 increases from the low level

  at the high level, the switching element S of the block 11 of the first stage becomes conductive and the voltage VB of the capacitive element C of the block 11 passes at the level of the voltage of the ground, so that the effect transistor of the field E 1 forming the NOR gate, N of the block 1 is blocked at this time, as the field effect transistor E 2 forming the NOR gate, N of the block II becomes conductive due to the high level corresponding to the first time signal el the output voltage Vc of the NOR gate, N of the block Il

  that is, the output voltage V 1 of block 11 is now

  held to take the level of the ground voltage After this, in the period of the pulse of the start signal é, when the first time signal Sl drops to the low level from the high level, the field effect transistor E 2 which forms the NOR gate, N of block 11 of the circuit is blocked, so that the output voltage V 1 of block II increases to the voltage level of the voltage source + Vcc as shown in FIG. the first time signal e 2 increases from the low level to the high level before the first time signal 61 increases again from the low level to the high level, the switching element S of the block 22 of the second stage becomes conductive and that is why the voltage VD on the capacitive element C of the block 22 goes to a level substantially equal to the level of the voltage source

  Vcc as shown in Figure 5, so that the trend

  output voltage VE of inverter I of block 22 goes to

  level of mass as shown in Figure 5.

  When the first time signal 51 increases

  again from the low to the high level, the

  In this case, the switching voltage S of the IL block of the first stage becomes conductive again, as the output voltage VA of the inverter Io has taken a level practically equal to the level of the voltage source + VCC, the voltage VB being the capacitive element C of the block 11 goes to a level substantially equal to the level of the voltage source Vcc and the field effect transistor E 1 which constitutes the NOR gate, N of the block Il becomes conductive, so that the voltage of output V 1 of block 11 goes to ground level At the same time, the switching element S of the circuit 13 of the first stage becomes conductive. At this time, the switching element S of the block 22 of the second stage is blocked and the voltage VD on the capacitive element C of the block 22 is maintained and takes a level substantially equal to the level of the voltage source + Vcc even if the output voltage V 1 of the block II passes to the ground; the output voltage VE of the block 22 is also maintained and takes the level of the mass as shown in FIG. 5 Consequently, the voltage VF on the capacitive element C of the block 13 takes the voltage level of the mass as represented in FIG. FIG. 5 and the field effect transistor E 1 constituting the NOR gate, N of the block.

13 hangs.

  However, since the field effect transistor E 2 which constitutes the NOR gate, N of the block 13 is made conductive by the first time signal e, passing at the jump level, the output voltage VG of the NOR gate, N of the block 13, that is to say the output voltage V 2 of the block 13 is retained and goes to the ground Then, when the first time signal e 1 falls again

  down to the high level, the transi-

  field effect tor E 2 which constitutes the NOR gate, N of the block 13 is blocked and this is why the output voltage V 2 increases to a level almost equal to the level

  the voltage source + Vcc (Figure 5).

  After that, the circuit runs continuously

  in the same way as that described above and the

  output voltage V, V 2 of respective periods t 1 of

  level and which does not overlap but is accompanied by

  the interval of time / e 2 between each of the two successively occurring signals is provided by the blocks 11, 13 corresponding to the respective odd-order stages, giving multiphase clock pulses whose width pulse corresponds to the period Z 1 and the interval (2 between each time two

successive impulses.

  In these conditions, as the period t is

  ie the width of each of the polyphase pulses

  is set to coincide with a separate time interval.

  the period of two successive high level pulses of the first time signal 51 and the time interval c 2 between each time two successive multiphase pulses is set to coincide with the period of each high level pulse of the first time signal.

  el, we can change the width of the pulse t'1 of each

  one of the polyphase pulses and the interval

  time Vr 2 separating two pulse pulses, successive polyphase, by changing the length of each pulse period of high level of the first time signal d without changing the interval <+ t 'between the flanks

I 1 2

  amounts or flanks each time two

successive impulses.

Claims (2)

R E V E N D I C A T IO N S   1) Clock pulse generator circuit giving polyphase rate pulses, circuit having an input terminal receiving an input signal containing a pulse (O%), a first and a second clock terminal tf 'Y 2 ) providing respective first and second time signals (e 1 e 2), each of   first and second time signals being pulse   have a constant cyclic period and the period of each pulse of the first time signal does not coincide with the period of each pulse of the second signal   oe, without overlapping signals, a set of   first circuit blocks (1 l 13) formed each   a J & of a first comniutation element (S) which receives   the time signal (L), a first element   ceit (C) connected in series to the first com-   mutatiotn (S) and a gate (NOR, N) receiving the first t: ignai of time (Taj and the voltage of the junction point   the first switching element (S) and the first element   2, capacitive ment (C) as well as a second set of blocks   Circuit (12 2) each connected between two first   first blocks ('1, S, 3 o) to form a series i ms ms msiuiui nes cnacun c; carrying a second element jie, commutaior; l $ receiving the second time signal (e <9 a capacitive secconce, ment (C) connected to the second element of eif ', utation (S) and an inverter (I) receiving   c tension of the function point of the second element of com-   atation (S) and the second capacitive element (C), the switching element 3 being also connected to the output of the gate (OR, N) of one of the first two blocks -1t, i 5 and its output of the inverter (I) is connected to the switching circuit (S) of the other of the two first blocks (11, 13 circuit characterized in that the   ainai df between is applied to the first element of commu-   Ibi of the first of the first blocks (1, 13) of the   cooked with a pulse period longer than a period   cycle of the first time signal and the output signals   (V 1, V 2) are provided by the gate (NOR, N) in the first blocks (11, 13).   20) pulse generator circuit according to claim 1, characterized in that each of the first and second switching elements (S) is formed of an insulating gate field effect transistor, the gate receiving one of the first and   second time signals (e 2) -   Clock pulse generator circuit according to claim 1, characterized in that the gate,   (NOR, N) consists of a first and a second   field-effect torsion with insulated door (E 1, E 2) to   wherein the drains are connected to each other so that the output and the sources are connected, the gate of the first and second transistors receiving the voltage from the junction point of the first switching element (S) and the first element capacitive (C) and the first signal of time.   Pulsing pulse generator circuit according to claim 1, characterized in that the first   (11) of the first blocks (11, 13) is connected to an invert-   additional signal (I 0) by which it receives the signal input (0).