GB2131244A

GB2131244A - Clock pulse generating circuits

Info

Publication number: GB2131244A
Application number: GB08328101A
Authority: GB
Inventors: Tadakuni Narabu
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 1982-10-21
Filing date: 1983-10-20
Publication date: 1984-06-13
Also published as: US4542301A; FR2535129A1; FR2535129B1; JPS5974724A; NL8303643A; DE3338397A1; GB8328101D0; DE3338397C2; GB2131244B

Description

1 GB 2 131244 A 1

SPECIFICATION

Clock pulse generating circuits This invention relates to clock pulse generating circuits.

Multiphase clock pulses are required for driving a charge transfer device arranged to be driven by so-called electrode-per-bit clocking. In the case of such electrode-per-bit clocking of a charge transfer device, as shown in Figure 1 of the accompanying drawings, multiphase clock pulses V1, V2, V3,... each having a pulse width T1 and supplied to the charge transfer device are required not to overlap, butto have a time interval T2 between each two successive pulses. Moreover, to increase the transfer efficiency to the maximum, it is desirable that the pulse width T1 and the time interval T2 are capable of being varied in response to clock pu ises supplied from externally, withoutvarying the time interval T1 + T2 between the fising edges of failing edges of each successive pulses V1,V2,V3 There has been proposed a pulse generating circuit for producing multiphase clock pulses, and which comprises a shift register, as shown in Figure 2 ofthe accompanying drawings.

In the circuit of Figure 2, circuit blocks 1, 2,3, each include a switching elementS and a capacitive elementC connected in serieswith each other. A voltage obtained atthe connection point betweenthe switching element S andthe capacitive elementofC is supplied to an inverter 1. The circuit blocks 1, 2,3,...

are connected successivelyto form a plurality of 95 stages, such that an output end ofthe inverter 1 in each ofthem is coupled to the series connection ofthe switching element S and the capacitive element C in the next one. Moreover, an output end of an inverter 10 is connected to the series connection ofthe switching 100 element S and the capacitive element C in the circuit blockV1 atthe first stage, and a starting signal 00 is supplied to the inverter 10. The switching elements S in the odd circuit blocks 1, 3,5,... are controlled to be turned on or off by a firsttiming signal 01, while the switching elements S in the even circuit blocks 2,4,6, 45... are controlled to be turned on or off by a second timing signal 02.

In more detail,the switching elementS isformed with an isolated gatefieid effect transistor (FET) ofthe 110 enhancement type. Thefirst orsecondtiming signal 01 or 02 is suppliedtothe gate ofthe FET. Each ofthe inverters 10 and 1 isformed with an insulated gate FET E ofthe enhancement type. and an insulated gate FET D ofthe depletion type with its gate and source connected tothe drain ofthe FETE. The gate ofthe FET E is supplied with thestarting signal 00 orthevoltage obtained atthe connection point between the switching elementS and the capacitive element C, and the drain ofthe field effect transistor E is used as an output 120 terminal.

Each ofthe first and second timing signals 01 and 02 comprises positive pulses having a constant cyclical period T3. The high level periods bywhich the switching element S is turned on in the timing signal 01 are not coincident with the high level periods by which the switching element S is turned on in the timing signal 02, as shown in Figure 3 of the accompanying drawings. That is, the timing signals 01 and 02 differ in phase. The starting signal 00 is formed into positive pulses having a cyclical period sufficiently longerthan the cyclical period T3 of each of the first and second timing signals 01 and 02, and a high level period of each positive pu Ise forming the starting signal 00 includes one of the periods of the pulses forming the firsttiming signal 01.

In this circuit, the FET E in the inverter 10 is made conductive and thereforeth e output voltage of the inverter 10 takes ground level during the period of the pulse of the starting signal 00. Within the period of the pulse of the starting signal 00, when the firsttiming signal 01 rises from the low level to the high level, the switching element S in the circuit block 1 atthe first stage is turned on and the voltage across the capacitive element C in the circuit block 1 takes g rou nd level, so that the FET E of the inverter 1 in the circuit block 1 is turned off, and thereforthe outputvoltage V1'of the circuit block 1 takes the level of a voltage source + Vcc. This condition is maintained, afterthe firsttiming signal 01 falls from the high level to the low level, and the switching element S in the circuit block 1 is turned off, up to an instant at which the first timing signal 01 rises again from the low level to the high level. Before the first timing signal 01 rises again from the low level to the high level, when the second timing signal 02 rises from the low level to the high level, the switching element S in the circuit block 2 at the second stage is turned on and the voltage across the capacitive element C in the circuit block 2 takes a level almost equal to the level of the voltage sou rce + Vcc. Thus the FET E of the inverter 1 in the circuit block 2 is turned on, and therefore the output voltage of the circuit block 2 takes ground level.

Then,when thefirsttiming signal 01 rises again from the low level to the high level, the switching element S in the circuit block 1 at the first step is again tu rned on. On th is occasion, since the FET E forming the inverter 10 has been tu med off and the output voltage of the inverter 10 takes the level of the voltage source +Vcc, the voltage across the capacitive element C in the circuit block 1 takes a level almost equal to the level of the voltage source +Vcc, and therefore the FET E of the inverter 1 in the circuit block 1 is turned on, so thatthe outputvoltage V1'of the circuit block 1 takes ground level. Simultaneouslythe switching element S in the circuit block3 atthethird stage is turned on. On this occasion, the switching element S in the circuit block 2 has been turned off and the voltage across the capacitive element C in the circuit block 2 is maintained to take a level almost equal to the level of the voltage source +Vcc even although the outputvoltage V1'of the circuit block 1 takes ground level. Moreover, sincethe FET E of the inverter 1 in the circuit block 2 is conductive, and the output voltage of the circuit block 2 takes ground level, the voltage across the capacitive element C in the circuit block 3 The drawing(s) originally filed were informal and the print here reproduced is taken from later filed formal drawings.

2 GB 2 131 244 A 2 takes ground level and therefore the FETE forming the inverter I in the circuit block 2 is turned off, so that an output voltage V2'of the circuit block 3 takes a level a] most equal to the level of the voltage source +Vcc.

Afterthat, the circuit operates continuously in the same manner described above, and the pulses of the outputvoltages VV, VX, W,... having respective identical periods of the high level, and which do not overlap, are obtained from the circuit blocks 1, 3,5, atthe first, third, fifth,... stages, respectively, as multiphase clock pulses. However, as apparentfrom Figure3,the period of each of these pulsesis setto coincidewith a period from one rising edgetothe next rising edge of thefirsttiming signal ' Ol,thatis,the cyclical period-r3 of thefirsttiming signal 01, and thereforethere is no time interval between each two successive pulses.

Accordingly, if it is intended to obtain multiphase clock pulses having a predetermined time interval between each successive two of them from the pulse 85 generating circuit described above, it is necessaryto derive the output voltages VV, W,... fromthecircuit blocks,1,5,... atthe first, fifth,... stages. That is, the output voltages are derived from every fourth circuit blockto produce the multiphase clock pulses.

However,whena pulse generating circuit in which the output voltages from every fourth circuit block are derived to produce multiphase clock pulses is used for generating n phase clock pulses, the pulse generating circuit must contain (1 + 4 (n-l)) circuit blocks each comprising the switching element S, capacitive element C and inverter 1, and consequently it contains a very large nu mber of circuit elements. Moreover, in this case, since both a pulse width of each of the n phase clock pulses and a time interval between rising 100 edges orfal ling edges of two successive pu Ises are determined by the cyclical period T3 of the firsttiming signal 01, it is im possible to vary the pulse width of each of the n phase clock pulses without varying the time interval between the rising edges or failing edges 105 of two successive pulses.

According to the present invention there is provided a clock pulse generating circuit for producing multiphase clock pu Ises, the circuit comprising:

an input terminal to be supplied with an input signal 110 containing a pulse; first and second clocking terminaisfor supplying first and second timing signals, respectively, each of said first and second timing signals comprising pulses having a constant cyclical period, the period of each pulse of said firsttiming signal neither being coincidentwith nor overlapping the period of any pulse of said secondtiming signal; a pluralityof firstcircuit blocks each comprising a firstswitching elementto be supplied with saidfirst timing signal, a first capacitive elementcoupled in series with said firstswitching element, and a NOR gate circuit connected to besuppliedwith said first timing signal and a voltage obtained from the connection point between said first switching element 125 and said first capacitive element; and a plurality of second circuit blocks connected between and so as to alternate with said first circuit blocks to form a series multistage configuration, and each comprising a second switching elementto be supplied with said second timing signal, a second capacitive element coupled to said second switching element, and an inverter connected to be supplied with a voltage obtained atthe connection point between said second switching element and said second capacitive element, said second switching element also being connectedtothe outputend of the NOR gate circuit in one of two successive ones of said first circuit blocks, and the output end of the inverter being connected to the first switching element in the other of said successive two of saidfirst circuit blocks; wherein said input signal is supplied to the first switching element in the first one of said first circuit blocks with a pulse period greaterthan one cyclical period of said first timing signal, and output signals are derived from the NOR gate circuits in said first circuit blocks.

The invention will now be described byway of examplewith reference to the accompanying drawings, throughout which like partsare referredto belike references, and in which:

Figure 1 shows waveforms of examples of multiphase clock pulses required to be produced by a clock pulse generating circuit according to the invention; Figure 2 is a circuit diagram showing a previously proposed pulse generating circuitfor producing multiphase clock pulses; Figure 3 shows waveforms of multiphase pulses and timing signals used for explaining the operation of the pulse generating circuitof Figure 2; Figure 4 is a circuit diagram showing an embodiment of clock pulse generating circuit according to the invention; and Figure 5 showswaveforms of multiphase pulses andtiming signals used for explainingthe operation of the embodiment of Figure 4.

Figure 4 shows an embodiment of clock pulse generating circuit according to the invention. First circuit blocks 11, 13---.. and second circuit blocks 22, 24,... are connected alternately in series to form a plurality of stages. Each of the f irst circuit blocks 11, 13,... comprises a switching element S and a capacitive element C connected in series with each other, and a NOR gate circuit N. The switching element S therein is controlled bythefirsttiming signal 01 to beturned on or off and the NOR gate circuit N is supplied with the voltage obtained atthe connection point between the switching element S and the capacitive element C, and thefirsttiming signal 01.

Each of the second circuit blocks 22,24,... comprises a switching element S and a capacitive element C connected in series with each other and an inverter t. The switching element S therein is controlled by the second timing signal 02 to be tu rned on or off, and the inverter 1 is supplied with the voltage obtained atthe connection point between the switching, element S and the capacitive element C. One of the first circuit blocks11,13,... and one of the second circuit blocks 22,24,. .. at two successive stages are connected such that the output of the NOR gate circuit N orthe inverter] is connected to the series connection of the switching element S andthe capacitive element C. Moreover, the inverter 10 is provided with its output connected to the series connection of the switching element Sand the capacitive element C in the first 3 GB 2 131 244 A 3 circuitblockll at the first stage, and the starting signal 00 is supplied to the inverter 10.

In more detail, the switching element Sin each of the first and second circuit blocks 1, 22,13,24,... is 5 formed with an insulated gate FETof the enhancementtypeto the gate of which the first orsecond timing signal 01 or 02 is supplied. Each of the inverters 10 and the inverters 1 in the second circuit blocks 22,24,... atthe even stages isformed with an insulated gate FET E of the enhancement type and an insulated gate FET D of the depletion type with its gate and source connected to the drain of the FET E. The gate of the FET E is supplied with the starting signal 00 orthe voltage obtained atthe connection between the switching element S and the capacitive element C, and the drain of the FET E is used as an outputterminal. Each of the NOR gate circuits in the first circuit blocks 11, 12,... atthe odd stages is formed with a pair of insulated gate FETs Ell and E2 with their sources connected to each other and their drains connected to 85 each other, and an insulated gate FET D with its gate and source connected to the drains of the FETs E1 and E2 connected in common. The gate of the FET Ell is su pplied with the voltage obtained at the connection point between the switching element S a nd the capacitive element C, and the gate of the FET E2 is supplied with the first timing sig nal 01. Moreover, the connection point between the drains of the FETs Ell and E2 is used as an outputterminal.

In this circuit, as shown in Figure 5, an output 95 voltage VA of the inverter 10 takes ground level during the period of the pulse of the starting signal 00. Within the period of the pulse of the starting signal 00, when the first timing signal 01 risesfromthelowleveltothe high level, the switching element S in the circuit block 11 atthe first stage is turned on and a voltage V13 across the capacitive element C in the circuit block 11 takes ground level, sothatthe FETE1 formingtheNOR gatecircuitNinthecircuitblockll isturned off. At this time, since the FET E2 forming the NOR gate circuit N inthecircuitblockll is turned on bythe high level taken by the firsttiming signal 01, an output voltage VC of the NOR gate circuit N in the circuit block 1 1,that is, an outputvoltage V1 of the circuit block 11 is maintained at g round level. After that, within the 110 period of the pulse of the starting signal 00, when the firsttiming signal 01 fails from the high level to the low level, the FET F2 forming the NOR gate circuit N in thecircuitblock11 is turned off and therefore the output voltage V1 of the circuit block 11 rises to the level of the voltage sou rce +Vcc, as shown in Figu re 5.

Then, the firsttiming sig nal 02 rises from the low level tothe high level before the first timing signal 01 again risesfromthe low level tothe high level,the switching elementS inthe circuitblock22 atthe second stage is 120 turned on andtherefore avoltageVID acrossthe capacitive element C inthe circuit block22takes a level almost equal to the level of the voltage source +Vcc, as shown in Figure 5, so that an outputvoltage VE of the inverter 1 in the circuit block 22 takes ground 125 level, as shown in Figure 5.

When the firsttiming signal 01 risesfromthelow level to the high level, the switching element Sin the circuit block 11 at the first stage is turned on. On this occasion, since the output voltage VA of the inverter 10130 has taken a level amost equal to the level of the voltage source +Vcc, the voltage V13 across the capacitive element C in the circuit block 11 takes a level almost equal to the level of the voltage source '+Vcc and the FET E1 forming the NOR gate circuit N in the circuit block 11 takes ground level. Simultaneously,the switching element S in the circuit 13 atthethird stage isturned on. On this occasion,the switching element S in the circuit block22 atthe second stage has been turned off, and a voltage V13 acrossthe capacitive element C in the circuit block 22 is maintained at a level almost equal to the level of the voltage source +Vcc even although the output voltage V1 of the circuit block 11 takes ground level, so thatthe outputvoltage VE of the circuit block 22 is also maintained at ground level, as shown in Figure 5. Accordingly, a voltage VF acrossthe capacitive element C in the circuit block 13 takes ground level, as shown in Figure 5, and the FET E1 forming the NOR gate circuit N in the circuit block 13 isturned off. However, sincethe FET E2 forming the NOR gate circuit N in the circuit block 13 is turned on bythefirst timing signal 01 taking the high level, an output voltage VG of the NOR gate circuit N in the circuit block 13, that is, an outputvoltage V2 of the circuit block 13 is maintained at ground level. Then, when the first timing signal 01 fails again to the low level from the high level, the FET E2 forming the NOR gate circuit N in the circuit block 13 isturned off and therefore the output voltage V2 rises to a level almost equal to the level of the voltage source +Vcc, as shown in Figure 5.

Afterthat, the circuit operates continuously in the same manner as mentioned above and the output voltage V1, V2,... having respective identical periods T1 of the high level, which do not overlap but have a time interval T2 between each successive two of them, are obtained from the circuit blocks 11, 13,... at the odd stages, respectively, as the required multiphase clock pulses.

Claims

Since the period T2, that is, the pulse width of each of these multiphase pulses is setto coincide with a time interval between each successive two pulse periods of the high level of the firsttiming signal 01, and the time interval T2 between each two successive multiphase pulses is setto coincide with each pulse period of the high level of the firsttiming signal 01, the pulse width T1 of each of the multiphase pulses, and the time interval T2 between each successive two of the produced multiphase clock pulses can be varied by varying the length of each pulse period of the high level of thefirsttiming signal 01, withoutthereby varying the time interval T1 + T2 between rising edges orfalling edges of each two successive pulses. CLAIMS

1. A clock pulse generating circuitfor producing multiphase clock pulses, the circuit comprising:

an input terminal to be supplied with an input signal containing a pulse; first and second clocking terminals for supplying firstand second timing signals, respectively, each of said first and second timing signals comprising pulses having a constant cyclical period, the period of each pulse of said firsttiming signal neither being coincident with nor overlapping the period of any pulse of said second timing signal; 4 a plurality of first circuit blocks each comprising a first switching element to be supplied with said first timing signal, a first capacitive element coupled in series with said first switching element, and a NOR gate circuit connected to be supplied with said first timing signal and a voltage obtained from the connection point between said first switching element and said first capacitive element; and a plurality of second circuit blocks connected between and so as to alternate with said first circuit blocks to form a series multistage configuration, and each comprising a second switching elementto be supplied with said second timing signal, a second capacitive element coupled to said second switching element, and an inverter connected to be supplied with a voltage obtained atthe connection point between said second switching element and said second capacitive element, said second switching elementalso being connected to the output end of the NOR gate circuit in one of two successive ones of said first circuit blocks, and the output end of the inverter being connected to the first switching element in the other of said successive two of said first circuit blocks; wherein said input signal is supplied to the first switching element in the first one of said first circuit blocks with a pulse period greaterthan one cyclical period of said firsttiming signal, and output signals are derived from the NOR gate circuits in said first circuit blocks.

2. A clock pulse generating circuit according to claim 1 wherein each of said first and second switching elements is formed with an insulated gate field effect tra nsisto r of the enhancement type with its gate being supplied with one of said first and second timing signal.

3. A clock pulse generating circuit according to claim 1 wherein said NOR gate circuit is formed with first and second insulated gate field effect transistors of the enhancement type with their drains connected to each other to make the output of said NOR circuit, and their sources connected to each other, and the gates of said first and second transistors are supplied with the voltage obtained at the connection point between said first switching element and said first capacitive element, and said first timing signal, respectively.

4. A clock pulse generating circuit according to claim 1 wherein said first one of said first circuit blocks is connected to an additional inverter through which said input signal is supplied thereto.

5. A clock pulse generating circuit substantially as hereinbefore described with reference to Figure 4 of the accompanying drawings.

Printed for Her Majesty's Stationery Office by The Tweeddale Press Ltd., Berwick-upon-Tweed, 1984. Published atthe Patent Office, 25 Southampton Buildings, London WC2A 1 AY, from which copies may beobtained.

GB 2 131 244 A 4 1 1 A j