FR2531791B1 - Circuit d'adressage pour equipement de test automatique - Google Patents

Circuit d'adressage pour equipement de test automatique

Info

Publication number
FR2531791B1
FR2531791B1 FR838313140A FR8313140A FR2531791B1 FR 2531791 B1 FR2531791 B1 FR 2531791B1 FR 838313140 A FR838313140 A FR 838313140A FR 8313140 A FR8313140 A FR 8313140A FR 2531791 B1 FR2531791 B1 FR 2531791B1
Authority
FR
France
Prior art keywords
test equipment
automatic test
addressing circuit
addressing
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR838313140A
Other languages
English (en)
Other versions
FR2531791A1 (fr
Inventor
Robert L Hickling
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of FR2531791A1 publication Critical patent/FR2531791A1/fr
Application granted granted Critical
Publication of FR2531791B1 publication Critical patent/FR2531791B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31907—Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G06F12/0661—Configuration or reconfiguration with centralised address assignment and decentralised selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
FR838313140A 1982-08-16 1983-08-10 Circuit d'adressage pour equipement de test automatique Expired FR2531791B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/408,404 US4480315A (en) 1982-08-16 1982-08-16 Dynamically controllable addressing in automatic test equipment

Publications (2)

Publication Number Publication Date
FR2531791A1 FR2531791A1 (fr) 1984-02-17
FR2531791B1 true FR2531791B1 (fr) 1989-04-28

Family

ID=23616154

Family Applications (1)

Application Number Title Priority Date Filing Date
FR838313140A Expired FR2531791B1 (fr) 1982-08-16 1983-08-10 Circuit d'adressage pour equipement de test automatique

Country Status (5)

Country Link
US (1) US4480315A (fr)
JP (1) JPS5952773A (fr)
DE (1) DE3328996A1 (fr)
FR (1) FR2531791B1 (fr)
GB (1) GB2125594B (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6145347A (ja) * 1984-08-10 1986-03-05 Nec Corp マイクロコンピユ−タ
GB8432302D0 (en) * 1984-12-20 1985-01-30 Conway R Installation for visually displaying pre-determined messages
US4752928A (en) * 1985-05-06 1988-06-21 Tektronix, Inc. Transaction analyzer
US4856001A (en) * 1987-05-29 1989-08-08 Zehntel, Inc. Digital in-circuit tester having channel-memory earse-preventer
US4862067A (en) * 1987-06-24 1989-08-29 Schlumberger Technologies, Inc. Method and apparatus for in-circuit testing of electronic devices
US5321701A (en) * 1990-12-06 1994-06-14 Teradyne, Inc. Method and apparatus for a minimal memory in-circuit digital tester
JP2716284B2 (ja) * 1991-06-07 1998-02-18 日本電気アイシーマイコンシステム株式会社 半導体集積回路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3623013A (en) * 1969-08-13 1971-11-23 Burroughs Corp Data processing network and improved terminal
US3784910A (en) * 1972-07-13 1974-01-08 Teradyne Inc Sequential addressing network testing system
GB1423126A (en) * 1973-11-07 1976-01-28 Bendix Corp Adaptive addressing systems for airbourne data systems
US4373181A (en) * 1980-07-30 1983-02-08 Chisholm Douglas R Dynamic device address assignment mechanism for a data processing system

Also Published As

Publication number Publication date
JPS5952773A (ja) 1984-03-27
FR2531791A1 (fr) 1984-02-17
US4480315A (en) 1984-10-30
GB8321906D0 (en) 1983-09-14
DE3328996A1 (de) 1984-02-16
GB2125594A (en) 1984-03-07
GB2125594B (en) 1986-03-12

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Legal Events

Date Code Title Description
ST Notification of lapse