FR2509558A1 - MULTI-TUBE COLOR TELEVISION CAMERA - Google Patents

Abstract

A. MULTI-TUBE COLOR TELEVISION CAMERA. B. CAMERA COMPRISING A PHASE ADJUSTMENT CIRCUIT 62, 66, COUNTERS 67, 77, 64, 69A, 69B, INVERTERS 65, 76, 78 AND LOGIC GATES 79, 80. C. THE INVENTION APPLIES TO COLOR TELEVISION CAMERAS FOR COINCIDENCE ADJUSTMENT OF FUNDAMENTAL IMAGES.

Description

Tube color television camera

multiple ".

  The present invention relates to a multi-tube color television camera and in particular a multi-tube color television camera.

  with a chock compensation system.

  In a multi-tube color television camera, having a set of means for making

  of images for example a triple tube camera that is to say

  say a camera with three camera tubes respectively giving the signals of the red, green and blue color images or a two-tube camera using two camera tubes to give the signals of

  luminance and chrominance, extra

  complex images to ensure the image registration of the different camera tubes.

  the intensity of the deflection currents of the beam of

  align the center positions of the output images of the respective camera or image tubes

  However, it is difficult to correct errors in

  ge (coincidence errors) generated by differences specific to each camera tube such as, for example, image rotation (rotation of the image with respect to the axis) to distortions or deformations (trapezoidal distortions, distortions pillow or similar) at the edge of the screen as well as errors in

  dimension of the image, linearity of scanning, of dis-

  tilt twists etc Generally to compensate

  such coincidence errors, we have a com-

  complex control which generates different control signals to adjust the deflection currents of the beams of the respective camera tubes. Furthermore, since the factors which cause the stall errors are strongly nested, the setting of the stall in one

  point of the screen may result in a mistake in

  to another point on the screen It is thus difficult to

  to ensure even stalling throughout the surface

of the screen.

  The present invention aims to create

  a multi-tube color television camera, re-

  mediating the disadvantages of known solutions,

  an automatic adjustment of the wedging giving a uniform wedging throughout the surface of the screen, and whose calibration error data corresponding to each horizontal scan line of the entire surface of the image are obtained from a reduced number of calibration error or coincidence data detected by even fewer sampling operations

  in a relatively short period of time.

  It is also an object of the invention to provide a camera having an automatic pitch control system which detects extremely accurate error data without being influenced by the frequency characteristics of the beam deflection system, including coincidence compensation or This is ensured by a simplified deflection drive system with a reduction in the degree of error compensation and faster error detection to facilitate

  convergence of data towards the goal.

  For this purpose, the invention relates to a multi-tube color television camera with a system

  automatic adjustment or compensation of the

  the camera having a first camera tube giving a first video signal of a test table for setting the calibration, at least a second camera tube giving a second

  video signal from the same test board, a means of

  error signal sampling to sample stall errors between the first and the second signal

  video compared to a set of image areas, distributed

  in segments, a calibration error generator, by

  interpolation to generate calibration error signals

  between the calibration errors sampled, by

  terpolation at least in the vertical direction of

  segmented image areas, a means for generating a

  calibration compensation signal based on the interpolated calibration errors thus obtained and the sampling errors sampled, and means providing the calibration compensation signal to a control circuit

  deflection of the second camera tube for

  sea the errors of wedging between the first and the second

video signal.

  The present invention will be described in more detail with the aid of the accompanying drawings, in which:

  FIG. 1 is a schematic plan view.

  than segmented image areas, used to explain the

  a calibration compensation system according to a mode of

implementation of the invention.

  Fig. 2 is a diagram of the memory areas for storing the error data relating to each segmented image area according to Fig. 1;

  FIG. 3 is a diagram for explaining

  plotting the interpolation of data recorded in adjacent areas in the vertical direction of the

  memory shown in Figure 2.

  FIG. 4 is a diagram showing a memory for storing the compensation data

  calibration obtained by interpolation.

  FIG. 5 is a block diagram of a -example

  A full detection circuit provides the error data for the horizontal direction and the vertical direction.

  Figure 6 is a block diagram of an example

  full circuit to realize the compensation of the setting,

  this circuit can be part of the circuit of Figure 5.

  FIGS. 7A-7Q are timing diagrams for explaining the operation of the circuit of the

figure 5.

  FIGS. 8A, 8B, combined form a block diagram of a control circuit according to an embodiment of the invention for controlling the detection,

  storage, interpolation and cal-

  error data in the vertical direction and

the horizontal direction.

  Figure 9 is a flow chart of the operation.

  Figure 8 is a schematic diagram showing the timing compensation of the circuit of FIGS. 8A and 8B.

  combination of figures l OA, OB, l OC -

  FIGS. 10A, 1B and 1C combined

  represent a flowchart giving the details of the sub-

  data input / output program of Figure 9.

  * Figure 11 is a graph showing the

  convergence of data towards a goal during the detection

error data.

  FIG. 12 is a flowchart giving the details of the interpolation routine according to FIG.

figure 9.

  Figure 13 is a graph showing the vertical data, this graph being used to

  explain the interpolation process.

  Fig. 14 is a flow chart for expansion interpolation of the upper part of

the image area.

  Figure 15 is a graph of

  polation by dilation of the lower end of the image area.

  Figure 16 is a flowchart of the

  dilation terpolation of the lower end of

the image area.

  FIG. 17 is a block diagram of an address generator generating the addresses of the RAM memories forming part of the circuit of FIGS. 8A and 8B.

  Figures 18 A-18 J and Figures 19 A-

  19 M are chronograms used to explain the f-

  the address generator of Figure 17.

  Figure 20 is a block diagram of a

  vertical deflection of a television camera

  multi-tube color cable to which the invention is applied.

  Fig. 21 is a block diagram of a system

  horizontal deflection of a television camera

multi-tube color.

  DETAILED DESCRIPTION OF DIFFERENT EMBODIMENTS

PREFERENTIAL

  An automatic stall system according to an embodiment of the present invention will be described hereinafter in a general manner with reference to Fig. 1; in this figure, there is shown the image area of a three-tube color television camera, this area

  being divided by 7 at a time in the horizon drecton

  tale and in the vertical direction, which gives a total of 49 so-called segmented image areas In the following,

  we suppose that we want to make the calibration

  that is to say the coincidence between the red signal provided by the red tube and the blue signal provided by the blue tube with reference to the camera tubes to obtain the green signal During calibration, a test table is reproduced with a "+" mark in the center of each

  segmented area according to Figure 1 It is also pos-

  sible to incorporate in the television camera a slide-like film, with the diagram of the test chart of Figure 1; this film can be placed in the optical path of the camera tubes when performing

stalling.

  For each segmented image area, the calibration error data which represents the errors V (calibration errors in the vertical direction) and the

  H errors (calibration errors in the horizontal direction

  tale) red and blue tubes are detected with reference to the green tube as will be described later The calibration error data is transformed into a numerical data and is temporarily stored in a corresponding element of a memory area shown in FIG. 2 This memory area has addresses in matrix-on 7 rows and 8 columns Each memory element thus defined, contains the error data of calibration representing respectively the error H and the error

  V of a corresponding segmented image area The last

  The column of the elements of the memory area shown in FIG. 2, which bears the reference "7", does not correspond to any of the segmented image areas (7 × 7) of the image area and is used to record the given

  errors in the calibration of the H and V errors during

  horizontal erasure interval H-BLK The erasing data

  In this case, the average value of the DS datum and the datum D 4 can be calculated to obtain the maximum value of the horizontal erase interval. data D 15 recorded in

  the memory element identified by "15" By this introductory

  calibration error data for the horizontal erase interval, a correction less

  brutal horizontal and vertical deflection currents

  down. It is also possible to provide a memory for storing data of average value of the vertical erase interval as well as for

  the horizontal erasure interval The data exchange

  tilings, respectively recorded in adjacent elements in the vertical direction in the memory area shown in Figure 2 are interpolated to obtain the error data of each scan line by numerical approximation As for the sampled data, recorded in the elements from the memory area adjacent to each other in the direction

  horizontally, the interpolation can be done by

  which means of signal processing in the form of

  logic, using a low-pass filter, and so this interpolation does not require signal processing

  numeric when this solution is chosen.

  When the number of segments in which the image area is distributed, is divided to extract the

  data corresponding to the calibration error, and that this name

  If the number of segmented image areas is too large, the detection and processing of the calibration error data are long operations. the embodiment of the invention now described, the image zone is divided into a 7 × 7 matrix of zones

  This is why in the case of the sys-

  NTSC, thirty-six lines are assigned to each image area segmented in the vertical direction. Then as shown in Figure 3, an approximation is made

  linear of thirty-five elements of data interpolation

  There is a difference between the vertically adjacent parts of the sampled data (for example D 16 and D 24). In this case, the data of the calibration error, thus detected, can be considered as corresponding to errors in the media of the d-zones. segmented Although H and V errors are interpolated for all data sampled in the vertical direction, the

  time required for the approximation calculation is

  shorter than the time required for detection

  This is why, according to the pre-

  invention, one obtains error data from

  with high accuracy and in a very short time

  thanks to a relatively small number of

  pling. In this way, the data of the calibration errors corresponding respectively to all the scan lines of the entire image surface are prepared in

  interpolating in the vertical direction

  Then, the calibration error data is temporarily stored in the memory area having memory addresses.

  such as those shown in Figure 4.

  This memory serves to record the data of

  thought has 256 rows and 8 columns of addresses

  matrix (8 x 256 matrix) Each memory address

  register two pieces of error data for them

respective H and V errors.

  Then, the calibration compensation data

  stored in the memory area is read in synchro-

  The horizontal and vertical deflection currents are adjusted according to the correction signal thus obtained. As a result, the correction of the image size of each pick-up tube is effected. views, the linearity of the deflection as well as

  the tilt distortion and the oerrection of the dis-

  trapezoidal torsion, pincushion distortion or

  can be realized simultaneously during the course of

  calibration compensation We see that the description

  previous paragraph relates generally to a procedure

  making it easy to ensure automatic detection

  and compensation for calibration errors.

  FIG. 5 shows a television camera with automatic adjustment of the wedging performed according to one embodiment of the invention; this camera comprises three camera tubes 2, 3, 4 giving color signals corresponding to the red and green components of the image observed. The deflection system of the camera is pre-set so that the phase of the signal of output G 'of the green tube 4 used conmmne reference for

  the calibration compensation can be advanced by

  port to the phases of the output signals of the red tube 3 and the blue tube 2 by a difference equal to (H + T) (H being the horizontal scanning period and corresponding T

about 150 ns).

  Figure 7A shows a hatched image in one of the segmented image areas of the table.

  test of Figure I; the output signal corres-

  The output signal G 'of the tube 4 is delayed by (H + T) by a line of delay 5 of the green tube 4 in the horizontal balancing line Ln. 1 E and a delay line 7 of T to output a main signal GO (FIG. 7 F). In the absence of detection of a stall error, the main signal GO (FIG. 7 F) is in phase in FIG. the horizontal direction

  and in the vertical direction with the output signals

  R and B (Fig. 70) of the camera tubes 3 and 2. The output signal of the delay line 7, T is further delayed by the delay line T, 8 and the delayed output signal, resulting in DLG '(FIG. 7C) is provided to a subtracter 9 to be subtracted from the other input signal which is the output signal of the delay line 5 giving a delay of 1H An EDG step signal representing the edge horizontal of the image 10 is generated as the output signal of the subtractor 9

  (Figure 7 D) This EDG step signal has a positive polarity

  for the video signal leading edge and a negative polarity for the video signal trailing edge The EDG signal is applied by a contact H of the inverting switch 11 to a multiplier 12 as well as to a side detector 13 The side detector 13 generates a sampling gate signal SG (FIG. 7 E) corresponding to

  the instant of the EDG signal or flank signal (FIG. 7D).

  A selector switch 14 selects the output signal RO or BO from the respective red tube 3 or blue tube 2 and supplies the selected output signal RC / Bo (FIG. 7G) to a subtractor 15. The subtractor gives the difference signal between the signal RQ / BO (FIG. 7G) and the main signal GO (FIG. 7F) The output signal REG (FIG. 7H) of the subtractor 15 is a position error signal which represents the phase advance hi of the output signal of the red tube or the blue tube with respect to the output signal of the green tube and this signal corresponds to the horizontal error The signal

  error position REG is applied to another

  multiplier 12 for Atre multiplied by the latter by the EDG edge signal. The result of the multiplication performed by the multiplier 12 is

  an error signal ER (FIG. 7 I) representing the ampli-

  study and direction of the horizontal stall error; this signal is applied to a sampling and holding circuit 16 The sampling and holding circuit 16 samples the error signal ER during the duration of the sampling gate signal SG II (FIG. 7 E) and gives a continuous sampling and holding voltage SH (FIG. 7J) corresponding to the level and polarity of the error signal ER A capacitor 17 connected to the output of the sampling and holding circuit 16 acts as a holding capacitor. The sampling gate signal SG is supplied to the sampling and holding circuit 16 by the AND gate 18 The AND gate 18 is opened by a

  GE sample gate pulse that is fed to him

  denies by the terminal 19 through a buffer circuit 20 The

  GE sample gate signal is generated in

  correspondance with each of the image zones, segmented

shown in Figure 1.

  When the phases of the output signals RO and B O of the red tube 3 and the blue tube 2 are delayed with respect to the phase of the main signal Go of the tube

  green 4 with a value equal to A 1 as shown

  In FIG. 7G, the sampling and holding voltage SH shown in FIG. 7J is of positive polarity and its level corresponds to the value A 1. Moreover, if the output signals of the red and blue tubes are in in advance of the main signal of an advance equal to A 2 (FIG. 7 K), the polarity of the

  position error signal REG (Figure 7 L) is the oppo-

  This is why the respective ER error signal which represents the magnitude and direction of the stall error has a negative polarity as shown in Figure 7 M; voltage

  sampling and holding, SH, resultant, negatively

  ve has a level corresponding to A 2 as shown

felt in Figure 7 N.

  The output signal of the sample circuit

  The calibration and hold 16 is applied as a calibration error data to a signal processing circuit ib Ai which, as subsequently described, prepares the compensation data. According to the compensation data thus prepared, the beam deflectors 22 and 23 corresponding blue tube 2 and red tube 3 are controlled, so that through this control operation, the R Ig Bo output signals of the red and blue tubes are phased with the main signal Go of the green tube 4 as is shown in Fig. 70 Since the output signal level of the green tube 4 is not equal to that of the output signal of the red tube 3 or the blue tube 2, the level of the position error signal REG may not cancel out as shown in Figure 7 P even though the images of all the tubes coincide correctly However as

  the error signal ER of the multiplier 12 takes into

  in the opposite direction for the leading edge and the trailing edge of the video signal as shown in Fig. 7 Q, the level of the sampling signal

and holding SH is canceled.

  As shown in FIG. 6, the part of the signal processing circuit which supplies the compensation data generally consists of a comparator 26, a up / down counter (U / D) 27 and a converter

  Digital / Analog (D / A) 28 Sample Voltage-

  and holding SH of the sampling and holding circuit 16 is applied to comparator 26 which compares

  the sampling and holding voltage SH at the potential

  ground (O V) so as to detect the polarity of the stall error data which indicates either that the output image of the red or blue tube is to the right or to the left

  of the image provided by the green tube A signal of comparison

  Reason COM supplied by the comparator 26 and which goes high or low depending on the polarity of the calibration error data is applied to the U / D input of the up / down counter 27 In response to each vertical synchronization signal VD applied as clock pulse CK to counter / down counter 27, the latter counts or counts according to whether there is a high level or a level

  low for the comparison signal COM supplied by the com-

  In practice and as will be detailed later on

  subsequently, the up / down counter 27 does not change the count data in units of 1 bit for each period

vertical scanning -

  The output signal of the up / down counter 27 is applied to the digital to analog converter

  D / A 28 which converts it into a control voltage.

  This control voltage is then supplied as a DC bias voltage to an adder 29 which adds it to the SAW sawtooth signal provided appropriately to cause the electron beam to deflect into the respective camera tube. output signal of the adder 29 is provided by a drive amplifier 30 which gives a deflection current to the deflection coil 31 of the red tube 3 or the blue tube 2

  connected to the output of the drive amplifier 30.

  If the sampling and hand voltage

  SH given as the output signal of error data.

  the calibration circuit of the sampling and main-

  16 is of positive polarity, the signal of comparison

  its com of comparator 26 goes to a high level and

  the counting state of the up / down counter 27 is decre-

  In response to this operation, the flow of

  bending which passes into the deflection coil 31 decreases, and the horizontal scanning position of the red tube or the blue tube is shifted to the left so as to reduce

  at least the error of the image output signal with respect to

  to the image output signal of the green tube.

  their if the sampling voltage and holding SH

  is of negative polarity, the count value of the

  The up / down converter 27 is incremented and the horizontal sweeping position of the red tube or blue tube is shifted to the right. This is why the output image of the red tube or the blue tube which has been shifted to the left relative to at the output image of the green tube, is shifted to the right to minimize the error

cushioning.

  By the repeated detection of the stall error and the corresponding correction of the deflection current as a function of the results of the detection, the stall error of the output images of the respective camera tubes gradually disappears.

  which ensures the automatic calibration The counting or de-

  counting of the counter 27 are interrupted when the error

  Calorimeter converges on the set value or goal.

  The automatic adjustment of the vertical setting is done in the same way The image-side signal of the vertical setting adjustment is provided to give by

  via a subtractor 24 (FIG. 5) the different

  between the output signal G 'of the green tube 4 and the signal obtained by delaying the output signal G' by a value equal to 2 H via the delay lines 5 and 6 at 1 H. The output signal the side signal provided by the subtractor 24 is applied to the multiplier 12 via a contact V of the inverter switch 11 via a delay line T, to keep the output signals of the red tubes in phase and blue with the main signal Go of the green tube 4 The operation of detecting the error V by the circuit of which the multiplier 12 is part is basically the same as that described to detect the error H. The compensation of the calibration at the of the detection of the calibration error data representing the errors H and V is done for both the red tube 3 and the blue tube 2 and for each of the forty-nine segmented image areas of the table of FIG. 1 test The calibration error data obtained p for each area

* 15

  Segmented image is temporarily stored in the respective memory area shown schematically at

  Figure 2 The calibration error data thus recorded

  stored in the memory of Figure 2 are interpolated in the vertical direction and the resulting interpolation data is written into the respective elements of

  the memory shown schematically in FIG.

  Figures 8A and 8B, combined, represent

  attempt a block diagram of the signal processing circuit

  21 to perform a series of trafficking operations

  data according to one embodiment of the invention.

  The signal processing circuit 21 is

  shown in Figure 8 B as consisting mainly of a half

  central microprocessor CPU composed of a microprocessor

and ROM and RAM memories.

  According to FIGS. 8A and 8B, an arith-

  and logic and registers of a central processing unit CPU 34 with a program stored in this unit constituting a counter corresponding to the up / down counter 27 shown in FIG. 6 The counting state of this counter is supplied to the beam deflector 22 or 23 of the blue tube 2 or the red tube 3 by

  that of buffer circuits 39a, 39b, 39c, 39d corresponding to

  digital and analog converters

  40a, 40b, 40c, 40d (FIG. BA), associated via a data bus 35 (FIG. SB) of a locking circuit 36,

  of a full adder 37 and a latch circuit 38 (FIG. SA) The comparison signal COM of the comparator 28 shown in FIG. 6 is applied to the CPU 34 via an input / output port (I / O port) 41 The counter count of the CPU 34 is incremented or decremented according to the polarity or level of the comparison signal COM The vertical synchronization signal VD used in the television camera can

* 2,509,558.

  9 can be supplied as a clock pulse to the counter of the CPU 34 and may include a clock generator

or clock 47 (FIG. 8A).

  As described above for FIG. 6, the deflection current is changed by incrementing or decrementing the counting state of the counter of the CPU 34.

  calibration compensation, the detection circuit represents

  Figure 5 again detects the stall error.

  By repeating the operations described above, we will delete

  I steadily errors in the images in the respective tubes and the calibration error data provided by the counter of the CPU 34 has a predetermined convergence This data

  calibration error is recorded at the corresponding addresses.

  of a random access memory (RAM) M 3 (Figure 8 B).

  The RAM memory, M 3 has an address matrix

  7 x 8 as shown in Figure 2.

  calibration error of each segmented image area shown in Figure 1 receives the respective address of

  the RAM memory, M 3 A control address for the

  Memory RAM, M 3 is provided by an address decoder of the CPU 34 via an address bus. A gate pulse GE for designating each segmented image area shown in FIG. generated by a gate pulse generator 42

  (Figure 8 A) and is provided to AND gate 18 through

  intermediate of the terminal 19 shown in Figure 5.

  At the end of the detection of the stall error of one of the four channels, that is to say the vertical error of the blue tube, the horizontal error of the tube

  the vertical error of the red tube and the horizontal error

  zentral of the red tube, calibration error data

  stored in RAM, M 3 are supplied separately.

  quently to the CPU 34 by the data bus The CPU 34 performs data interpolation

  calibration errors received in the vertical direction.

  A basic interpolation program and a program of

  control system of the entire system are in-

  written in a read-only memory (ROM) M 4 (Figure 8 B) Part of the RAM RAM, M 3 is used as

  work register The interpolation data is in-

  written by the data bus 35 in a random access memory (RAM), M 2 having a memory area as shown in FIG. 4 A predetermined datum, for example the data item H (hexadecimal notation), is written to all the addresses of the RAM memory , M 2 at the start of a compensation operation This predetermined datum at each address is replaced by the respective interpolation data and during this re-registration in the RAM memory, M 2, the command addresses are provided.

  to the RAM memory, M 2 by the CPU 34 via

  diary of a buffer circuit 44 which is then passing.

  At the end of the interpolation, the stall error data recorded at the respective addresses of the RAM memory, M 2, are read in synchronism with the scanning of the camera tubes 2, 3, 4. The calibration error is provided to the beam deflector of each respective camera tube 2 or 3 through the following circuits 39a, 39, 39c, 39d and D / A digital-to-analog converters. a, 40 b, 40 c, 40 d corresponding through the full adder 37 and the latch circuit 38 During this operation, the buffer circuit 43 becomes on and the control addresses of the RAM, M 2 are provided by buffer circuit 43 from

  of an address generator 46 According to the data

  stored at each address of the RAM memory, M 2, we ob-

  holds an image output signal which has been subjected to a calibration compensation, coarse A second calibration compensation operation is then performed on the basis of this coarse-corrected image output signal.

  reading of the data in the RAM, M 3 and the register

  the data in this memory RAM, M 2 are executed

  under the control of the output signal of a circuit of

  data processing control 48 (FIG. 8B).

  The data needed for the second operation

  calibration compensation are provided for the addition of

  The complete adder 37 adds the data for the second calibration compensation to the full counter 37 of the CPU 34 via the data bus 35 and the latch circuit 36.

  data-corresponding to the first compensation of

  RAM, M 2 The result of this addi-

  This is converted by the buffer circuits 39a, 39b, 39c, 39d and the D / A digital converters a, 40b, 40c, 40d into analog data which are supplied to the deflector of the tube. Shooting 2 or 3 corresponding The second calibration compensation data which is detected by a counting / down counting operation of the counter in the CPU 34 as in the case of the data item corresponding to the first calibration compensation is recorded in FIG. corresponding address of

  the RAM memory, M 3 Such a second compensation data item

  Stalling is a fine compensation component compared to the coarse compensation component corresponding to the data of the first stall compensation.

  At the end of the second compensation operation

  calibration for each segmented image area

  shown in FIG. 1, the data recorded in the memories RAM, M 2 and M 3 are again the subject of a synthesis by the CPU 34 and are recorded in the RAM, M 3.

  in RAM, M 3 are interpolated in the direction

  vertically by the CPU 34; the data resulting from each interpolation is stored in the memory

RAM, M 2.

  The calibration compensation described above is performed twice for the vertical errors of the respective red and blue tubes 3 and 2 and four times for the horizontal errors of these tubes.

  compensation operations, repeated, it can not be

  a complete elimination of calibration errors from

  in more detail, each of the image areas, segment

  FIG. 1 may be considered as the center of the screen and a continuous polarization or deflection current is provided to each image area.

  segmented to detect the static error data

spective.

  In other words, the calibration error data is detected under static conditions. Then, when such calibration error data is obtained,

  in the statistical conditions are read in synchronism

  me with the beam scanning operation of the respective camera tube, and that they are subject to

  deflector of each tube, the frequency characteristics

  quence or dynamic characteristics of the deflector may

  However, according to the invention, the stalling error

  resulting from the dynamic characteristics of deflec-

  is removed by the clearing operations

  repetitions reducing the calibration error to zero.

  When the error data provided by the first calibration compensation operation is read in synchronism with the beam scan and is supplied to the deflector as an error signal, this error signal is a high frequency signal, the frequency being at least four times the horizontal scan frequency Such a high frequency signal may cause distortion as a result of

  specific to the inductance of the deflection system.

  beam angle of the corresponding camera tube.

  However, in the case of the detection of

  According to the present invention, a continuous signal determined as a function of the counting state of the counter of the CPU 34 is provided as an error signal at each

  deflector This error signal is not subject to

  fluence of the frequency characteristics of the deflection system, which makes it possible to obtain error data

extremely precise.

  During the second compensation operation

  and, as a result of this, the addition made in the full adder 37 (FIG. 8A) of the first error data read in the RAM memory, M 2 to the second error data provided by the CPU 34 can cause

  For this reason, the detector debor-

  50 detects the carry output of the full adder 37 When overflow of the adder

  37 is detected, a polarization datum pre-

  determined, is provided to the data bus by the detec

  overflow 50 and through a

  bake lock 51 to restore the overflow condition

  is lying. The error data which has been detected and interpolated, is stored in the RAM memory, M 2 to be transferred to each of the RAM memories, MI, M1 ', M1 "

  and Mi "'by the full adder 37, the green circuit

  rusting 38 and one of the corresponding buffer circuits 39a, 39b, 39c, 39d Each of the RAM memories, Ml Ml "'has the same capacity as the RAM memory, M 2 RAM memory

  Ml is allocated to the R / V channel, that is to say to the vertical channel.

  tical of the red tube 3; the RAM memory, ML 'is allocated

  fogging the R / H channel that is to say the horizontal channel of the red tube 3; the RAM memory, Ml "is assigned to the B / V channel, that is to say to the vertical channel of the blue tube 2;

  RAM, Ml "'is assigned to the B / H channel ie

  tell the horizontal channel of the blue tube 2 The circuits-

  buffers 39a, 39b, 39c, 39d associated with the respective R / V, R / H, B / V and B / H channels are selectively implemented by a control signal provided by a circuit selection decoder. buffer (hereinafter referred to as "decoder

  B / S) 52 through the door 53 (Figure SA).

  The memories RA Mt M 1 M 1 '* $ are given by a symbol

  control signal provided by a chip selection decodel (hereinafter called C / S decoder) 54 by 1

  These decoders 52 and 54 work-

  slow in response to a cue signal provided by

  CPU unit 34 through port I / O port 41 (: Efigu-

re 8 B).

  The data recorded in the documents

  RAM, Ml Ml "'are read in synchronism with the de-

  bending the electron chip of the respective camera tube in response to an address signal provided

  by an address generator 56 through an address bus.

  its 57 Data is provided am deflector of arwatu

  22 and 23 of the red and blue tubes 3 and 2 by

  digital to automatic (D / A) converters 40 a-O 40 d cor-

  As a result, the compensation is

  stagnation of vertical and horizontal errors in each

  one of the red 3 and blue 2 tubes, the television camera

  sion thus provides an output signal vi ddo ne ccmor-

  The read and write operations of the data in the RAM RAM Ml '' are made according to a read / read command signal.

  registration provided by a cc signal generator: nuản-

  The generator 60 provides a read / write command signal in response to a rate generated by a rate generator 59 and the signal of

  control output of the signal processing circuit 48.

  Figure 9 shows a flowchart of

  the calibration compensation operation described above.

  Note that this operation is initialized by the

  In the course of the first resulting step 100, a predetermined datum 100 is obtained from a compensation start button (not shown) of the television camera.

  which can be for example equal to 80 H (hexadecimal notation)

  male) is written in the RAM memory, M 2 In step 101, the predetermined data item stored in the RAM memory, M 2 is transferred to the RAM memories MI Ml "'When this predetermined data is supplied to the

  RAM memories, Ml Ml "', the output signal of each

  each digital to analog converters 40 to 40 d

  is zero and the degree of correction of the deflection current

  beam angle of each camera tube is zero. In step 102, the circuit decides

  if a start signal is available This signal of de-

  It can be appropriately generated at the end of the operation of the automatic centering circuit to align the centers of the image areas of the red and blue tubes with respect to the green tube. This automatic centering circuit can have the structure described above in FIG.

  with the help of figures 5 and 6 The self-centering

  It is intended to align the centers of the images of the respective camera tubes before performing the stall compensation and to reduce the importance of the stall compensation. If the centering is done manually, the starting signal distinguished during

  step 1 È 2 can be generated by the depression of a

  starting tone at the end of the manual centering operation.

  In step 103, the circuit chooses

  a channel among the different channels (R / V, R / H, B / V, B / H).

  During step 104, the predetermined datum is again entered in the RAM memory, M 2 since this predetermined datum is written in the RAM memory, M 2 each time the data stored in the memory

  RAM, M 2 is reset before compensation is

  This pre-determined data, which corresponds for example to BOH (hexadecimal notation), does not correspond to any calibration compensation. In response to this preset operation, the data stored in the RAM memory, M 2 during the previous calibration compensation operation, is

  In step 105, the counter (counting

  REGI) to count the number of opera-

  calibration compensation procedures that have been performed

is set to "0".

  In step 106, the circuit decides or determines whether the channel (R / V, R / H, B / V and B / H) selected or designated in step 103 is a horizontal channel (R / H or B / H) or a vertical channel (R / V or B / V) If the selected channel is a horizontal channel, the subprogram

  input / output (I / 0) of data 107 to load the data.

  M 3 is executed at the end of the execution of this subroutine 107, the circuit executes a subprogram 108 ensuring

  interpolation in the vertical direction for the

  born of horizontal error loaded into RAM memory, M 3.

  At the end of the execution of the subroutine 108, the counting state of the counter REGI is incremented by one unit,

  then the circuit distinguishes or decides whether the state of account

  resulting ge is equal to "4" If the counting state is

  not equal to "4", the program returns to the sub-pro-

  The subroutine 107 is thus repeated until

  than four times and this corresponds to four calibration compensation operations At the end of the fourth loop, the resulting data stored in the RAM memory, M 2 is transferred during step 110 into one of the RAM memories , Ml Ml "'(which corresponds to the R / V channel, R / H, B / V or B / H) previously selected during

step 103 -

  Moreover, when in step 106, it is determined that the chosen channel is a vertical R / V channel

  or B / y, the data I / O routine 107 'and the sub-program

  interpolation program 108 'are performed successively

  In step 111, the circuit discriminates or decides whether the REGI loop formed of subroutines 107 'and 108' has been executed twice as for compensation.

  vertical errors, since the unity of the element-

  image in the vertical direction of the image is the li-

  Horizontal scanning pattern and the vertical scanning speed is much lower than the horizontal scanning speed of the electron beam of each tube-shooting, the compensation of vertical errors is less influenced by the dynamic characteristics

  deflectors, so that we can obtain a

  very satisfactory thinking for vertical stall errors by performing the compensation operation

corresponding only twice.

  After loading the data entered in the RAM memory, M 2 in one of the RAM memories, Ml Ml "'during step 110, the circuit decides in step 112 whether the compensation of the four channels R / VT, R / H, B / V and B / H has been executed If not, the

  program returns to step 104 and a com-

  thought is performed for each of the remaining channels, as chosen, in the order in step 103. If the decision taken in step 112 is YES, the compensation operations performed by the

  circuit shown in Figs. 8A and SB are terminated.

  FIGS. 1A, 1B and 1C together as shown in FIG. 10 represent a flow chart of the input / output routine I / 0 of data 107 in the flowchart of FIG. 9; according to this flow chart, in step 120, the control address SA of the RAM memory, M 3 is set to one of the corresponding segmented image areas shown in FIG. 1. In step 121, the address Said control unit SA is thus applied to the I / O port 41 (FIG. 8B) and thus to the gate pulse generator 42 (FIG. SA) In response to the command address SA and to the address generated by FIG. the address generator 56 in synchronism with the scan

  O 10 of the electron beam of the camera tube resp.

  In this way, the gate pulse generator 42 generates a gate pulse GE representing the position on the screen of the segmented image area identified by the command address SA. In response to this gate pulse GE, the horizontal error data using the detection circuit shown in the figure for the segmented image area represented by the

order of SA.

  During step 122 of the ordinograim of FIG. 1 OA, the counting state of the loop counter REGI is determined. If the count state is equal to "1", the data item 80 H (hexadecimal notation) is charged

  in the register r 3 of the unit CPUT 34 during the

  pe 123 so as to fix the variable range (dynamic range

  that) of the counter in the CPU 34 on the pre-determined value

  In step 1 i 24 (FIG. 10 B), the count state of the counter of the CPU 34 is set in a predetermined manner to the value 80 H as shown in FIG. 11 and the degree of correction of FIG. the deflection of the beam of the corresponding camera tube is zero in the current compensation operation. The dynamic range g of the counter count up / down counter operation is equal to 80 HA in step 125, the state of Counter count is transferred from CPU 34

  (FIG. 8B) to the locking circuit 36 via

  Data bus 35 The output signal from the bus

  Locking furnace 36 undergoes a digital-to-analog conversion to be applied as a correction current to the respective beam deflector. To facilitate the convergence of the data towards the limit or the goal, the state

  counter count of the CPU 34 is not changed.

  in 1-bit units as in the case described above, but preferably this state varies by half of the variable range to ensure a fast search of

the error data.

  Therefore, in step 126, the data representing the dynamic range of the counter of the CPU

  34 and which is registered in the register r 3, is reduced

  at half of the original value that is to say -8 OH / 2 During step 127, the circuit checks whether the vertical synchronization signal VD is applied to the CPU 34 Si unit. the result of this check in step 127 is YES, the comparison signal

  COM of the comparator 26 corresponding to the data of comp-

  Up / down counting U / D representing the error direction is loaded during step 128 in the CPU 34 by the I / O port 41 This U / D data is checked in

  step 129 If the U / D data is an incremental data item

  In this case, the counting status of the counter of the CPU 34 is counted in the dynamic range r 3 (= 80 H / 2) in step 130. Otherwise, if the U / D data is a given value. decrement, the counting state of the

  counter is counted by r 3 (= 80 H / 2) during the

eg 131

  In step 132, it is checked whether the dynamic range

  reduced meter r 3 of the counter reaches 1 bit.

  The result of decision step 139 is negative, the pro-

  gram returns to step 125 to transfer the count state of the counter into the latch

  36 The result is a degree of correction (+ r 3/2 that is,

  say + 80 H / 2) corresponding to the counting state of the

  tor; this value is supplied to the beam deflector as shown in Figure 11 Then, the dynamic range

  r 3 of the meter is again divided by two for example

  depending on (+ r 3/4 or 80 H / 4) and the counting status of the

  is counted or is deducted from that quantity

  The counting or downcounting loop of the U / D counter is repeated until the successively reduced dynamic range r 3 reaches the value of 1 bit. Thus, the output signal of the counting state of the counter converges. towards a goal or a limit S by the successive variations + r 3/2, + r 3/4, -r 3/8,

  -r 3/16 etc for each vertical synchronization signal

  the RV as shown in Figure 3.

  After the reduction of r 3 to 1 bit, the beach

  counter dynamic is maintained at this value

  that the reduction of r 3 to 1 bit is confirmed in step

  132, the processing of the data is done in the order

  shown in FIG. 1 o C, namely the detection of the vertical synchronization signal VD supplied to the CPU 34

  (step 127 '), loading in the CPU 34 of the data

  born U / D representing the direction of the error (step 128 a), verification of the up / down counting data U / D (step 129 '), counting or downcounting of the counting state of the counter according to r 3 (step 130 'or 131') During step 133, it is checked whether the counting or counting that is to say the U / D operation has been repeated four times as shown in FIG. 11. If not, the counting state is transferred to the locking circuit 35 (step 125 ') If in step 133', the circuit verifies that the U / D operation (counting / down counting) has been repeated

  four times to appreciate that the data of er-

  has converged towards the limit value, then in the

  eg 134, the counter count of the CPU 34 is stored at the corresponding address of the memory

  RAM, M 3 This completes the first compensation operation

  for storing one of the segmented image areas shown in FIG. 1 Then in step 135, the control address of the RAM memory, M 3, is incremented by one and the calibration compensation of the next segmented image area is performed if in step 136 the circuit verifies that the first stall compensation of all segmented image areas is not complete The loops of up to j shown in FIGS. and OA are repeated until the end of the

  calibration compensation of all image areas seg-

  mented. When in step 136, it is verified that the first calibration compensation operation of all

  the 49 segmented image areas of Figure 1-is ter-

  mined and that the error data has been entered at all the corresponding addresses of the RAM memory, M 3, then in step 137 (FIG. 1 OC), the circuit writes the average value data obtained by interpolation to each

  address of the RAM memory, M 3 corresponding to the inter-

  H-BLK horizontal erasing value shown in FIG. 2 This completes the first data I / O input / output routine 107 and the program returns to the

  main program according to the flow chart of Figure 9.

  In the main program, the sub-program is

  interpolation me 108; the interpolation data is stored in the RAM memory, M 2 According to the data read in the RAM memory, M 2, the corresponding tube beam deflector is controlled for

  make a calibration compensation.

  When the first clearing operation

  calibration is performed, the counting status of the

  As a result of the flowchart of the main program according to FIG. 9, the input / output routine I / 0 of data 107 is returned to a second compensation operation. In this second calibration compensation operation, the counting state equal to two of the REGI loop counter is checked in step 122 and step 138 is jumped from step 122

  as shown in FIG. IQA At step 138, the first

  The first error data, i.e., the error data obtained during the first calibration compensation, is read at the control address of the RAM memory, M 3 by the CPU 34. step 139, the sign or the polarity of the error data is checked and it is decided whether the error data is greater or less than the reference datum equal to 8 OH If the sign distinguished in step 139 is positive, that is, if the error data is greater than 8 OH, then in step 140 the error data 51 (FIG. 11) is subtracted from FFH (represented by states "1" in hecadecimal notation ) and the result of the subtraction is entered in the

  register r 3 as variable dynamic range r 3 'Au

  milk if the verified sign in the strut 139 is negative,

  the error data itself is written in the register r 3 during step 141 as a dynamic range

variable r 3 '.

  Then we perform the data processing

  in the same way as in the first

  the calibration thinking described above Ainisi the opera-

  Counting / down counting of the counter is done from the state 80 H in increments of L-, -rr '/ 4, + r 3' / 8 etc. as shown in Figure 11 i Consumes most of the calibration error is compensated by the first calibration compensation operation and

  since the limit S of the counter is small, the dynamic range

  meter can be relatively low in the

  second calibration compensation operation.

  When the second calibration compensation operation is completed by counting / down counting and the second error data is written to all the addresses of the RAM memory, M 3, the program returns to the main program in the flowchart shown in Figure 9 and the data is interpolated in the vertical direction according to the subprogram

  interpolation circuit 108 shown in FIG.

  In more detail according to FIG. 12, the address N (0 to 55) of the RAM memory, M 3 represented in FIG. 2, is fixed at step 150. Then, during step 151, the address of the RAM memory, M 2 is put

  in the registers r 3 and r 4 to correspond to the address-

  Although RAM, M 3 is represented in FIG. 2 as being a one-dimensional memory whose addresses are the values O to 55, the RAM memory M 2 is

* shown in Figure 4 as a two-way memory

  which extends both in the vertical direction

  and in the horizontal direction In step 152, the data recorded at each address of the RAM memory, M 2 corresponding to the address of the RAM memory, M 3 is read and is added to the corresponding error data in the memory RAM, M 3 In the case of the first operation

  of the calibration compensation, the data item 80 H is predetermin

  born or stored in RAM, M 2 At the beginning of

  the second calibration compensation operation, the

  born from interpolation obtained from the first

  error detected during the compensation operation.

  previous calibration setting is recorded in the

  RAM, M 2 and the data of the second detected error is stored in the RAM, M 3 In step

  152, the new error data is obtained by adding

  M 3 + M 2; this new value is saved

in the RAM memory, M 3.

  In step 153, the data recorded

  at the address N of the RAM memory, M 3 is loaded into the register rl and in step 154, the data item stored at the address (N + 8) of the RAM memory, M 3 is loaded into

  the register r 2 of the CPU unit 34 The data at the addresses

  its N and (N + 8) are adjacent to each other in the vertical direction of the image area shown in Fig. 2 At step 155, the interpolated data II, I 2 etc. by dividing the difference of the data recorded in the respective registers rl, r 2 corresponding to 36 elements or increments is calculated by approximation

  The result of this calculation is recorded temporarily

  evening in a virtual zone M 3 'having K addresses

  (O to 35) RAM, M 3 The expression of the inter-

  polation is as follows: 136 K) rl + Kr 2 + 18 to / 36 The value of K varies from 0 to 35 and the result of the calculation

  is registered at the corresponding address of the zone M 3 '.

  As a result, and as shown in FIG. 13, the data corresponding to 35 respective scan lines, between a pair of adjacent data in each case, are calculated.

  the vertical direction for example D 16 and D 24.

  In the decision step 156, the N addresses (from 0 to 55) are classified into higher addresses (O to 7)

  intermediate addresses (8 to 47) and addresses

  (48 to 55) In the case of higher addresses

  and lower, the program switches to A and B respectively.

  In the case of intermediate addresses, the program switches to C of o during phase 157, the interpolation data recorded at the address K (0 to 35) of FIG. zone M 3 'are transferred to the address of

  the RAM memory, M 2 denoted by the registers r 3 and r 4.

  In step 158, the address N of the RAM memory, M 3 is incremented by one unit. In step 159, the address of the RAM memory, M 2 corresponding to the incremented address.

   N "= (N + 1) is calculated to make the following interpolation

  However, the program returns to step 158 through step 160. If the N address of the RAM memory, M 3 is ahead of 55 and the interpolation is complete for most of the data corresponding to the d-boxes. segmented image, this state is distinguished in step 160

  and the program goes back to the main program

shown in Figure 9.

  According to Figure 14 which is a flowchart

  interpolation of extension or expansion of the ex-

  upper trenity of the image zone corresponding to the branch A from step 156 to FIG. 12 shows that in step 161, the address K (from 0 to 17) of the zone M 3 'is fixed As a working memory in the RAM memory, M 3 In step 162, the address J (36 to 53) of the area M 3 'is set. The calculated interpolation data in the direction of the upper end ( K = 0) towards the inside of the image zone in step 155 in FIG. 12 is written at the address K (0 to 17) of the zone M 3 'The address J of the zone M 3' contains the data that

  corresponds to the extension by interpolation.

  In step 163, the address O (K = 0) of the zone M 3 'is loaded in the register rl of the CPU 34 The data at the address O corresponds to the data of the parts of higher end 0, 1, 2 segmented image areas In step 164, the address

  K of the zone M 3 'is loaded in the register r 2 of the unit

  When an extension interpolation is carried out by linear approximation as indicated in the graph of FIG. 15, the interpolation datum of the register r 2 and the new datum r 2 'obtained by

  this interpolation are symmetrical following a symmetry

  sort by point around the data of the register rl at the upper end As we have ar 2 f 1 = rl r 2 ', the extension interpolation data is obtained by the following expression r 2' = r I x 2 r 2 In step 165, the result obtained by this expression is again entered in the register r 2 In step 166, it is verified that the calculation result is exceeded If there is no overshoot, the result of the calculation of step 165 is

  transferred to address J of zone 13 'during the course of

  The address J of the zone M 3 'is the address 52 if the data of the register r 2 is equal to 1 In the case corntra -e, if there is an overflow, the contents of the register r 2 and delivered in the FFH state (corresponding to a set of states

  "l" in hexadecimal notation) cu in the OOH state (a set of

  state of "O" in the notation of: adcima Ie) in step 167. At the end of an interpolation operation, the address J is decremented by one unit, that is to say that it goes to (J 1) in step 169 In the step, the address K is incremented by one unit and set to (K + 1) The interpolation method is repeated 18 times until the address J is equal to 36 When in step 171, it is verified that J = 32, the extension interpolation data at address J (36 a

  53) of the zone M 3 'shall be transferred to the address corres-

  I in the memory RAM M 2 in step 172

  an extension interpolation operation for -rn elem-

  data at the upper end of the imaging area.

  ge is over, the program returns to branch 1 e C

according to Figure 12.

  According to Figure 16, we see that

  the ordinogranime of the interpolation of extension of the extre-

  The lower half of the image area in branch B of step 156 in FIG. 12 is generally the same as that shown in FIG. 14, and differs primarily only in that data interpolation, extension below the data at the lower end of the image area is calculated based on the data at the address K (18 to 53) of the zone M 3 'obtained by interpolation upward from the data of the lower end of the area

  image according to step 155 of FIG.

  In this way, we calculate the data of in-

  terpolation for all memory zones (256 x 8)

  shown in FIG. 4 and the result of the calculation is transferred to one of the RAM memories, Ml Ml "'of the RAM memory, M 2 as indicated with reference to FIG. 9 _ In the NTSC system, the number When the image area is vertically divided into 7 segmented image areas as shown in FIG. 1, and 36 lines are assigned to each segmented image area, the image area is 262.5. ,

  we have 6 x 36, that is 216 data elements of inter-

  polation for the intermediate portion of the frame and 18 data elements interpolation, extension for each of the upper and lower ends of the image area Therefore, the vertical addresses of each of the RAM, M 2 and Ml Ml V 'must be

  equal to 36 x 7 + 1 = 253 to contain a negative address

  In this way, a memory with a capacity of 2k bytes can record the data corresponding to a channel To have a correspondence

  between the vertical addresses of the memory and the

  In scanning modes 36 x 7 addresses are assigned to 36 x 7 scan lines and the remaining unique address is assigned to the 11 scan lines as the vertical clear interval. Thus the memory addresses are assigned to each of the scan lines.

36 x 7 + 11 = 263.

  At a vertical address of the RAM memory corresponding to 11 scan lines of the vertical erase interval, the average value between the data of the upper end obtained by extension interpolation at the upper end of the

  image area and data at the lower end obtains

  naked by extension interpolation at the lower end

  This average data is read repeatedly during the scanning of the lines forming the erasure interval. The erase interval (11 lines) for RAM addresses, Ml ml "'and M 2 is shorter than that As the scanning is done in a wide range containing the interval of erasure of the image in the tube of photography, one can thus improve the precision of the compensation

  on the periphery of the image area by performing a

  calibration thought even within the inter-

  vertical deletion zone A part of the

  moire represented as being surrounded by the solid line u in Figure 4 corresponds to a real image area

in the NTSC system.

  When the present invention is applied

  to the PAL television system, the error data required

  the calibration compensation is extracted from the

  same way as above By modifying the corresponding

  this between the vertical addresses of the RAM memories, Ml Ml "'and M 2 and scan lines, we can use

  the same circuits and the same programs for the

  NTSC and for the PAL system As the number of scan lines per frame is 312.5 in the PAL system, the image area is divided vertically

  in 7 segmented image areas and 42 lines are

  fogged at each segmented image area If the vertical fade interval is 15 lines, the required number of scan lines is 42 x 7 + 15 =

  309 That's why it takes 4 scan lines to

  complementary to have the 312.5 scan lines corresponding to one frame and the interpolation data

  can be obtained for these 4 additional scan lines

  by extending interpolation to

  down in the lower segmented image area any-

  times if an address is assigned to a line as in the case of the NTSC system, the required number of addresses

  is equal to 42 x 7 + 1 + 4 = 299, and the corresponding data

  to a channel can not be stored in a memory with a capacity of 2k bytes. In terms of cost and consumption, it is undesirable

  to increase the capacity of the memory.

  For this reason in the way of

  of the invention for the PAL system, 36 addresses are assigned to the 42 lines The incrementation of the address has stopped once every 6 steps to ensure the correspondence between the number of error data elements and the number of lines Given this processing system, in terms of memory location, the effective image area of the PAL system as indicated by the dotted lines v in FIG. 4 is substantially the same as the image area. effective NTSC system

  as indicated by the line in solid lines u.

  The address generator 56 which generates a

  RAM addresses, Ml Ml "'to read the data.

  error in synchronism with the scanning operation of the camera tube will be described below using

  FIG. 17 According to this figure, the signal of synchronization

  HD horizontal scoring (FIG. 18B) used in the television camera is applied to an H phase adjusting circuit 62 to undergo a phase adjustment as shown in FIG. 18C, and then applied to a PLL circuit 63. The gate pulse GE is generated by the gate pulse generator 42 as a function of an address generated by the address generator 56, the H phase control circuit 62 serves to adjust the phase of the horizontal synchronization signal HD to that the effective image area is symmetrical with respect

to the GE gate pulse.

  The output of the PLL circuit 63 provides

  16 FH clock pulses (FIG. 18 F) by frequency multiplication so as to have a frequency equal to 16 times the horizontal frequency The clock pulses 16 FH are supplied at the clock input CK of the counter H

  64 to 4 bits A report output FH at the horizontal frequency

  Zontal (FIG. 18 E) is divided by the counter H1 64 and passes through an inverter 65 to give an inverted signal FH (FIG. 18H) which is fed back to the PLL circuit 63 as a phase comparison signal. A pulse rate 8 FH (figure 18 G) whose frequency is equal to 8 times the horizontal frequency is obtained from the

  least significant bit of the counter H 64 This impulse

  cadence 8 FH is used as the cadence for gen-

  address an address needed to read horizontal error data from the% AM memory The three most significant upper bits VMAO, VMA 1 and VMA 2 of the counter H 64 are used to define the horizontal address of the data of vertical error This address changes from

  O to 7 in the horizontal scan interval

shown in Figure 18 H.

  A phase control circuit V 66 is also

  The phase control circuit V 66 receives the vertical synchronization signal ED (FIG. 19B) used in the signal generator 56 and is the same as the phase control circuit H 62. television camera and provides a time signal VD 1 shown in FIG. 19 D This time signal V,

  VD 1 is applied as a preset signal to a

  erase driver V (V-BLK) 67 which sets an erase interval V, (VBLK) (Fig. 19A) to the read address A time signal V, VD 2 (Fig. 19E) is also provided by a phase control circuit V, 66 to be applied as a flip-flop condition signal 68 which generates an erase signal V, BLK (FIG. 19H). This flip-flop 68 is provided for order

  counters V, 69a and 69b as will be detailed.

  According to FIG. 19 F, the counter V-BLK 67 is preset to the counting state "4" by the time signal V, VD 1 (FIG. 19 D). This preset value is determined by the preset data PS applied to the counter 67 and a high level signal provided by a switch NTSC / PAL switch 70 The counting status

  V-BLK 67 is counted at the reception at

  PE authorization rate of each FH pulse rate

  (horizontal scanning frequency) provided by the

  When the count state reaches the value "15", the counter 67 generates a transfer pulse "15 CA" as shown in FIG. 19 G The counter V-BLK 67 receives furthermore a clock pulse CLK; the clock pulses 16 FH (FIG. 18 F) which are provided by the PLL circuit 63 to

through the buffer circuit 72.

  Since the AC transfer pulse (FIG. 19 G) of the V-BLK counter 67 is applied to the flip-flop 68 as an erase pulse, the erase signal V, BLK (FIG. 19H) obtained at the output Q flip-flop 68 in

  synchronism with the rate impulse FH has a

  pulse width equal to 11 H This erase pulse signal BLK is applied to the CLR inputs of both

  counters V 69a and 69b as the erase pulse.

  For this reason, the counters V 69a and 69b make a count at each horizontal scanning interval,

  after the erase pulse signal BLK represents

  Figure 19 H has returned to its highest level.

  The two counters V 69a and 69b are

  4-bit transceivers connected in series with each other Although the clock pulse 16 FH applied to the V 69a and 69b counters has a frequency equal to 16 times the horizontal frequency, the counters generate counting states

  from 0 to 256 which are counted in synchronism with the inter-

  horizontal scanning range since the impulse of

  FH of horizontal frequency or frequency of

  This is applied to the TE authorization entry of the

  V 69 a These count states 0-256 corresponding to the

  8 bits VMA 3 VMA 10 are used as vertical addresses

  shifts for the memory area shown in FIG. 4 for reading the vertical error data in the respective memory. In more detail, the horizontal address bits VMAO-VMA 2 of the counter H 64 and the address bits vertical VMA 3-VMA 10 counters V 69a and 69b are applied to the RAM memories Ml and Ml "(Figure SA) to read the vertical error data

red tube 3 and blue tube 2.

  The VMAO-VMA bits 5 and the VMA bits 6-VMA 10 are also provided to the respective latch circuits 75a and 75b which also receive the rate

  8 FH (FIG. 18 G) of the counter H 64

  rust 75 a and 75 b each consist of eleven flip-

  flop D and give the read addresses of the horizontal error data; these addresses change with the leading edge of the rate SF 1 I and are defined by the horizontal address bits HMA 0-HMA 2 and the bits

  corresponding HMA 3-HMA 10 vertical address

  VMAO-VM 52 bits and VMA 3-VVA bits 10

  shown in FIGS. 18H and 18I for the address bits

  its horizontal VMAO-VMA 2 for error data

  vertical and HMAO horizontal address bits

  HMA 2 for the respective horizontal error data, the counting of the addresses defined by the IU O HMA bits 10 for the reading of the horizontal error data is delayed by half the period of the clock rate 8 PH relative to the count addresses defined by the bits VM 0-VMA 10 for the lebture of the vertical error data The horizontal address bits HMAO-HMA 2 and the vertical address bits HMA 3-HMA 10 are applied by the locking circuits 75a and 75b to the RAM memories, Ml 'and Ml "' (Figure 8A) to read the error data.

  horizontal line of red tube 3 and blue tube 2.

  The vertical error data read in the RAM, MI and MI "memories and the horizontal error data read in the RAM memories, M1 'and M1' 'are converted

  by analog-to-digital conversion in converts

  40a and 40c as well as in the converters 40b and 40d before being applied to the vertical and horizontal deflection coils deflectors 23 and 22 of

  red and blue tubes 3 and 2 by means of a

  appropriate low pass (not shown) The delay or the temple constant of such a low-pass filter is

  chosen to compensate for the corresponding phase difference.

  halfway through the period of the 8 FH rate between the reading of the vertical error data of the memories

  RAM, Ml and Ml "and the reading of the horizontal error data

  zontales of the memories RAM, MI 'and Ml "' -

  According to Figure 18 J which shows a part of

  the gate pulse ("O" and "6") GE generated by the gen-

  As a function of the VMA or HMA addresses and the control address SA representing the segmented image areas 0, 1, 2, etc., FIG. 2 shows that the gate pulse GE is behind the VMA and HMA addresses if the delay is taken into account

  due to the low-pass filter mentioned above.

  A television camera according to this embodiment of the invention will be described hereinafter in its application to the PAL system. FIG. 19 J shows

  the vertical erase interval of a PAL Com-

  As indicated above, when the present invention is applied to the PAL system, an interval of 15 H of the erase interval is assigned to an interval.

  erase while reading the data in the memory.

  When the inverter switch 70 (FIG. 17) is in the PAL position, a predetermined low level signal changes the predetermined datum of the V-BLK counter 67. This results in the preset of the V-BLK counter 67 being set to a state of

  counting "O" as shown in Figure 19 K in function

  time signal V, 11 (FIG. 19 D) and the

  then 67 counts to state "15" at the frequency

horizontal scanning.

  The Q output of the flip-flop 68 goes low during the time interval 15 H from the time signal V, VD 2 to the report output I CA of the counter

  V-BLK 67 During this period of time corresponding to

  At 15:00, the counters V, 69a and 69b are erased to interrupt their counting. When the flip-flop 68 is reset by the carry-off output CA, the cleared state of the counters V, 69 a and 69) is released and counters start counting state 1 at state 255, as shown in Figure 19 L.

  The low level signal of the Cormutator-in-

  Pourer 70 is also provided by inverter 76 at the authorization input Tr of a counter 6/7, 77 of a 4-bit structure. This counter 77 receives 1 i clock pulse 16 FH on the clock input. CLK and rate pulse FH on the counting authorization (PE) input; the count 77 thus works at the horizontal scanning frequency The counter 77 receives a state "9" as preset data PS, that is to say as shown in FIG. 19 M, the counter 77 counts from the state 10 to " 15 "after the 15 Hr breaking interval; this counter

  generates a report output CA when the report state

  the value reaches "15".

  counter 77 is applied back to the erase input

  CLR by the inverter 78 and the OR gate 79 of negative logic that is why as shown in FIG.

  19H, in response to the FH pulse rate, after the

  In this way, the counter 77 functions as a base-seven counter. As the carry-off output CA of the counter 77 is inverted by the inverter 78, it is set to the "9" state. applied to

  the PE authorization entry of the counter V 69 a, this

  69 stops counting when his state of

  stage reaches the value "15" The output of the inverter 78 is also supplied to the input of the AND gate 80

  which receives the pulse rate PH on another

  For this reason, the sending of the pulse rate PH to the PE authorization input of the counter V 69 b is forbidden, although that the counter V 69 b stops counting when its counting state reaches the value "15". As a result, as shown in FIG. 19 L, the interruption of the counting of the counters V 69a and 69b at each interval of 7 H The vertical addresses VMA 3 and VMA 10 are thus generated, so that the same address is generated twice or is repeated after each group of 6 addresses, for example in the following order, 6, 6, 7, 8, 9, 10, 11, 12, 12, 13 etc. When the present invention is applied to the PAL system, the content of the RAM memories, Ml Ml "'is read such that after each sixth line, the next line is read with the data of the line immediately preceding. has 42 scan lines

  which are attributed to the 32 vertical addresses of the

  RAM, MI MI "'As shown in Figure 4,

  the effective image area of the PAL system can be

  green by RAM memories of the same capacity (256 x 8)

  as the RAMs used for the NTSC system.

  As already indicated, the VMAO addresses VMA 10 for reading the vertical error data generated by the address generator 56 shown in FIG. 17 are applied to the RAM, Mi (R / V) and M "memories (B / V), while the HMAO HMA addresses 10 for reading the horizontal error data are supplied to the RAM memories, Mi '(R / H) and Ml "' (B / H). The error data is thus read in synchronism with the scanning operation The vertical error data thus read in the RAM, MI and M1 memories after passing through the D / A converters 40a and 40c (FIG. SA) and the mentioned low-pass filter previously (not shown) is applied as a calibration offset signal ERROR R / V and ERROR B / V terminal 8 la and Sic (Figure 20) of

  vertical deflection system of the television camera

according to the invention.

  As shown in Figure 20, the system

  from vertical deflection to vertical deflection coils.

  spacers 82 G, 82 R, 82 B for the green tube 4, for the red tube 3 and the blue tube 2 respectively These coils are driven by class A or class B amplifiers 83 G, 83 R, 83 B respectively The variable resistors 84 G, 84 R and 84 B are connected in series to the vertical deflection coils, respectively 82 G, 82 R, 82 B.

  voltage terminals of the resistors 84 G, 84 R, 84 B are

  plicated back to the differential inputs of the amplifiers

  83 G, 83 R, 83 B, so that currents proportional to the input voltages divided by the value of the resistors 84 G, 84 R, 84 B

  the respective vertical deflection coils The ampli

  indicator 83 G for the drive coil 82 G of the tube

  green receives a sawtooth signal from vertical scanning

  V-SAW cal generated in synchronism with the sync signal

  vertical tracking VD by the sawtooth curve generator 85 The amplifiers 83 R and 83 B of the drive coils 82 R and 82 B of the red and green tubes receive the same sawtooth signal from the

  adders 86 a and 86 b respectively.

  The R / G ERROR and ERROR-B / V calibration compensation signals are supplied to the adders 86a and 86b through the respective terminals 81a and 81c to perform vertical pitch compensation of the red and blue tubes. deflection-vertical 82 G,

  82 R and 82 B have different frequency characteristics.

  rents and high-frequency components for the calibration offset signal of vertical errors have

  frequencies which are equal to several times the frequency

  horizontal scanning and can thus deteriorate

  this is compensated by the repeated compensation

previously written.

  In the horizontal deflection system

  shown in Figure 21, terminals 81b and Bld receive

  the ERROR R / H and ERROR B / H error compensation signals, respectively, which result from the passage of the horizontal error data read in the memories

  RAM, Ml 'and Ml "by the digital / analog converters

  D / A 40b and 40d and by suitable low-pass filters

  A transistor 88 is driven by the horizontal synchronization signal HD so that the current in

  sawtooth at the horizontal scanning frequency

  pours the horizontal deflection coils 89 G and 89 R,

  89 B corresponding to green, red and blue tubes

  denser 87 is connected in parallel to transistor 88 for integration; a diode 91 is connected in parallel to the transistor 88 via a

  return transformer of spot 90 which ensures the amor-

  The secondary of the balancing transformer

  93 is connected in series to a capacitor 92 in

  the line through which the defibrillation current

  xion is applied to each of the homogeneous deflection coils.

  zontale 89 G, 89 R and 89 B A H-SAW sawtooth signal at the horizontal scanning frequency is generated

  in synchronism with the horizon synchronization signal

  tale HD by the sawtooth curve generator

  94 and is applied to the transformer transformer primary

  thought 93 via a gain control circuit 95 and an amplifier 96.

  compensation ensuring the linearity of the horizontal deflection

  tal. The lateral deflection coils 89 G, 89 R and 89 B are shown in FIG. 20 as having portions 89 G ', 89 R', 89 B 'which are adjustable to

  to control the inductance so as to allow a variation

  the size of the output image of

  each tube of shooting Variable resistances-

  97 G, 97 R, and 97 B are connected in series on the respective horizontal deflection coils 89 Gw 89 R, 89 B By controlling these variable resistors 97 G, 97 R, 97 B, the central position of the output image of each tube The variable resistances

  97 R and 97 B red and blue tubes may be replaced

  by a variable impedance circuit.

* editions, the central positions of the output images

  red and blue tubes are aligned with the posi-

  the output image of the green tube under the control of an automatic centering circuit as

indicated above.

  The horizontal coincidence compensation of the red tube 3 and the blue tube 2 can be done by the

  passage of a compensation current through the

  auxiliary bearings 98 R and 98 B which are in the form of secondary windings relative to the main horizontal deflection windings 89 R and 89 B respectively These auxiliary windings 98 R and 98 B

  are trained by amplifiers 99 R and 99 B receivers

  the error signals corresponding to the horizontal error data for the red channel and the blue channel, which data are read in the RAM memories, M1 'and MI "' By mounting these windings 98 R and 98 B,

  the main deflection windings 89 R and 89 B can

  There is no need to provide class A or class B amplifiers for this, which results in lower power consumption. As the coarse compensation for linearity, the the image and the central position of each camera tube can be made using the deflection currents passing through the main deflection windings,

  the importance of the error to be compensated by

  Auxiliary 98 R and 98 B is relatively weak.

  Therefore, the output capabilities of the amplifiers

  99 R and 99 B may be relatively small.

  Since the ends of the horizontal deflection windings 89 R and 89 B are short-circuited by the switching drive circuits in the horizontal scanning interval, the energy supplied to the auxiliary windings 98 R and 98 B escapes through the low impedance drive circuit and disturbingly influences the magnetic flux of the auxiliary windings In particular, the high

  frequency of the magnetic fluxes of the auxiliary windings

  are mitigated by this integration.

  performing the second calibration compensation and the

  following thinking as already described above, we have

  an error signal which is compensated for this attenuation

  This solves the problem of attenuation of the high frequency components. Auxiliary windings similar to the windings 98 R and 98 B of FIG. 21

  may also be provided for in the deflection system.

vertical section of Figure 20.

  In the embodiments of the invention,

  As described above, the interpolation of the vertical direction of the error data for each scan line is by linear approximation. However, this interpolation can be done by interpolation of the second or third degree. interpolation in the horizontal direction can also be done in the embodiments described above.

  although the memory area must be increased for this.

  As the calibration error generally increases at the

  of the screen, the image area shown in FIG.

  re 1 can be divided into segmented image areas

  smaller or smaller, in the vicinity of the periphery

  screen to improve the accuracy of the compensation

  The number of segmented image areas is preferably an odd number such that 7 × 7 = 49 as in the embodiment described above.

  zone-image is divided into an odd number of zones-

  segmented image, there is a segmented image area that is accurately formed in the center of the screen Therefore, if a continuous bias is applied to the main deflection windings in advance of the stall compensation to ensure the centering of the tubes, the degree of error to be compensated by

  the auxiliary windings is decreased.

  In summary according to the invention, the image area

  effective is divided into a set of seg-

  * (eg 7 x 7) and the stall error of the output signal of each camera tube (the red tube or the blue tube) by reference to the output signal of a camera shot tube. reference (tube

  green) is detected and recorded in a first

  moire (M 3); the information contained in the first memory is interpolated and the resulting data is stored in a memory area (256 x 8) of a second memory Jb (M 2) which is expanded in the direction corresponding to the vertical direction of the screen ; the error signals corresponding to the data read in the second memory are applied to the beam deflection control means for the red and blue camera tubes. In the above, the calibration error data of a relatively small number of operations

  sampling period can be detected in a period

  short and with a relatively small number

  segmented image areas As the data is interpolated

  to provide data corresponding to the horizontal scan lines, compensation can be

relatively precise calibration.

Claims (10)

R E V E N D I C A T IO N S   1) Color television camera with tubes   with an automatic caliper adjustment system.   ge, camera comprising a first camera tube (4) giving a corresponding first video signal (GO)   an image of a test chart for adjusting the calibration   ge, a second camera tube (3) giving a second video signal (RO 0) corresponding to the image of the test board and having a deflection control circuit, camera characterized in that it comprises a means   error sampling (34, M 3, 42) for sampling   transmitting stalling errors between the first and the second video signal in signal portions that correspond to a segmented image array of the image, an interpolation error generator with interpolation (34, M 2, f'l etc. ) to generate interpolation calibration errors by interpolation between the calibration errors sampled at least in the vertical direction of the network of zones   segmented images, a means (Ml, Mi ', 56, etc.) for gen-   the calibration compensation signals based on sampled interpolation and calibration errors and means (40a, 40b, 99r, etc.) for providing the calibration compensation signals to the deflection control circuit the second tube of pri ee de vuies to correct the errors of setting of it compared to the first tube shooting.   2) Color television camera with tubes   with an automatic caliper adjustment system.   A method according to claim 1, characterized in that the deflection control circuit of the second camera tube (3) comprises a main deflection coil   and an auxiliary deflection bob (98 R) and the   Calibration compensation products are supplied to the coil auxiliary deflection.   3) Multi-tube color television camera with an automatic adjustment system according to claim 1, characterized in that the means generating calibration compensation signals is composed   of a memory (Ml) for recording the compensating signals   storing means and means (34) for modifying the calibration compensation signals stored in the memory   function of calibration errors, sampled.   4) Multi-tube color television camera with an automatic calibration adjustment system according to claim 1, characterized in that the error sampling means comprises a counter (27, 34) which selectively increments and decrements its content. half of the previous count state according to the detected error polarity to determine the value   final calibration error, sampled.   A multi-tube color television camera with an automatic pitch control system according to claim 1, characterized in that the error sampling means comprises a memory 43) having a set of addresses respectively corresponding to the segmented image areas.   ) Multi-tube color television camera with automatic adjustment system   according to claim 5, characterized in that the gen-   calibration error, with interpolation, comprises a memory (M 2) with addresses which correspond respectively to calibration errors, with interpolation   and sampling errors sampled.   7) Multi-tube color television camera with automatic adjustment system   according to claim 1, characterized in that   carries a third camera tube (2) giving a third video signal also corresponding to the picture of the test board and having a respective deflection control circuit (89 B, 98 B and 98 B) and the medium of error sampling (34, M 3, 42) samples the calibration errors between the first and the third video signal (GO, B 0) in the part corresponding to this network to give the other calibration errors, the generator of interpolation error (34, M 2) interpolated   also between other calibration errors, exchange   at least in the vertical direction to give other interpolated calibration errors, the means   generating the calibration compensation signals including   a means (Ml ", Mil" ', 56 etc.) generating other   calibration compensation data according to the other interpolation and calibration errors sampled and   the means providing compensatory compensation signals   includes means (40c, 40d, 99b, etc.) providing the other stall compensation signals to the deflection control circuit of the third picture tube to correct stall errors thereof.   compared to the first tube of shooting.   ) Color television camera with tubes   with an automatic caliper adjustment system.   ge according to claim 1, characterized in that the error sampling means samples the   horizontal and vertical stall errors between   first and second video signals corresponding to these   and the error generator with interpolation   (M 2, 34) ensuring the interpolation in the direction   vertical error between the horizontal   and vertical calibration errors, samples   lonnées. 90) Color television camera with tubes   with an automatic caliper adjustment system.   ge according to claim 1, characterized in that the   generator of calibration errors with interpolation com-   carries a means (M 3, 34) for interpolating upwards and   down from the calibration-sample errors   born in the parts of the video signals that correspond   at the bottom and top respectively   ve the network of segmented image areas.   A multi-tube color television camera with an automatic adjustment system according to claim 9, characterized in that the   generator of calibration errors with interpolation   memory (M 2) with addresses corresponding to   the sampled calibration errors and interpolation errors interpolated between and from   Sampling errors sampled.   11) Color television camera with tubes   with an automatic caliper adjustment system.   ge according to claim 10, characterized in that the   calibration errors, sampled and calibration errors   interpolated between and from calibration errors   sampled correspond to all horizontal lines   zontales of a frame of the video signal and the memory (M 2)   has an address corresponding to each of the horizontal lines zontal.   ) Color television camera with tubes   with an automatic caliper adjustment system.   Ge according to claim 10, characterized in that it further comprises a switching means (67, 70, 77)   having a first and a second state to selectively adapt   the NTSC signal adjustment system   and PAL, the calibration means comprising a means of address-   sage (67, 77) who, for the first state, ensures the inter-   polation of sampled stall errors and interpolation stall errors, and with sampled stall errors, matches all horizontal lines of a frame to those signals which are all temporarily stored at the respective memory addresses (M 2) and in the second state, interpolation staggering errors corresponding to horizontal lines adjacent to intervals between sampled stall errors are recorded at same addresses as the memory.   13) Color television camera with   in accordance with claim 1, characterized in that each of the first and second camera tubes (4,   3) comprises a horizontal and vertical deflection means   shim (89, 82) for scanning the respective image in a vertical succession of horizontal lines, and the error sampling means includes means (42) for spacing the sampling of the stall errors at remote positions on the along lines   selected horizontals which are spaced in the vertically.   14) Color television camera with   multiple pairs with an automatic calibration adjustment system according to claim 13, characterized in that the error sampling means comprises a memory (M 3) with addresses respectively corresponding to the positions spaced along the horizontal lines chosen to record provisionally the corresponding calibration errors and additional addresses at which are recorded temporarily average values of the respective calibration errors at the beginning and at the end of the horizontal lines chosen to determine   calibration compensation signals during horizontal erasure times.   ) Television camera in which you   multiple pairs with an automatic wedging adjustment system according to claim 13, characterized in that the error sampling means comprises means for selectively sampling the horizontal and vertical pitch errors between the first and the second video signal (GO , R 0) in the parts thereof and the means for generating the calibration compensation signals   memory (Mi, Ml ') to record the   horizontal and vertical calibration compensation, respectively, as a function of horizontal and vertical calibration errors, sampled and in accordance with 1-th calibration errors with interpolation in the vertical direction from horizontal and vertical calibration errors sampled.   16) Color television camera with   multiple pairs with an automatic adjustment system according to claim 15, characterized in that the horizontal deflection means of the second camera tube (3) comprises a main deflection coil (89 R) and an auxiliary deflection coil (98 R), means for applying (88, 87, 91) a sawtooth signal to the main deflection coil for horizontal scanning of the second camera tube and means (99 R) for applying to the   auxiliary deflection coil the compensating signals   horizontal calibration read in respective memory   (Mi) in synchronism with the scan.   ) Color television camera with   multiple pairs with an automatic adjustment system according to claim 16, characterized in that the vertical deflection means of the second camera tube (3) comprises a vertical deflection coil (82 R), a means (85) to apply a second signal in   sawtooth to the vertical deflection coil and   dragging the vertical scanning of the second camera tube and means (86a) for adding to the second sawtooth signal calibration compensation signals   read in the respective memory (Mi) in syn- Chronism with the sweep.   18) Color television camera with   in accordance with claim 1, characterized in that the error sampling means comprises a control means (34) for performing a predetermined number of successive operating cycles and the means generating the signals. calibration compensation is a memory (Mi, Ml ') for recording calibration compensation signals and means (34) for modifying the calibration compensation signals stored in the memory   variations in calibration errors, samples   during the successive operating cycles of the error sampling means (M 3 etc.), and the means providing the calibration compensation signals to the deflection control circuit comprises means (56).   to read the calibration compensation signals, recorded   in memory (Ml, Mi ') in synchronism with each other   successive operating cycles of the means of error lining.   19 ') Color television camera with   with a self-adjusting adjustment system according to claim 18, characterized in that   the error sampling means separately samples   horizontal and vertical registration errors between a first and a second video signal in the parts, and   memory consists of memories (Ml, Mi ") for recording   respectively record compensating signals of   horizontally and vertically based on the sampled horizontal and vertical calibration errors and the respective interpolated   of work cycles is higher in the sample-   horizontal stall errors and the generation of the respective stall compensation signals, compared to vertical stall errors when these are sampled.   ) Color television camera with   in accordance with claim 19, characterized in that   the interpolated wedge error generator ensures the in-   terpolation in the vertical direction between sampled horizontal stall errors and sampled vertical stall errors.   210) Color television camera with   multiple pairs with an automatic calibration adjustment system according to claim 20, characterized in that the error sampling means comprises a counter (27 or 34) which selectively increments and decrements its content by one half of the state previous count   depending on the polarity of the error detected to de-   end the final value of the calibration error, exchange tillonnée.