JPS589495A - Registration control circuit of multitube color camera - Google Patents

Abstract

PURPOSE:To increase the data collecting speed when an error is detected, by reducing a prescribed quantity to half each time in case the compensating data is increased and decreased by said prescribed quantity in accordance with the horizontal and vertical shifts between the output signals of a reference image pickup tube and another image pickup tube. CONSTITUTION:An image pickup screen obtained through a color TV camera of 3-tube (R, G and B) type is divided horizontally and vertically, and a reticle is picked up at the center of each divided region. In each divided region, an error signal ER is obtained to show the degree of horizontal and vertical shifts of the R and B tubes on the basis of the G tube. The signal ER then receives the sample holding through a sample holding circuit 16. Then the plus or minus of the signal ER is discriminated by a comparator 26. Based on the result of discrimination, an up-down counter 27 receives an up-down control by a prescribed amount. Then the output of the counter 27 receives a D/A conversion, and a light polarizing current is flowed to a light polarizing coil 31 of the R or B tube. The data collecting speed is increased by reducing the prescribed amount of up- down control to half each time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a registration A1 circuit for a multi-tube color camera equipped with a plurality of imaging means such as a three-tube type (RlG, 13) or a two-tube type (luminance and chroma), and in particular, 1
The present invention relates to a registration 1@fake circuit in which a home screen is divided into a plurality of parts and registration is automatically adjusted for each part.

(The following is a blank page.) Multi-tube color television cameras require extremely complicated adjustments in order to perform registration (alignment of each color) of the f-quadrant tubes. In general.

Although the beam deflection and current are corrected so that the center position of the output image of each quadrant matches, etc.), +i
It is difficult to correct color deviations caused by differences in image pickup tubes such as lI + l image size, 7 existing 11 (linearity, skew distortion, etc.). Create various correction signals to correct the distortion, etc. for each image pickup tube, adjust the gain of F1, and adjust the beam deflection current of each S based on -J4. Registration adjustment was done by following Case 1. Therefore, the side-turning circuit is extremely rough.

Since the cause of color misregistration is an independent pattern, there is a problem that even if alignment is performed in one place on both sides, it will not match in another part, and the uniform resist over the entire screen The present invention provides a registration adjustment circuit for a multi-if type color camera that solves this problem. I will explain.

FIG. 1 is a plan view of a screen illustrating an automatic registration method according to a practical example of the present invention. As shown in Figure 1,
For example, a screen shot by a three-tube (R, G, B) color television camera (11 is in the horizontal direction (11 directions) Bl
It is divided into 7 parts each in the vertical direction (V direction), and 7x7=49
In each area, for example, get a green signal G.
Registration adjustment is performed for the other R'if (red light) and the B tube (-14) using the G tube)'fr-Hanao. At the time of registration, a pattern board with 6+" characters in the center 11 of each divided area, as shown in FIG. 1, is photographed as an object.

Note that a chip in which this pattern is embedded may be placed internally in a television camera, and the pattern chip may be inserted into the imaging optical path by an external operation during registration adjustment.

In each divided region, information for correcting the B tube and the deviations of the B tube in the H direction and the V direction (V deviation, l-1 deviation) with respect to the G tube is detected as described later, and is digitized. It is temporarily stored in the memory area as shown in Figure 2. This memory area has 8 columns in the 11 direction and 7 columns in the ■ direction (8x7
), and each memory element stores correction information for H deviation and V deviation corresponding to each divided area. The second screen that does not correspond to the 11 divided areas (7x7)
An extra column in the 11 directions of the memory area in the figure is provided to store correction data for l (shift and V shift) in the horizontal blanking interval H-BLK.The data in this blanking interval is It may be the average value of the last data of the sample data sequence arranged in , and the first data of the next sample data sequence.

For example, data D14 in the memory area in Figure 2 and the next column (
Average value (D14+D16)/of data D16 of row)
2 is calculated and set as data D15. By inserting +$I positive data in this horizontal blanking interval, the correction applied to the horizontal and vertical deflection currents becomes smoother.

Note that a memory column for storing average value data may be provided for the art dealer blanking section V-BLK as well as for the horizontal blanking section.

Next, with respect to the sample data stored in the memory area of FIG. 2, the intermediate portion between the data is interpolated in the v-column direction, and data for each scanning line is created by approximate calculation. Note that in the H column direction, substantial interpolation is performed between data by analog processing (low-pass filter).

If the number of divisions of the screen for extracting the deviation correction data is too small, the tlll[ of the registration bias will deteriorate, and if it is too large, it will take too much time to detect the deviation data. In the actual example, the screen is divided into 7x7, so in the case of the NT8C system, 36 lines are allocated for one section njj in the ■ direction, and 11311 lines are allocated in the V direction as shown in Figure 6 (for example, between DI6 and D24). The interpolated data 11 to I35 of 65H are calculated by linear approximation. In this case, it is assumed that the detected deviation correction data corresponds to the center position of each divided area. Interpolation calculation is V
7 for the full IE data of misalignment and H misalignment
This is performed for all rows, but the time required for 41-H+ is much shorter than the time required for detecting a shift. Therefore, it is possible to obtain detailed registration adjustment data of treetop turtles in one hour with a small number of samples.

Registration adjustment data corresponding to each line of the entire screen is created by the V column abstraction, and this data is
It is stored in the expanded memory area as shown in the figure.

The memory for this adjustment data has a size of 8 columns in the vertical direction and 256 columns (8x256) in the V direction, and one element has two columns for V deviation correction and I (deviation correction). I″′-ta 5: Remembered.

The registration TJag data stored in the expanded memo+r-ai area of FIG. l1ill (goods) will be made. As a result, each screen size, deflection linearity, skinny distortion, etc. can be corrected and circuit-wise! It is possible to simultaneously process wide range of trapezoidal distortions. It is also easy to automate detection and adjustment.

Next, FIG. 5 is a block diagram showing an example of a circuit for detecting deviation correction information in the horizontal and vertical directions, and FIG. 6 is a block diagram showing an example of the principle of the 1fll control circuit of the registration adjustment section in FIG. It is a diagram. Further, FIG. 7 is a waveform diagram illustrating the operation of FIG. 5.

As shown in the MIJ5 diagram, the color television camera of this 41st edition has six image pickup tubes (green (G), red (ru), and # (B)).
) (3) f4) (G tube, 1 tube, B tube).

) The output G' of the G tube (2), which is the standard for strain adjustment, is higher than the output of the It tube (3) and the B tube! (+
The deflection system is adjusted in advance so that the phase is advanced by T (H: horizontal horizontal circumference 1υ1, T key 150 ns). It shows the four hundred wisdom+++1 of the cross pattern in one, In->q~. Figure 7 G tube (2
) has the waveform shown in FIG. 7B. The output G' of the G tube (2) follows the 1H delay line (5) and the TMl& line (7), is delayed by H+T as shown in FIG. When the registration is correct, the main line fK No. 131
It is in phase with the output RQ% BO of +41 in the horizontal and vertical directions.

The output of the T:I @ extension line (7) is further delayed by the T delay line (8), and the delayed output DLG' (Fig. 7C) and the input of the T sharpening/line are reduced by W, the line (9). ), an edge signal gDG representative of the horizontal edges of image III as shown in Figure 7 is obtained. This edge signal is a signal that has positive polarity when the video signal rises or falls, and negative polarity when it falls. This edge ('M No. 113DG is H) 7 points of changeover switch port 1) is multiplied by 03.
At the same time, it is also supplied to the edge detection n++ 31, where a sampling gate signal SG (FIG. 7 I) is formed at the position of the edge signal.

On the other hand, one is selected by the selection switch 0 for the output of the other R tube t31 t or B tube (4) or Bo. On the other hand (G in FIG. 7) is given to a subtractor t151, where G
The difference between the tube output and the main signal Go is determined. Subtractor (1
The output REG of 9 is based on the standard GW output; the output of the Le tube or B tube for one song + UU positional shift No. 16 representing the horizontal shift Δ1)
Figure 7H). This misalignment No. 3 is caused by
13 and is multiplied by the edge signal gDG. The result is an error signal EIt representing the direction and direction of the horizontal deviation as shown in Figure 7. This is sent to the sample and hold circuit (1f9,
Sampling is performed in the section of sampling gate No. 14 8G described above, and a DC sample-and-hold voltage 8H (Figure J in IIIZ) representing its level and polarity is obtained. Note that the capacitor (1?) coupled to the output end of the sample and hold circuit (11) is a hold capacitor.

The sampling gate signal 8G is sent to the sample hold +61 path ill via the AND gate 0 ladder. This AND gate (1 barrel is opened by the gate signal GE supplied from the terminal Ql through the buffer 2). are formed accordingly.

The output l-1Bo of B tube (3) or B f (4) is
As shown in FIG. 7G, the ineffective urine signal C1o of the Gfi output
In the case that there is a delay (by Δ1 to the right), the sample-and-hold voltage SH in Figure 7 J shows a level corresponding to Δ1 with 1E polarity. As shown in Figure K, when the main signal is advanced (shifted to the right by Δ2), (π misaligned signal [1, W The error number 1 representing the amount and direction of is negative polarity as shown in the Luer diagram M1.
As shown in FIG. 7N, one novel corresponding to Δ2 is shown with negative polarity.

The output of the sample bold circuit (I6) is input to the control circuit 121) based on the position 1a deviation information, and the beam control of the corresponding B tube (3) or 3'4 +41 is performed according to the position 1a deviation information. The device position 2rl is controlled 1. As a result, 14
The tube's star is B yen! As shown in FIG. 7O, the main line signal Go7 output from the G tube almost completely fails. Na r
? Normally, the output level of the GG tube and the output level of the other 1M or B tube are not equal, so the 111Ii due to the output of each
Even if the pJ positions match, the level of the 1<= sign does not become zero as shown in Fig. 7P. However, the error signal E I (, of the output of the multiplier - is As shown, the sample and hold voltage becomes zero because the polarity is randomly reversed at the rising edge and rising edge of the video signal.

In principle, the control circuit mainly consists of comparators l, !, as shown in FIG. bl, up/down (U/D)
Counter shift), l)/A transformer is constructed in one layer. The output 8H of the sample hold circuit 00 is sent to the comparator C11, and the output 8H of the sample hold circuit 00 is sent to the
The polarity of the positional deviation information (in the horizontal direction, to the right or left with respect to the output image of the G tube) cannot be detected. Detection output CO becomes high or low level depending on polarity.
M is given to the up-down control human power U/D of the up-down counter (5), and the clock pulse CK of the counter
For each vertical signal VD given as 12? ) performs a counting increase or decrease operation depending on the high level or low level of the detection signal COM.

The output of the counter surface is given to the D/A converter r'k, and after being converted to pressure fM by the analog control 'T, it is converted into a 1μ current bias and 4 pressures and then sent to the additive circuit C to form a sawtooth shape for 14 directions. It is added to wave No. 18 SAW. The output of the horn 11 arithmetic circuit is given to the drive amplifier (to), and the 1n direction coil C3 of the B tube (3) or B' tube (4) connected to the output is given to the drive amplifier (to).
1) A deflection magnetic current is applied.

Sample hold circuit (11D output (:l Ik”)
Sample hold representing t-shift information-i) E S
If rr is positive, the output CO of comparator (a)
When M becomes the crystal level, the bias and undercurrent of the counter (iM is a little bit, so the bias and undercurrent of the coil Ca1 is a little bit, and the deviation from the output image of (fat) is small. ff The horizontal scanning position of f or BtfI should be moved to the left (lit I). Conversely, if sample hold [rES l-1 is gL polarity] 7, counter 1
The Ht value of 2η increases, and the horizontal scanning position C is shifted to the right.Then, the B tube or the output of the B tube, which was shifted to the left with respect to the output image of the G tube, or the output of the B tube uIIi II ! is moved to the right.

In this way, by repeating the detection of the deviation information and changing the DC bias amount of the deflection and -flow according to the detection result, the positional deviation of the output image of each imaging sensor gradually becomes smaller.
Self-vJ adjustment of horizontal registration is performed. The up/down counter C2η is stopped at the end of PJ@alignment by determining whether or not the positional deviation has converged.

Registration adjustment in the vertical +#i j5 direction is also performed in the same manner as described above. The image edge signal in the vertical direction is the output G' of the G tube (2) in Figure @5.
This output G' is formed by subtracting the difference between this output G' and a signal delayed by 21-I by the IH delay line (5) +61 using a subtracter Q. In order to match the phase with the main signal Go of the output of the standard G tube (2), the output of the output of the +241 is passed through the T delay line (c) to the V (m direct) of the switch (old). ) is sent from the contact side to multiplier f+2. hanging xi
The operation for detecting deviation information by the circuit after O is the same as the operation for detecting deviation information.

Registration 1 adjustment based on the detection of the above-mentioned H deviation and V deviation correction data is performed in the screen division area (7x7
) for both the Le pipe (3) and the B pipe (4). As described above, the deviation correction data obtained in each WIJ area is temporarily stored in the memory area as shown in FIG. Convoluted into expanded memory space like .

FIG. 8 is a block diagram showing an example of the control circuit shown in FIG. 5 for performing this series of data processing.

Note that the circuit in Figure 8 is suitable for the U of a microcomputer.
Consists of PU and memory (rtoM, i is also AM),
The functions corresponding to the up/down counter etc. in FIG. 6 are achieved by the microcombi program.

In FIG. 8, CI)U(central processing unit t)C(
In the display unit and register 4), a counter corresponding to the 7-up counter (5) in Figure 6 is constructed. The output f-t of this counter is f-tapas (
g), launch circuit (to), full jaw g'acs'n, launch circuit (to) by 1 increment, and buffer (39a) ~
(39d) and 1)/A to the corresponding tube (3) or B tube (4) beam deflection device (2) or (2) (5th
(Figure) is given as a registration adjustment signal.

The detection signal COM indicating the direction of 1III image position shift obtained from the comparator (4) in FIG.
0 boat) (40 to the CPU (b), and depending on the high level and low level of this detection 1st signal, cPu3
The #1 value of the counter in a is increased or decreased. The clock pulse of this counter may be the vertical synchronization signal VD used in television cameras, and this clock pulse VD4
! From the clock generator +471 in FIG. 8 to the CPU 34
) will be sent to.

Then, as described above, the beam deflection current is changed by increasing or decreasing the count value of the counter, and furthermore, the direction of deviation of both front positions after the change is detected by the detection system shown in FIG. By repeating this, the amount of positional deviation of the image is gradually reduced, and in a predetermined convergence state, correction data corresponding to the matching point of registration is obtained from the counter. This correction data is stored in the corresponding address of random access memory 8 (3).

Memo IJ-M3 has the area (7x8) shown in Figure 2,
The registration adjustment value obtained for each of the llllllfll divided areas in Figure 1? l++ IE
Data is written to the corresponding address. Me IJ
The control address corresponding to FIG. 2 of M3 is supplied from the address counter 1.11) through the buffer f+31441 and the address bus (45)f. Also the first
The gate pulse GE that specifies each of the divided regions in the figure is generated by a gate pulse generator (1 section), and the tone (111
is sent to ANDGATE (119).

When the data ejection for one channel (1 (,!Moss or B?Z ■ deviation or ToI deviation) is completed, the memory M3
Contents! ′! The CPU (
(b), where interpolation calculations are performed to interpolate between data in one column direction. The Hashimoto program necessary for interpolation calculations is written in read-only memory (ROM) M4. Also, a part M3' of the memo +)-M6 is used as a calculation register. Kamama Choka is data bus 61
, are written to the random access memory M2, which has a memory area of π4 in the buffer (ll).

Next, memo 9-M2 + 1 corresponding to the entire screen that was erased
The oil IE data for the channels is read out in synchronization with the beam scanning of the image pickup tube, passes through all the jJ++ 'g devices (3η, the latch circuit (to), and goes east to the buffers C59a) to (39
d), the deflection S of the corresponding image pickup tube through each of the D/A transformers (4tJa) to (40d), s, y<
At is given. As a result, both image outputs whose registration has been adjusted based on the contents of Memo +7-M2 are obtained.

A second registration adjustment is performed on this image output. The successive address of memory M2 is C.
It is supplied from the PUE34 via the address line (449) and the buffer (1→).The control of writing and reading of the memory M2 is performed based on the output of the Case 1 circuit 11!6.

The secondary correction data required for the second registration and 4 adjustment is transferred from the up/down counter provided in the CPU α◇ to the data bus CG and the latch circuit (7
) and sent to the full-jaw tracker (37), where it is added with the previous supplementary iE data from memory 812, and then
As described above, 1) /A is converted and applied to the deflection device of the corresponding image pickup tube. The 2-bit correction data detected by the increase/decrease in the number of up/down counters mentioned above is in Memo I.
It is stored in the corresponding address of J-11J5. This 2
The next -+ll positive data is the fine 1 for the 11th adjustment.
It is an i14 integral.

When the second registration and adjustment for each of the screen division areas shown in Figure 41 is completed, the contents of memory M3 and the contents of memo +7-M2 are added in CPUC, and the history is added to memory P% (3). Next, interpolation of the rin iE data in the memo II-MS in the V column direction is performed by the CPU c+, +), and the interpolated data is stored in the memory M2.

The above-mentioned registration xl is performed twice for the V deviation of Rw13) and the B tube (4), and 4 times for the H deviation of the IIS. Extremely accurate correction data can be obtained by performing readjustment based on the result of the previous register storage date adjustment. In particular, in the screen split area shown in Figure 1, correction data is statically detected by treating each area as the center of the screen and applying a DCO) uI 6-direction bias to each missed area. When synchronized with the beam scanning and given to the t-equipment of each mt quadrant, the 1-C1 beam is affected by the frequency value temporality (dynamic characteristics) of each mt quadrant and the 1-C1 beam is corrected. Therefore, by readjusting the registration as described above, it is possible to bring this closer to zero within the range where the adjustment error can be detected. can.

Furthermore, when the correction data corrupted in the first registration GTM is read out in synchronization with beam scanning and given to the deflection device as a correction signal, this iE signal is a high-frequency signal having a frequency at least four times the horizontal scanning frequency. This high frequency signal causes distortion due to the frequency characteristics due to the inductance of the deflection system of the image pickup tube. However, in the detection of correction data excluding the distortion adjustment, each r(i
For each of the 7 divisions, DC No. 16, which is determined according to the increase or decrease in the count of the up/down counter in C1) U (mouth), is given to each deflection device as the sleeve 1E signal, so this IA signal is used to control the deflection system. It is not affected by the frequency characteristics of #. Therefore, extremely accurate correction data can be obtained.

In addition, in the second and subsequent registration adjustments, the output 0) 1 correction data of the memory 12 and the 2 correction data of the 1α flow created by the first CtU input are added in the full adder C shown in Fig. 8. Therefore, add 'n. Results may overflow. For this reason, the carry output of the whole jaw's mouth is detected by the overflow 1 inducement circuit (g), and when an overflow occurs, it is detected from the l1 circuit I am trying to reset the overflow condition by sending it to .

The correction data detected and interpolated as described above and stored in the memory M2 is passed through a selected one of the latches and buffers (S9a) to (59d). Compatible memory M1 to M1m 1
transferred to. These memories M1 to M1 have the same area as memory M2 (Fig. 4), where Ml is the V channel of R tube (3), M1' is the H channel of )L\f, and M
1 KaBW (4) no V Chi”rnet tv, M 1 KaB
it(7) is assigned to the H channel, respectively. In addition, the buffers (39a) to (59d) are controlled to each channel (几/V,
R,/)I%B/V,B/H).

Also, memory M1~M1'' is C/8 (chip select)
The signals are selected corresponding to each channel by the control signals given from the decoder 6 (game) eii'2, 4M. These decoders c+3654) are CPU04
) through the input/output circuit +49.

The contents of memo IJ-M1 to M1 are as follows:
The beam deflection operation is carried out synchronously in response to an address signal applied from (g) through the address bus 6η,
Each image pickup tube 1:3) (41 deflection value M a r!'v
given to. As a result, registration adjustments are made in the V and H directions of R tube +3) and B tube (4) using G tube 12) as a reference, and Eirin output without color shift is output from Telepicanora (,1). .In addition, each memory M1
~M1 writing and continuation control are performed by writing/reading.
R/W) '+ulj (MJ (MJ) is performed in response to the IvijO11 signal supplied from K generator 6η through gate □□□.1hlJ control (d generator 6?) is controlled by IMI Vh (4 tank And a write/read f111J control signal is formed based on the output of the clock signal generator 6.

Next, i register (9+suite) is a flowchart 1 which summarizes the adjustment operation in the above-mentioned registration. ), the brisset/soto data is written to the memory M2, and at step 11! (101), the preset data of M2 is transferred to each of the memories M1 to M1''.

This preset data is, for example, 80 I-1 (16 luck display) Te; Ih Tsu T-yo <, Kono case, l) / A
*The output of converters a (40a) to (AGd) is zero, and the beam deflection current correction of each image pickup tube is zero.Next, 'F11 disconnection (102) detects whether or not there is a start signal. will be held. This start signal may be, for example, the 1g signal generated by the operation of an automatic centering circuit that aligns the center voltages of the R tube and GW screens with the G tube as a reference. This automatic centering circuit may have the same circuit configuration as shown in FIG. 5 and FIG. It is provided for the purpose of making it as small as possible. Note that when the centering is performed manually, the configuration is such that a start button is operated to generate a start signal when the manual adjustment operation is completed.

Next, in process (10), one channel of the four channels (adjustment of V deviation and H deviation of R tube and B tube is specified), and further in process (104), preset data is written to memo 17-M2. This preset data writing is performed in order to reset the contents of the memory M2 before the start of the 6th shot of registration adjustment for each channel.
The preset data is non-adjustable (corresponding data 8
0E ((16 □ Shin). This preset l is the result of the previous registration adjustment.
This recorded data will be erased. Next @ Ri (105
) to adjust the number of registration adjustments (1st key, 2nd I
A counter (I is also an hfGI loop counter) is preset.

The channel specified in the arrow processing (103) is
If it is [(, then the data i10 subroutine (107) for importing the 4" deviation correction data to the memo IJ-M3 in FIG.
) is carried out, and the subroutine (10
B) is carried out. When the interpolation plate is finished, 11. W.G.I.
The judgment is whether the count value of the loop counter is 4 or not (10
9), and if it is not 4, return to the correction data import subroutine (107). This loop is looped back four times, and registration adjustments from primary to quaternary are performed. After completing the four adjustments, process i (ii
o) The data in memory M2 corresponds to f Lua 1 Mo IJ
-Ml ~ Ml” (14% 13, 1 VhH (7)).

Registration l in the V direction in the above judgment (106)
! If the branch is 14, the same data acquisition and interpolation subroutines (107) and (108) as in the H direction are performed (1), and the IL ju G I loop is
A determination is made as to whether or not the process has been performed twice. rrtm in V direction
As for the positive, since the 1iIll elementary level in the horizontal and vertical directions of the screen is originally the horizontal scanning line, it is possible to obtain a result that satisfies #1 by adjusting the registration twice.

In the process (110), if the contents of the memo IJ-M2 are transferred to the corresponding memories M1 to M1, the judgment (1
At step 12), it is determined whether or not the adjustment of all four channels has been completed. If NO, the process returns to step 104 and adjustment of the remaining channels is started.Registration using the circuit shown in Figure 8 All adjustment operations are completed.

Next, FIG. 10 is a flowchart showing details of the data I10 subroutine (107) for taking in correction data in FIG. Further, FIG. 11 is a diagram showing a data convergence condition when detecting deviation correction data.

When entering the data I10 subroutine, a memo U-M ! corresponding to each divided area in FIG. 1 is displayed. The control address of I is set (process fi120). The set 1lII control address S of memory M3 is output to the input/output circuit (PIO) (It) in FIG.
sent to. Gate pulse generator (for 4 forces, this iii
A gate pulse GE representing the position of the s1ti1 plane divided area is formed in accordance with the eight control addresses and the address synchronized with the travel of the beam output from the address generator (to). In the projection system shown in FIG. 5, tub iE data of V deviation and Fl deviation is detected for each divided area.

Next, at T41 cut (122) in Figure 10, I(, 1!3 G
The count value of the I-loop counter is determined, and if it is the first registration adjustment, the edible range (step width) for one count increase/decrease of the measurement up-down counter in the CPUC 34) is determined by 801 ((164) In order to make the data 80)f in register rs in CPU04)
is loaded (process 123). Then, the initial value of the up/down counter is preset to 80H (processing 124
). In this alternative, the output value of the up/down counter becomes 80H as shown in Fig. 11, and the value for the beam deflection of the image pickup tube to be adjusted is zero. Step 11g of counting increase/decrease is 8 D H
It becomes. The contents of the counter are transferred from the CPU (b) in FIG. 8 to the latch (1) through the data bus (9) in a process (125).

The output of the latch (2) is converted into a D/A'R signal and applied as a correction current to the beam deflection system.

In the next process, the data in the register r3 that stores the change in the counter is halved (process 126).

Then, in judgment (127), the presence or absence of the vertical synchronization signal VD sent to the CPUG4) is detected. If detected, the up-down information (shift correction direction The instruction data) U/D is taken into the CPUG 4 from the input/output circuit I in FIG. 8 (processing 12B). This up/down information is determined in judgment/129), and if it is up, the up/down counter is incremented by r3 (=80H/2) in process ff1 (130). The up-down information is down], ge, processing (
131), the count value of the counter is decreased by r3.

Next, the step width 15 of the counter is 4L for 1 bit.

A determination as to whether or not it is made is made at judgment M (132). 1 lock (1
If 32) is NO, the process returns to step 125 and the contents of the counter are transferred to the latch register. As a result, as shown in FIG. 11, for example, a correction t(+r3/2) corresponding to the increment of the counter is applied to the beam deflection system. Thereafter, as described above, the step width r5 is halved to i for each idl iE, and the count value of the counter is increased or decreased by r3 in accordance with the U/D data. This up/down counter increase/decrease loop is repeated until r6 becomes 1 bit, and the correction data of the counter output is +r3/2, +r3/4, -r5/ 8, -r
5/16......and converges to the target f+tf 8.

When r3=1 is reached, the step width of the counter is reduced by 1 bit (decision 127'
), U/D data coloring (processing 129'), uptown determination (determination Wr129'), and transfer of the counter to r3 and the counter contents to the latch (processing 125'). When this 1-bit increase/decrease is repeated four times as shown in Fig. 11, this is detected in judgment (133), and it is assumed that the f-Sanno data has almost converged to the target 11th area, and the process i1! At (134), the contents of the counter are stored in the corresponding tt+lJ address of the memory 813.

This completes the first registration A11 for one of the divided areas in FIG. 1, and then the process (
135), the I control address of the memory M3 is incremented by one, and registration adjustment for the next divided area begins. Then, the processing loop from ■ to ■ in FIG. 10 is repeated until the completion of adjustment for all addresses is detected at check @ (156).

When the first registration adjustment is completed for all (49) of the 49 divided areas shown in FIG. 1, and the correction data required for &A adjustment is written to all addresses of memory M3. , then the horizontal blanking section H-Bl of Maki 1 diagram
, K, the average value data before and after the address I of M3 is written (process 167). This allows the first
The data I10 subroutine (107) is completed,
Return to the main program shown in Figure 439. In the main program, the data interpolation subroutine (108
) is performed, this inter-track data is stored in the memo IJ-M2, and the beam deflection thread is controlled by the (starting data) of this memory M2 and the registration ai49 is executed.
1. Ru.

When the 11th registration adjustment is completed, I
The LFIGI loop counter is incremented by one, and as shown in the main program of FIG. 9, the data returns to I10 Suffl Retin (107) and the second registration adjustment begins. At the second registration morning, the first
Branching from the judgment (122) in Figure 0 to the processing (138),
The first correction data is output from the corresponding control address of memo IJ-M3 to CPUI: (◇), and then the next tel is disconnected (
139), when the non-adjusted data (80H) is set to zero, the +E negative (larger or smaller relative to the non-adjusted data) of this correction data is determined, and if it is 'itE, 8D H is obtained from the 611 positive data in the process (140). is subtracted, and the result of the decrease is written into the register r3 as the dJ variable step width r3' of the up/down counter. If it is negative, conversely, in the process (141), the correction data is ML4ed from 13DH, and the subtraction result is combined with r51.

From then on, the same data processing as the first time is performed, and as shown in FIG.
, r3'/4, r3'/8 . . . The up/down counter is decremented in step widths of number of songs, songs, and so on.

Since most of the registration errors have been corrected in the first step 141, the value S of the counter 111M is small, so the step width of the counter may also be small.

When the second registration adjustment is performed by increasing or decreasing the count of the counter and the secondary correction data is written to the entire area of memo 17 M3, the main program shown in Figure 9 is entered and the interpolation calculation in the direction of the 7th column is performed again. (It will be done.)

FIG. 12 shows a flowchart of the 1111 subroutine, and FIG. 3 is a diagram of a data string in the direction (1) for explaining the interpolation calculation method.

In FIG. 12, first, the address N (0 to 55) j:i: of the memo+7-M5 area in FIG. 2 is set (process 150).

Next, address r3 of memo IJ-M2 in the fnJ diagram.
Set r4 to correspond to N (process aisi). Note that Memo +7-M3 is a one-arrow memory with an address area of 0 to 55, but memory M2 has an address area of 7 as shown in Figure 4.
It has been expanded to include two missing elements in the column direction and H column direction. Next one is here! (Me died at 152nd - M2's memo IJ
-The data for the address corresponding to M3 was recently published.M! 1
added to. None In the first registration adjustment, M2 contains data 8011. Also 2
In the 1f71st registration storage controller adjustment, go to (2 contains the interpolated data of the primary correction data required in the previous adjustment. At this time, M3 contains the correction IE portion for the first primary correction data. Contains secondary correction data.Therefore, by processing flit (152), the memo 17-M3 (
The absolute amount of this correction data is written.

Next, in the process (153), the data at address N of the memo IJ-MS is successively output to the register r1 of the CPU, and around
1,800 m of data is continuously output to register r2 of the CPU. The data of the N address and the N+8 virtual turtle are data that are instantaneously connected in the direction of the 7th column of the screen division area, as shown in FIG. Missing (Divide the data between rl and r2 into 66 equal parts and divide the data into 6th
Interpolated data 11, I2 as shown in the figure...
...... is calculated by edge shape approximation (process 155)
.

The calculation result is at the address provided in Memo +7-M3 (
0 to 65) are temporarily stored in the temporary area M3'.

The interpolation calculation formula is (36-K)r1+Kr2+18 6 , the value of K is changed from O to 35, and the calculation result is M 3
' to the corresponding address. Note that the numeral 18 in this calculation formula is added for rounding. As a result, as shown in FIG. 13, for example, a set of data D16 adjacent in the seven column direction
, D24 are obtained by calculation.

Next, in judgment (156), address data N of M3
For (0 to 55), the upper end of the screen split area (0 to 7),
Classification is performed as intermediate (8-47) and lower (48-55). In the case of the upper end and the lower end, the process is branched into A and B, and extended interpolation, which will be described later, is performed. In the intermediate case, it branches to C, and in the process (157), 1 of the interpolated memory M S'
(Note the contents of a (0-65)! r3, r of J-M2
Transferred to 44 locations. and address N of memory M6
is increased by one (processing 158), and the address r3. of M2 corresponding to the increased N is increased by one (process 158). r4 is sent to srs (process [159)].

Then, in order to perform the next interpolation 11t11I, size M (1
The process returns to process fffl (152) via branch (50). Memo! When the address N of J-M, 5 advances to 55 and the interpolation for almost the entire screen is completed, the judgment (1<SO
), this is determined and the process returns to the main flow shown in FIG.

Fig. 14 is a flowchart showing the extension interpolation of the upper end of the +ihi surface performed in the same section (156) in Fig. 12, and Fig. 15 is a line diagram of the extension interpolation method.
In Figure 4, first, in the process (161), the memo IJ-M5
Calculation memo IJ-M 3' address (
Addresses from 0 to 17) are set, and further addresses (162 and 162) are set.
) Te memo +7-M3' (7) J e ground (56-55)
(7) Address is set. M 3' Ktltt
+k (0 to 17) contains the interpolated data calculated from the upper end data (K = 0) in the process (155) of Fig. 12 for the inner side of the first surface. . Also M 3'
The five locations are storage locations for 9 tons of long-sleeved data.

Next, in the process (165), memory 8i 5' has 0 (K
-0) is loaded into register r1 of the CPU. This 0
The data for the same area is at the top of Figure 2 0, 1, 2...
It corresponds to the data of... M 3 in Nagi ni processing (164)
'Load the address into register r2 of the CPU. When performing extended interpolation by linear approximation, as shown in FIG. 15, interpolated data r2 and data r2' obtained by extended interpolation are at points symmetrical positions with respect to the data "1" at the upper end. Therefore, r2- Since r1=rl-r2', extended interpolation data can be obtained using the formula r2'=r1x2-r2.

In the process (165), the calculation result of the above formula is written into the register r2 again. The calculation result is checked for overflow in judgment (166), and if there is no overflow, it is transferred to five locations in memory M6' in process (16B). Note that if the data of r2 is the 1st address of M6', the J adjacent land of M3' corresponds to the 52et land. If the nasal value overflows, the register r2 is reset to WE F Fi+ (all 1) or 00)□ (all O) in the process (167).

When one extended interpolation calculation is completed, the number of 5 joint locations is decreased by one (processing 169), and K $ 1111 is increased by one (processing 170). -7 and 1 until J reaches 62
After repeating the calculation eight times, when it is detected in judgment (171) that all of J has been completed, the data of J @ +lk (36 to 5!1) in memory M3' obtained by the abrasive interpolation is The data is transferred to address I of memory M2 (processing QJ1172). The above-mentioned extended interpolation process ILa is applied to one of the data at the upper end (once completed, it is returned to the 0 point in Figure 1!12).

Next, FIG. 16 is a flowchart of the extension interpolation of the lower end of the screen division area performed in branch B of judgment (156) in FIG. This flowchart is almost the same as the one shown in FIG. KJ ground (18-56)
The difference from FIG. 14 is that extended interpolated data below the lower end data is arranged in IIt based on the data at the lower end.

As described above, the memory area in Figure 4 (256 x 8)
The interpolated data is fftKed for all of the data, and the calculation results are transferred from the memo +7-M2 to the corresponding memos IJ-M1 to M1 as explained in Figure m9.

In addition, in the NTSC system, the number of scanning lines in one field screen is 262.5, and if the screen is divided into 7 equal parts as shown in Figure 1 and 36 lines are assigned to each section, 6 lines will be scanned in the middle of the screen.
x 36 (interpolated data of t61 is created, and extended interpolated data of 1Bla each is created at the top and bottom of the screen. Therefore, Memo II-M 2 and IJM
1 to M1'' in the ■ direction, 36 x 7 + 1 = 253 addresses are required for data in the screen blanking section V-BLK. In other words, 2 bytes of memory can be used for one channel. Data can be stored.The correspondence between the address in the direction of this memory and the scanning line is 36 for 8!16 x 7 scanning lines.
x7 addresses are assigned, and the remaining one address is assigned to 11 strokes fg as a direct blanking section. In other words, a memory address is assigned to each of 36x7+11=263 scanning lines.

One address in the V direction of the 11th line of the blanking section contains the general upper end data of the data obtained by extension interpolation at the upper end of the screen, and the data obtained by extension interpolation at the lower end of the screen. The average value of the obtained data and the lowest data is highlighted.

This average value data is repeatedly output over the 11 lines. In addition, memory M1~p, mouth'zz and M
The blanking section (11 lines) in the address of No. 2 is shorter than the blanking section of the actual Eizou Eigo in Shooting 111! Since scanning is carried out over a wide range of areas within the blanking period of the video, it is possible to increase the accuracy of correction to the periphery of the screen by performing the registration storage date d1 adjustment also during the blanking period. It's because I can do it.

Note that the area surrounded by a solid line U in the memory area in Figure 4 is NT.
An effective screen for the SC method is shown.

When applying the embodiment of the present invention to a PkL television system, extraction of correction data necessary for registration adjustment is performed in the same manner as described above, but note IJ-M
By changing the correspondence between the V direction addresses of 1 to M i/// and M2 and the scanning lines that form the screen, it is possible to
Efforts are being made to standardize the hardware and software with the AL system. In other words, in the PAL system, the number of scanning lines in one field is 312.5, so if the screen is divided into seven equal parts, 42 lines are allocated to one section, and the direct blanking period is 15 lines, the required number of lines is 312.5. The V-direction address is 42x7+1+4=299, and the number of scanning lines is 42x7+15=309.

Therefore, one field of scanning lines! The shortfall for 112.5 is 4 lines, and for these 4 lines, interpolation data can be created by extending downwardly and interpolating the section at the bottom of the screen during interpolation calculation.

However, as in the case of the N'r SC method, if one address is assigned to one line, two addresses will be assigned as shown above.
99 addresses are required, and one channel's worth of data cannot be stored in 2 bytes. Increasing the memory capacity is undesirable in terms of cost and power consumption.

For this reason, in this embodiment, when using the PAL system, 66 addresses are assigned to 42 lines, and the increment of the address is stopped once every 6 steps, so that the number of lines can be adjusted according to the correction data continuously output from the memory. almost match.

As a result of this processing, the effective screen area of the PAL system becomes almost the same as the effective screen area 11 (1!IIV) of the NTSC system in the memory space, as shown by the dotted line V in FIG.

FIG. 17 is a circuit diagram of address generation 'a (to) for generating an address for reading out the correction data stored in the memo IJ-Ml to M1 in synchronization with the beam scanning of the image pickup tube.
The figure and FIG. 19 are time charts for explaining the operation.

The person in FIG. 18 shows the horizontal blanking section H-BLK. - I3 also indicates the horizontal synchronizer No. 16 14 D used in this television camera. This horizontal synchronizing signal is shown in FIG.
418, the phase is adjusted to yn< in Figure C, and then the PLL rotation is given to W rotation 1 East 9. Since Goo No. 146 GB is formed in the gate pulse generation circuit 443 based on the address generated by Jin's address generator ω, so that Goo No. 211 is left and right symmetrical within the effective screen.
H for the purpose of adjusting the phase of horizontal opening No. 1 I
A phase adjustment circuit is provided.

A clock pulse 16F'H multiplied by 16 as shown in FIG. 18F is obtained from the PLL circuit power.

This clock pulse is supplied to the clock input CK of the 4-bit l (counter), and the carry output F'[-1 (horizontal frequency, Fig. 18E) of this counter is fed to the inverter Fi!9 as shown in Fig. 18 (PLLu The clock pulse 81i'H shown in FIG. 18G is output from the least significant bit of the counter fi4).
is obtained. This clock pulse is used as a clock for creating an address when reading H deviation correction data from the memory.4'1. Ru. Further, the upper 5 bits of the counter 1 become iAO to VMA2 to successive addresses (2) of the 15-axis of the V shift 111 positive data memory. This address is 0 to 78 within the horizontal circle as shown in Figure 18.
? Walk/River.

Next, FIG. 419B shows the direct synchronization signal VD used in this television camera, and A skips the first episode direct blanking section V-BLK. ;T pull 4J19 Figure C shows water - °, J, L same number 11 bar No. 111). The 1 α phase adjustment circuit + 1 fathom is provided in the same way as the lfSγ (0 adjustment 1! 1 is lit, and this timing signal is used by the V blanking (V-BLK) counter i for setting the blanking section of the read address.
It is supplied as No. 1 Kogli Set Itt. °V again
Phase adjustment circuit name (V timing 1pt No. V made in 9)
D2 (19th section) is given as a set signal to flip-flop 11181 for creating a V blanking signal. This tree flop feeling Vj-'vRt7
) V ti counter (69a) (69b) flil
It is provided for Jff1ll.

The V -BLK force '77J'1fiO is shown in Figure 19F.
Thus, the V timing value number VD1+ is preset to the count value 4. This preset data P8 and NTSC/PAL are given to this counter.
It is determined by the high level signal obtained from the changeover switch CII. V - B L K counter liθ count 1
11t increases with each clock pulse E'H (horizontal frequency) given through the buffer (rυ) from 0 to H count increase, and when the count value is 15, g In addition, the lock pulse F11 is given to the enable power of the counter, and the clock pulse 161''), multiplied by 16, is given to the clock power through the buffer 0.

Since the carry pulse 15CA of the counter N)η is given as a clear pulse to the flip-flop tea, a blanking pulse B L having a width of 11 tons as shown in FIG.
K is obtained by spinning the clock F11. This blanking pulse is given as a clear signal to each of the V counter II (69a) (69b), so the V counter receives the blanking pulse nLK as shown in FIG. 19I.
After (b41910) returns to a high level, the count increases in the HjA11 period. Note that the V counter (69a) (69
b) each has 4 bits and is connected to the tiles in a 1μ column.

The seventh clock pulse is 1611' ii, but the enable count output of the counter (69a) is V in the memory area in FIG. 4 for successively outputting %V deviation correction data.
It is used as the axis address VMA~VMA10 (8 pits).

As described in 4L, 1 (counter; (and V counter (65) a) (69b) Te formation g Letter V 7 F
L/, X V MA O ~ VM person 10 is a memo of Figure 8! Given to husband and wife of J-M1 and Ml, R'# and B-
71 vr deviation correction data is read out.・Also, the V address is 111! A latch circuit consisting of a D flip-flop of I is given to the latch circuit II% (75a) (75b), and the clock
It is sent as an H address at the rising edge of PIl (m181-G). Figure 18 I is l (HI of address
11] Component 1-IM A O ~) shows the change in gait a of 1 MA2.

As shown in 1 and I in FIG.
■Sequential misalignment correction data addresses VMAO to vMA1
0R:it, 8F'i (created with a phase delay of half a clock cycle. In other words, when reading the oil data from the memory, converting it to D/A, and applying it to the deflection system via the low-pass filter, the vertical Since the delay (time constant) of the deflection system and the + deflection system (!: Terror-pass filter) is different, this delay is adjusted using a phase difference of half a clock.

18+ and 4J are used to detect the above-mentioned successive address V k1 person or HMA and the screen division area (0, 1, 2......・・・・・・
The gate signal Gfi! generated by the gate pulse generator 14 in FIG. 8 based on the address S\A representing .
A part of (6 and 0) is shown. F. Registration a! based on the correction data as described above. When performing 4 adjustment, the delay of the low-pass filter at the time of D/A conversion must be taken into consideration. Therefore, i leaked address VM
A and HMA are sampling gates (
It is created with a phase that is more advanced than No. 1 G J4).

Next, a case will be described in which the television camera of this example is installed and operated in the L'AL system. FIG. 19J shows the vertical blanking section of the FAI signal. If you use 114 for a PAL system like you already know,
The section 151 (in the blanking section) is assigned to the blanking section when reading the memory.
The changeover switch f70 in FIG. 7 is connected to the PkL contact side to form a low level preset number 1, and the preset data of the V-BLK counter 61η is changed. As a result, V
-1'3LK counter output is V timing signal VDI (
gl 9 D), the t value is preset to 0 as shown in FIG.
do.

Therefore, the Q output of the flip-flop is 15CA, which is the carry output of the counter from the timing fs to VD2.
The V counter (69a) (69b) is cleared during this 15H period, and its counting operation is prohibited. And carry output 15CA
When the flip-flop state is reset, the clearing of the V counters (69a) (69b) is canceled, and counting from 1 to 255 is performed as shown in Figure 19.

On the other hand, the low level output of the changeover switch (71) is applied to the enable power Tg of the 4-bit 6/7 counter qη via the inverter σe, thereby making the counter q7 in the operating state. This counter σD uses clock pulse 1<5F)I as a clock, and clock pulse ? )( is the count enable manual power (pm) and "C" is used, so the counting operation is performed at the horizontal frequency. 9 is given as the preset data 138, and as shown in FIG. The number of stitches is counted up to ~15, and a carry output CA is generated at the count of 15. This carry output of the counter σD is output from the inverter σ and the negative logic OR gate σ.
1 to the clear human power CLR, the counter is counted again (preset to 9) in synchronization with the horizontal synchronizing pulse FH after clearing, as shown in FIG. It works as.

The carry output CA of the counter ση is inverted by the inverter σ barrel and then given to the enable human power PE of the V counter (69m), so when the 1lta value is 15, this V
The counting operation of counter C69a) is interrupted.

In addition, the output of the inverter 171 is also given to the AND gate (to), so the gate & car is set to 4 and the V counter (6
The clock Fl (1IIi) applied to the enable manual PE of 9b) is cut off, and the counting operation of the Iv counter (69b) with a count value of 15 is interrupted.
■ Counter (69a) (69b) as shown in the 19th diagram.
) is paused once every 71(), and V at v
x V M A '5 ~ V M A 10 it 5
．． 6.6.7 ・-・-Songs 11.12, 12.13...
When the address is incremented six times as shown in . . . , the same address is generated twice.

Therefore, in application to PAL system, Memo IJ + M1
71. The contents of ~M1 overlap with the previous line for one line out of seven lines.71. Ru. As a result, memory M
42 runs f for 62 addresses on the v axis from 1 to M1
ffl will be allocated, as shown in Figure 4 (
, Same as NT8C system ・Floating memory (256x8
) can cover the effective screen of the PAL system.

Next, FIG. 20 is a circuit diagram of the direct deflection system of the television camera of this embodiment, and FIG. 21 is a circuit diagram of the horizontal deflection system.

Addresses VMAO to VMAI for reading the V Zureura old data created by the address generator (to) in Figure a417
OGt memo +7-Ml (R/V), Ml (B/V
), and the address HM A O-HM 10 is given to the memory M1' for successive output of I-1 deviation correction data.
(R/H) and Ml (B/H), and correction data is outputted at IfI°C in synchronization with beam scanning.

The outputs of Ml and Ml are D/A variables (40a) (40
c) and is applied to the terminals (81a) (81c) in FIG. 20 via a low-pass filter (not shown). Also Ml, Ml
The output of is passed through the D/input converter (40b) (40d) and a low-pass filter (not shown) to the four outputs (81b) in Figure 21.
(81d).

As shown in Fig. 20, the ■deflection system is <+'(t t2
), 几"t t3) &hiB"II (4)ノV
<m direction coil (62 (J) (821L) (82B)
Each of them is equipped with a class A or B N amplifier (83G
) (83R) (8313). ′?
! r (-The same coil has a resistor (84G) (841) (84
114 B) are connected in series, and the voltages of these I terminals are fed back to the amplifier (83G) (851 and 8313), so that the amplifier input terminal is connected to the resistance It of these resistors.
OJ where the ti flow like divided by & is bIL to the no coil
J semi(D G 'ff (7,) :j 4 /L/
(F32G) i-', 1; 177' (8
5G) has a sawtooth wave generation circuit +1<i) lko1? is formed in synchronization with the direct assistance signal VD], ta1fξ
A serial sawtooth signal V-9AW is provided. ′
B tube and the amplifier that drives the B tube (8511,) (8
5B) is the addition of the above sawtooth wave signal IL? l road (IB6
a) Given via (R6b).

These adder circuits <86s) (8Sb) are
A registration adjustment number 1 is given from 1a) (81c), and the registration adjustment in the direction ① of the B tube and Bg is thereby performed. Each 1t'v let deflection coil (82G) (821st (82B)) has a frequency characteristic, so V has a component several times as large as one horizontal frequency.
Registration for deviation correction fA41 The bird area of No. FS may deteriorate. However, this deterioration can be compensated for by performing 1i1 (registration re-alignment) as described above.

In the horizontal sieve system shown in FIG. 21, the sawtooth heel wave dtlrt of the horizontal period is changed to
d horizontal deflection coil (89G) (8931) (89B)
It is flowing to. Note that the capacitor auxiliary connected in parallel with the transistor is for integration, and the diode connected in parallel through the flyback transformer (su is for the damper). Also, each horizontal deflection coil (89G) (89L) (8
A capacitor 13 is connected to the deflection/current supply line to 9B).
2/X of the +ll1E transformer (t) and the winding are inserted in series through t. This correction transformer (13/1
The next winding is provided with a sawtooth wave H with a horizontal period, which is generated in the sawtooth wave generation circuit (2) in synchronization with the horizontal period HD.
-8 AW is supplied via a gain adjuster (!li) and an amplifier C, which performs horizontal deflection linearity adjustment.

The horizontal deflection coil (89G) (89R) (8913) has a part (tj9cf) (89
n') (t39QO, and by adjusting these, it is possible to adjust the size and center position of the output image of each camera tube. Also, in series with each horizontal deflection coil, Variable resistors (97G), (97a), and (97B) are inserted, and by adjusting these, the approximate center position of the output of the container tube can be adjusted.
The three-tube IjJ variable resistance resistor 714) (97B) may be used as a variable inbegence circuit. C1 The automatic centering circuit described above may be used to align the center stirring of the R and B tubes with the G tube as a reference. .

The horizontal registration of the R tube (13) and G tube (4) is the main horizontal deflection coil (89) (89B).
) inserted in the form of a secondary winding of the auxiliary coil (98B) (
98B) by passing a correction current through it. These auxiliary coils (98R) (98B) are connected to the It channel and B
Channel 1 (Amplifier (9) that uses the deviation correction signal manually)
9R) (99B). By providing such a correction coil, the main deflection coil (89 ratio) (
89B) can be driven by a switching method, and there is no need to use a class A or class 8 amplifier to flow the deflection current, resulting in lower power consumption and power.

In addition, it is possible to make rough adjustments in advance to the I7, = arity, image size, and center position of each image pickup tube for the deflection/low current flowing to the main deflection coil.
1 (98B) The registration 1 Hachi no Ura iE can be smaller, so the drive amplifier (99B)
The output capacity of B) (99B) may be small.

In addition, in the horizontal running ★ section, the main deflection coil (89B) (89B
) are short-circuited by the switching drive circuit and i
Therefore, the energy supplied to the auxiliary coil (98B) (98B) leaks to the low impedance oscillation circuit via the main deflection coil, affecting the magnetic flux of the correction coil. In particular, the high frequency component of the magnetic flux of the 1lli positive coil is placed as an integral action. However, by repeating the re-adjustment of the 2nd, 3rd, and 4th registration regions as mentioned above, it was possible to create a correction (No. 14) that compensated for this @Mr. Noble, and this problem was completely solved. Note that a direct deflection system (also in this case, an auxiliary coil for registration adjustment may be provided).

In addition, in the above-mentioned actual gun example, Tani J81! Although Jlf1 in the V column direction of ÷10 positive data with respect to the scan line is performed using one stroke approximation (first order), second order or sixth order interpolation may be employed.

Also ■ (Although interpolation of the effect direction is not performed, Memo 17-
It is also possible to expand the area and perform interpolation in the F1 direction. 'Also, in general, the r error in registration is large at the periphery of the screen. Regarding the screen splitting problem, please refer to the actual example (7x7
) It is preferable to scrape by an odd number. In odd-number division, a division area is created at the center of the screen, so one main deflection coil (n
As described above, the present invention divides the effective screen area into a plurality of areas (for example, 7 x 7), and for each divided area, calculates the output signal of the reference image pickup tube (for example, the G tube) relative to the output signal of the other image pickup tube (for example, the G tube). Detects the registration error (positional shift of the output image of the container tube) of the output signal of the R tube or G tube,
This is stored in the memo IJ-(M3), and the registration of other image pickup tubes is adjusted using the correction signal corresponding to the output of this memory. A correction signal is supplied to the beam deflection control means while increasing or decreasing the correction data by a predetermined amount in accordance with the detected horizontal and vertical deviations from the output signal of the correction data, and increasing or decreasing the correction data. - Adjusted to approach the target value of John adjustment.

It is possible to quickly and quickly perform error detection.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a screen for explaining the automatic registration adjustment method according to an embodiment of the present invention; FIG. 2 is a diagram showing memory areas for storing misalignment correction data in each of the screen division areas of FIG. 1; Figure 3 is a diagram for explaining the operation of interpolating the middle part of vertically adjacent data in the memory area of Figure 2, and Figure 4 is a memory that stores the registration adjustment data formed by interpolation. A line diagram showing the area, FIG. 5 is a block circuit diagram showing an example of a detection circuit for horizontal and vertical direction deviation correction information, and FIG. 6 is a basic example of the control circuit of the registration adjustment section in FIG. Fig. 7 is a waveform diagram showing the operation in Fig. 5, and Fig. 8g8 is a block diagram of a control circuit that executes each control of detection, storage, interpolation, and registration adjustment of correction data for H deviation and ■ deviation. Circuit diagram, Figure 9 is a flowchart summarizing the registration adjustment operation in Figure 8, Figure 10 is a flowchart showing details of the data I10 subroutine in Figure 9, Figure 11 is data convergence when detecting deviation correction data. A line diagram showing the status, Figure 12 is a flowchart of the interpolation subroutine in Figure 9, Figure 16 is a diagram of the interpolation calculation method, ■ A diagram of the direction data string, and Figure 14 is an extension interpolation at the top of the screen. Flowchart, Figure 15 is a line diagram showing the extension interpolation method, Figure 16 is a flowchart showing extension interpolation at the bottom edge of the screen, Figure 17 is a diagram showing the extension interpolation method, and Figure 17 is a diagram showing the extension interpolation method.
18 and 19 are time charts for explaining the operation of FIG. 17, respectively. FIG. 20 is a vertical deflection system of the television camera of the embodiment. Figure 21 is a circuit diagram of the horizontal deflection system.In the symbols used in the drawings, (1)...
......Screen (2X3X4)...
・・・・Imaging tube (5X6)・・・・・・・・・・・・
1H delay line (9)...... Subtractor a... Multiplier (ti...
・・・・・・・・・・・・・・・Subtractor screams・・・・・・・
...Sample hold circuit (2υ...
......Control circuit (22X23)...
...... Deflection device C)6)...
・・・・・・・・・・・・・・・・・・ Comparator Q7)・・・・・・・・・・・・・・・・・・
Up/down counter (2)・・・・・・・・・・・・
・・・・・・・・・ CPU(40a) ~(40d)
= D/A converter-・・・・・・・・・・・・・・・
・・・・・・Address generator (goods)・・・・・・・
・・・・・・・・・・・・・・・H counter (69a) (
69b) ・・・・・・・・・・・・ V counter 00)
・・・・・・・・・・・・・・・・・・・・・Choice switch ση・・・・・・・・・・・・・・・・・・・・・
6/7 counter (81G) (82B) (82B) =
-V ii Mukai Ile (89G) (89 place (89B)
)...Horizontal deflection coil (98R) (98B)...
・・・・・・・・・Auxiliary coil M3・・・・・・・・・・
......First memory M2...
・・・・・・・・・・・・・・・ Second memory M
1~M11″・・・・・・・・・・・・）l Mo IJ
− is. Agent: Masaru Ueya Matsuzai Modified JP-A-1989-94') 5 (1B) JP-A-58-9
495 (23) 1^1 Ushisho 5s-949 = <2 Japanese Patent Application Laid-Open No. 58-9495 (27) (Order) Procedural Amendment (Method) December 24, 1981 2, Title of Invention Multi-tube Color Camera Registration Tokyo Parts Store Kitashinyo 6-7-A (218) Sony Corporation 6 Number of inventions increased by 7 from 1 amendment, 1 or more drawings subject to amendment - (Voluntary) Procedural Amendment 1982 Relationship with Patent Application No. 106682 dated October 6, 1982 Patent Applicant: Tokyo Parts Co., Ltd. 1 Kitashina Co., Ltd. 6-7 Part No. (218) Sony Corporation 6, Number of Inventions Increased by Amendment 7, Subject of amendment Detailed explanation of the invention in the specification (1)
), "Data D14..." on page 5, lines 15-17 of the statement box.
・・・・・・・・・・・・・・・Calculate ``[Data D
Calculate the average value of 8 and D14 (D8+D14)/2 and correct it to ``. (2) Correct "column 256" in line 11 of page 7 to "line 256." (3) Correct "element" on page 7, line 12 to "address area". (4), "G pipe, R pipe, B pipe" on page 8, line 11 of the same page is changed to "
Correct to “B tube, R tube, G tube” 〇(5), same page 8, lines 12 and 20; page 14, 10
Lines and 14th; Line 22j1118; Page 51 2
Correct "G tube (2)" in each row to "G tube (4)". (6), "Figure 7 E" on the first line of page 9 is changed to "Figure 7 F".
Correct. (Power, p. 9, line 4 and 22g, line 17, “(3)
(4)'' is corrected to r (2) (3) J. (8), page 9, line 19; page 11, lines 6 and 17; page 16, line 2; page 22, line 2 and line 187(2); page 51, line 6 Correct each "B tube (4)" to "B tube (2)". (9), "Right shift" in the 8th line of page 11 is corrected to "Left shift". (10), page 15, line 11, "UPU and memory (ROM, RAM)" is changed to rcPU and memory (ROM).
, RAM). ■, l'-CDUJ on page 15, line 15 [CPUJ
Correct. (1no, page 17, lines 6-7, “Address...
......(43 (44) and "[cpuc+4
),! :Corrected to l. (1311 "Basic program" on page 17, line 17 of the same is corrected to "program that controls the program and the entire system.") 11 "Written." In this operation, the address for memory M2 is set by the CPU (34) with the buffer (44) open.
It is given well. ” Kasumi, page 18, line 9, “As a result,” [For this operation, the buffer (431) is opened, and (3) the address for memory M2 is stored in the address counter (
40 will be given to you. As a result, the following is corrected. a01, page 18, lines 12-14, ``Nao memory...
......, will be supplied. ” to be deleted. aη, on page 19, line 11 of the same page, ``further'' is corrected to ``again.'' 08), on page 26, lines 6 and 5, [CM) J is corrected to r(Go) J. (11, p. 25, line 17 (7) rR, BXVXHJ
Correct to 1'-R/V, R/H, B/V, B/HJ. (To) Correct "divided area" in the first line of page 27 to "one of the divided areas."しυ, on page 27, line 10, ``kore'' is corrected to ``kore''. 03, page 61, line 20, “8DH from correction data”
Correct the data from rFFH (all 11”) to “correction data”. ■ Teng, page 62, lines 6-4, “From 80H...
. . . r3" is corrected to "r3J as the correction data indicates that the counter is variable. C! Rotation 6th figure". (c) "62," page 37, line 9 and page 50, line 1.
" is corrected to "66". (2e % 5th 3rd TZ 1 4th line CD r
Correct "G pipe (4)" to "B pipe (2)". −1 above

Claims (1)

[Claims] The effective screen portion is divided into a plurality of areas, and for each divided area, all registration errors of the output signals of other image pickup tubes with respect to the output signals of the reference image pickup tube are detected, and this is stored in a memory. In a registration adjustment circuit for a multi-tube color camera, which supplies a correction signal according to the output of the memory to the beam deflection control means of the other image pickup tube, the circuit for detecting the registration error controls the beam deflection control means of the other image pickup tube. means for holding registration correction data applied to the means; means for detecting horizontal and vertical deviations between the output signal of the reference image pickup tube and the output signal of the other image pickup tube; and the deviation detection means. means for changing the data held by the holding means by increasing or decreasing the correction data by a predetermined amount according to the output of the holding means, and detecting the deviation and changing the correction data alternately. The extraction pressure data as the registration error is obtained by repeating the process, and each time the step width of the increase or decrease of the correction data by the changing means is sequentially halved. Registration adjustment circuit 0 for a multi-tube color camera, which is provided with an adjustment means such that the correction data asymptotically approaches a target value for registration adjustment.