JPS58131882A - Registration adjusting circuit for multi-tube type color camera - Google Patents

Abstract

PURPOSE:To obtain highly accurate data quickly in less adjusting processes, by predicting the shift between a control variable of beam deflection due to a compensation signal and the required adjusting amount to a target based on the compensation data, and weighing the compensation data based on the result. CONSTITUTION:When a sample hold voltage SH representing position shift information of an output of a sample hold circuit 16 is positive, an output COM of a comparator 26 goes to a high level and the count value of a counter 27 is decreased. Thus, a bias current of a coil 31 is reduced and the horizontal scanning position of an R or B tube so as to reduce the shift of a G tube to an output picture is shifted left. Inversely, when the SH is negative, the counted value of the counter 27 is increased, the horizontal scanning position is shifted right and the output picture of the R or B tube shifted left to the output picture of the G tube is shifted right.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a registration adjustment circuit for a multi-tube color camera equipped with a plurality of imaging biofilms, such as a 6-tube type (R%G, H) or a 2V type (luminance and chroma). In particular, the present invention relates to a registration adjustment circuit that divides an imaging screen into a plurality of parts and automatically performs registration adjustment for the husbands and wives.

A multi-tube color television camera requires extremely complicated leg adjustment in order to register each image pickup tube (positioning each color). In general.

%The beam deflection current is corrected so that the center position of the output image of the image tube is adjusted, but the angle of view (@rotation of the image with respect to the center)%
Distortion at the periphery of the screen (keystone distortion, pin distortion, etc.), image size,
Non-linearity of scanning, each valley of skew history temple? It is difficult to correct color blur caused by differences between NL imagers. Conventionally, various correction signals are created to correct these distortions that cause color shift, the gains of these signals are adjusted for each image pickup tube, and the beam deflection of the container tube is adjusted based on the adjusted signals. Registration adjustment was performed by controlling the current. Therefore, the control circuit is extremely complicated, and each cause of color misregistration is an independent phenomenon, so there is the disadvantage that even if alignment is made in one part of the screen, it will not match in other parts. It has been difficult to achieve uniform registration across the entire screen.

The present invention provides a registration adjustment circuit for a multi-tube color camera that solves this problem, and embodiments thereof will be described below with reference to the drawings.

FIG. 1 is a plan view of a screen for explaining an automatic registration method according to an embodiment of the present invention. As shown in Figure 1,
For example, the imaging screen (1) of a 6-tube (R%G, B) color television camera is divided into 7 parts in the horizontal direction (H direction) and vertical direction (V direction), and 7x7 = 49 pieces. In each area, for example, with the image pickup tube (G tube) that obtains the green signal G as a reference, the other R tube (red signal) and B tube (green signal)
Registration adjustments are made for the. When adjusting the registration, as shown in Figure 1, a pattern board with a 6+" character written at the center of each divided area is imaged as the subject. The chip on which this pattern is written is placed inside a television camera. The pattern chip may be built into the image pickup optical path, and the pattern chip may be inserted into the imaging optical path by an external operation during registration adjustment.

In each divided area, information for correcting the deviations in the H direction and ■ direction (■ deviation, H deviation) of the R tube and B tube based on the %G tube is detected as described later, and is digitized as shown in Figure 2. It is temporarily stored in a memory area such as This memory area has a size of 8 columns in the H direction and 7 columns (8x7) in the ■ direction, and each memory element stores correction information for H deviation and ■ deviation corresponding to each divided area. An extra column in the H direction of the memory area in FIG. 2 that does not correspond to the divided area (7x7) of screen (1) is provided to store correction data for H deviation and ■ deviation in the horizontal blanking interval H-BLK. It is being The data in this blanking interval may be the average value of the last data of the sample data series arranged in the %H force direction and the first data of the next sample data series.

For example, the average value of data D8 in the memory area in FIG. 2 and data D14 in the next column (row) (D8+D14) /
2 is calculated and set as data D15. By inserting the correction data for this horizontal blanking section, the correction applied to the horizontal and vertical deflection currents becomes smoother.

Note that a memory column for storing average value data may be provided for the vertical blanking section V-BLK as well, similarly to the horizontal blanking section.

Next, the n sample data stored in the memory area of FIG. 2 are numbered in the V column direction, the intermediate portion between the data is interpolated, and data for each scanning line is created by approximate calculation. Note that in the 8th column direction, substantial interpolation is performed between data by analog processing (low-pass filter).

If the number of screen divisions for extracting deviation correction data is too small, the accuracy of registration adjustment will deteriorate, and if it is too large, it will take too much time to detect deviation data. In the example, the screen is divided into 7x7, so...
In the case of the N 'II' 8 C system, 6 lines are assigned to one section in the ■ direction, and 6 lines are allocated between adjacent data in the ■ direction (for example, D16 and D24) as shown in FIG.
Five pieces of interpolated data 11 to I35 are calculated by linear approximation.

In this case, it is assumed that the detected deviation correction data corresponds to the center position of each divided area. Interpolation calculations are performed for both the V deviation and H deviation correction data in the entire V column direction, but the time required for the calculation is much shorter than the time required for deviation detection. Therefore, highly accurate registration adjustment data can be obtained in a short time with a small number of samples.

Registration adjustment data corresponding to each line of the entire screen is created by v-column interpolation, and this data is
It is stored in an expanded memory area as shown in the figure. The memory for this adjustment data has a size of 8 columns in the H direction and 256 columns (8 x 256') in the ■ direction, and stores two data for ■ deviation correction and H deviation correction in one memory address area. ing.

The registration adjustment data stored in the expanded memory area of FIG. 4 is read out and converted into an analog correction signal, and the horizontal and vertical deflection currents are controlled based on this correction signal. As a result, it is possible to simultaneously process corrections for the screen size, deflection linearity, skew distortion, etc. of each image pickup tube, as well as corrections for trapezoidal distortion, pin distortion, etc., which are complicated in terms of circuitry, just by this registration adjustment. Also detected,
It is also easy to automate adjustments.

Next, FIG. 5 is a block diagram showing an example of a detection circuit for horizontal and vertical direction deviation correction information, and FIG. 6 is a block diagram showing an example of the principle of the control circuit of the registration adjustment section in FIG. be. Further, FIG. 7 is a waveform diagram illustrating the operation of FIG. 5.

As shown in FIG. 5, the color television camera of this embodiment has six image pickup tubes 12) 13 of green (G), red (L), and f (B).
H4) (B tube, R tube, G tube).

The output G' of the G tube (4), which serves as the reference for registration adjustment, is higher than the outputs of the other R tubes (3) and B tubes (2).
The deflection system is adjusted in advance so that the phase is advanced by 10 T (H: horizontal scanning period, 150 ns during T). The number in Figure 7 is the cross in one of the screen division areas shown in Figure 1. A part of the image portion of the pattern is shown. The output before G (2) in the horizontal scanning period numbered in FIG. 7 has a waveform shown in FIG. 7B. The output G' of the G tube (4) is connected to the 1H delay line (5
) and T delay line (7) as shown in Figure 7F.
The main line signal was delayed and returned to the outside as a signal sound. This main line signal is used when the registration is correct.
It is in phase with the outputs kLo and Bo of the other image pickup tubes 12+ +3) in the horizontal and vertical directions.

The output of the T-delay H (7) is further delayed by the T-delay line (81), and the delayed output D L G' (Fig. 7C) is subtracted from the input of the T-delay line by the subtractor (9). , 7th
An edge signal EDG representing the horizontal edges of the image (10) as shown in the figure is obtained. This edge signal is a signal that has positive polarity when the video signal rises and negative polarity when it falls. This edge signal El)G is sent to the multiplier (12) through the H contact of the changeover switch υ, and is also supplied to the edge detector α1, where it is used for sampling corresponding to the position of the edge signal. Gate signal SG (
FIG. 7E) is formed.

On the other hand, one (
7G) is applied to the subtracter α, where the difference between the G tube output and the main signal Go is determined. The output RnG of the subtractor a4 is a positional deviation signal R, EG (FIG. 7H) representing the horizontal deviation Δ1 of the output image of the R tube or B tube with respect to the reference image due to the reference G tube output. This positional deviation signal is given to the other input of the multiplier (121),
Multiplication with the edge signal ffDG is performed. The multiplication result is
An error signal El representing the amount and direction of the horizontal shift as shown in FIG.
(DC sample-and-hold voltage S l sampled in interval j and representative of its level and polarity
-1 (Fig. 7J) is obtained. Note that a capacitor (17J is a hold capacitor) coupled to the output end of the sample and hold circuit 16).

The sampling gate signal SG is sent to the sample hold circuit (IQ) via the AND gate 08). This AND gate α8 is opened by the gate signal GEc of 4L supplied from the terminal α) via the buffer (20).

This gate signal is formed to correspond to the valley division region in FIG. 1, which will be described later.

Output of B tube (3) or B tube (2) +to, Bo@- As shown in Fig. 7G, if there is a delay (Δ straddle right deviation) with respect to the main signal Oo of the G tube power, the output of B tube (3) or B tube (2) The sample and hold voltage SH in FIG. 7 J- has positive polarity and shows a level corresponding to Δ1. If the output of the R or B pipe is ahead of the main signal (by Δ2 to the left) as shown in Figure 7, the positional deviations It and Nu will be as shown in Figure 7. The polarity is opposite to that shown in FIG. 7H, and the error signal representing the amount and direction of the deviation has a negative polarity as shown in FIG. 7M. Therefore, the sample and hold voltage SH has a negative polarity of Δ2 as shown in FIG.
Indicates the corresponding level.

The output of the sample and hold circuit (■6) is sent to the control circuit 01) as 5 position deviation information, and the beam deflection device (of the corresponding B tube (3) or B tube (2)) is sent to the control circuit 01) according to the deviation information number.
22) CI! 3) Furnace controlled. As a result, the B tube or the output of the B tube comes to almost match the main signal Go of the output of the G tube, as shown in FIG. 70. Note that normally the output level of the G tube is not equal to the output level of the other LT or B tubes, so even if the image positions of the respective outputs match, the level of the positional deviation signal will change as shown in Figure 7. does not become zero. However, the error signal it of the output of the counter (I)
1% is shown in FIG. 7 (Q) As shown, since the rising and falling edges of the video signal have opposite polarities, the sample and hold voltage becomes zero.

The control circuit basically consists of a comparator (261, up/down (U/1)), a Calantare force, and a D/A converter (28), as shown in FIG. The output S H of the sample hold circuit u6) is sent to a comparator (support) and compared with the ground potential (OV), and the polarity of the positional deviation information (in the horizontal direction, to the right or left with respect to the output image of the G tube) is detected. High level maf corresponding to polarity
The detection output C0Ili4, in which c becomes a low level, is applied to the up-down counter (27) as an up-down control input /D, and the counter (2υ performs a counting increase or decrease operation depending on the high level or low level of the detection signal COM.

The output of the counter (2 ゛Addition circuit (29)
The output of is given to the drive amplifier, and a deflection current is passed through the deflection coil 0υ of the B tube (3) or B tube (2) connected to its output.

If the sample-and-hold voltage 8H representing the positional deviation information of the output of the sample-and-hold circuit σQ is positive, the output COM of the comparator (second period) becomes a high level, the count value of the counter (27) decreases, and thereby the coil C31
) is reduced, and the B tube or the horizontal scanning position of the B tube is moved to the left so that the deviation with respect to the output image of the G tube (4) becomes smaller. Conversely, sample hold voltage S
If H has a negative polarity, the count value of the counter (5) increases, and the horizontal scanning position is shifted to the right, and the B tube or The output image of the B tube is shifted to the right.

In this way, by repeating the detection of deviation information and the change of the deflection DC bias amount according to the detection result, the positional deviation of the output image of each image pickup tube gradually becomes smaller, and automatic horizontal registration is performed. Adjustments will be made. The up/down counter (27) is stopped at the end of the adjustment by determining the convergence state of the decrease in % positional deviation.

The vertical registration adjustment is also performed in the same manner as described above. The image edge signal in the vertical direction is obtained by subtracting the difference between the output G' of the %G tube (4) and the signal obtained by delaying this output G' by 2H by the 1H delay line (51+6) in FIG. ) is formed by subtracting. The subtracter (edge 1g of the output of 2IO is the standard G tube (
In order to match the phase of the output of 4) with the main line signal Go, it is sent to the multiplier from the ■ (duty) contact side of the changeover switch Uυ through the T delay line (25J). The information detection operation is the same as the 11 deviation information detection operation.

The registration W [phase] adjustment based on the detection of the above-mentioned H shift and V shift correction data is performed in the screen division area (
7X7) for both the R tube (3) and the B tube (2). As described above, the deviation correction data obtained in each divided area is temporarily stored in a memory area number as shown in FIG. 2, and data interpolation is performed in the v column direction of this memory area.

41.1 into the extended memory area as shown in Figure 4.

Fig. 8 is a block diagram showing a specific example of the control circuit shown in Fig. 5 for performing this series of data processing. The circuit shown in Fig. 8 mainly consists of the CPU and memory (EtOM, RAM) of a microcomputer. The functions corresponding to the up/down counter (27) etc. in FIG. 6 are achieved by a microcomputer program.

In FIG. 8, a counter corresponding to the up/down counter (5) in FIG. 6 is incremented by the arithmetic unit and register of CP[J (central processing unit) (b).

The output data of this counter passes through the data bus 65), the latch circuit μs (, the full adder C3 output, the latch circuit (38), and then the buffers (39a) to (39d) and D
/A converter (40a) to (40d) selected one
It is given as a registration adjustment signal to the beam deflector (2 seconds or (c) (Fig. 5) of the corresponding l (W +3) or B tube (2) through the comparator (26) of Fig. 6. The detection signal COM indicating the direction of the image position shift obtained is given to the CPU (aa) via the input/output circuit (10 hoard) (4D), and the CPU (34) The clock pulses of this counter may be the vertical synchronization signal VD used in television cameras, and the clock pulses VDU of FIG. G34).

Then, as described above, the beam deflection current is changed by increasing or decreasing the count value of the counter, and furthermore, the direction of image position shift after the change is detected by the detection system shown in FIG. By repeating this, the amount of positional deviation of the image is gradually reduced, and in a predetermined convergence state, correction data corresponding to the matching point of registration is obtained from the counter. This correction data is stored at the corresponding address of the random access memory station.

The memo v-M5 has an area (7×8) shown in FIG. 2, and correction data for registration training obtained for each of the screen division areas shown in FIG. 1 is written to the corresponding address. Memo! The control address corresponding to FIG. 2 of j-M3 is supplied from the cpuH through the address bus (45). Gate pulses GE specifying each of the divided regions in FIG. 1 are generated by a gate pulse generator (42) and sent from the terminal (II to the AND gate α in FIG. 5).

When data detection for one channel (V deviation or H deviation of R tube or DB tube) is completed, the contents of the memory are sent to the CPU one after another through the data bus (35), and are sent in the V column direction. An interpolation calculation is performed to interpolate between the data. The programs necessary for interpolation calculations and the programs that control the entire system are stored in read-only memory (
ROM) written in M4. Also, part 1' of the memory station is used as a calculation register. The interpolation results are written to a random access memory line having the memory area of FIG. 4 through a data bus (3 groups) and a buffer (49).

Next, the correction data for one channel corresponding to the entire screen stored in the memory is read out in synchronization with the beam scanning of the image pickup tube, and the full adder (I) and the latch circuit (38) are read out in synchronization with the beam scanning of the image pickup tube.
ID, ii Mycobara-7-(39a) ~(3+
9d), the deflection device number of the corresponding image pickup tube is provided via a selected one of the D/A converters (40a) to (40d).

Koichi-ichi゛□“-′ -噌→Saki-me For this operation, the buffer (four moats are open,
- Control of loading and reading of M2 is performed based on the output of the control circuit (481).

The secondary correction take required for the second registration adjustment is sent from the up/down counter provided in the cPup phrase to the full adder C (η) via the data bus 6511 latch (brand 9), as in the first registration adjustment. and here memo IJ-
After being added to the previous correction data from M2, the data is subjected to D/A conversion as described above and is applied to the deflection device of the corresponding image pickup tube. The secondary correction take detected by increasing or decreasing the count of the up/down counter is stored at the corresponding address in the memory. 1 for this secondary correction take
#Out of adjustment for the third out of adjustment.

When the second registration adjustment for each of the screen division areas shown in FIG. 1 is completed, the contents of the memory M3 and the contents of the memory M2 are added together in the CPUC 34) and stored in the memory storage again.

Next, interpolation in the direction of seven columns of the correction take in the memo IJ-M3 is performed in the CPUC 34), and the interpolated take is written into the memory history.

The above registration adjustment was performed twice as described above for the misalignment of B tube (3) and B tube (2).
Also, regarding H deviation, it is performed four times. Based on the results of the previous registration adjustment, very accurate correction data can be obtained by repeating the readjustment. In particular, in the screen division area shown in Figure 1, correction data is statically detected by treating each area as the center of the screen and applying a DC (7) deflection bias to each area. If the correction value is read out and applied to the deflection device of each image pickup tube in synchronization with beam scanning, the beam will not be controlled according to the correction value due to the influence of the frequency characteristics (dynamic characteristics) of the deflection device. Therefore, an alignment error that cannot be corrected by just one registration adjustment will occur. However, by readjusting the registration as described above, this can be brought close to zero within the range where the adjustment error can be detected. I can do it.

In addition, when the correction take obtained in the first registration adjustment is read out in synchronization with beam scanning and applied as a correction signal to the deflection device, this correction signal has a frequency at least four times the horizontal scanning frequency. The high frequency wave 1g and the high frequency wave 1b cause distortion due to the frequency characteristic due to the inductance of the system between the ends of the image pickup tube. However, when detecting the correction take during registration adjustment, a DC signal determined according to the increase or decrease of the up/down counter in the CPU is applied to each deflection device as a correction signal for each screen division area. Therefore, this correction gear signal is not affected by the frequency percentage of the end-to-end system at all. Therefore, an extremely accurate correction take can be obtained.

In addition, in the second and subsequent registration adjustments, the primary correction take of the output of memory M2 and the secondary correction take of the DC generated by CP Ll t34J are added by the total DI calculator No. 071 in Fig. 8. , Power II calculation may overflow. Therefore, the full adder 67
)'s carry output is detected by an overflow detection circuit, and when an overflow occurs, a predetermined bias data is sent to the take bus via the detection circuit t5 (latch path 5m from It), and the overflow state is reset. I try to do that.

The correction data detected and interpolated as described above and stored in the memory is passed through the full adder 3η, the latch function and the selected one of the buffers (39a) to (39d) to the corresponding memo') - The data is transferred to one of M1 to M1. These memories M1 to M1 have the same area as the memory history (Fig. 4), and Ml is the V channel of the B tube (3),
M1' is the H channel of the B tube, fVii ~ 5B tube (2)
The V channel and Ml of the B tube are respectively assigned to the H channel of the B tube. In addition, buffers (39a) to (39d)
is selected according to seven channels (B/V, R/H, B/V, B/H)) for each channel by a control signal applied from a B/8 (buffer select) decoder 62 through a gate. Furthermore, the memories M1 to M1'' are selected corresponding to each channel by a control signal l applied through a C/8 (chip select) decoder (54 gates).These decoders t,';a (54) operates based on a control signal supplied from the CPUH through the input/output circuit f4U.

The contents of the memo IJ-Ml to M1 are the address 18 given from between the address generators through the address bus 6η.
It is read out in synchronization with the beam deflection operation according to the number, and is applied to the deflection device of each imaging '#+2) +3) through the corresponding D/A converters (40a) to (40d).

As a result, registration adjustments are made between the ■ direction and the H direction of each of the R tube (3) and B tube (2) using the G tube (4) as a reference, and the image output without color shift is output from the TV camera. can get. In addition, each memo! The control of writing and reading of J-M1 to M1 is performed according to the control signal (M) supplied from the write/read (R/W) control signal generator through the control signal generator. (60) forms a write/continue output control signal O11 based on the output of the control circuit (1) and the clock generator 6(2).

Next, FIG. 9 is a flowchart summarizing the operation of the above-mentioned register John 17dllE. First, the adjustment operation is started by operating the adjustment start button on the camera, and the process (1
00), brisset data is written to memory M2,
In the process (101), the preset data of Nη is stored in the memory M.
1 to M1, respectively. This preset data may be, for example, 80H (hexadecimal notation), and in this case, the output of the D/A conversion'a (40a) to (40d) is zero, and the amount of correction for the beam deflection' surge of each image pickup tube is has become zero.

Next, in judgment (102), the presence or absence of a start signal is detected. This start signal is, for example, R based on the G tube.
The signal may be generated by the completion of the operation of an automatic centering circuit that aligns the center positions of the screen of the tube and the G tube. This automatic centering circuit may have the same circuit configuration as shown in FIG. 5 and FIG. It is provided for the purpose of minimizing the amount. In addition, when center gold setting is performed manually, the configuration is such that a start button is operated to generate a start signal when the manual adjustment operation is completed.

Next, in processing (103), 4 channels (R'1.BW(7)
One channel of the adjustment (JV deviation, H deviation) is specified, and further processing (104) memo! Preset data is written to j-M2. Write this sled set data in a memo! This is done in order to reset the contents of J-M2 before starting the registration adjustment of each channel, and the preset data is data 80H (hexadecimal) corresponding to the non-abrasive adjustment amount. This preset erases the data recorded in the memory length during the previous registration adjustment process. Next, in the process (105), the number of registration adjustments (primary adjustment, secondary adjustment,
) is preset (REGI loop counter).

Next, in the process (103), the specified channel is H.
or V is determined in judgment (106), and if it is 1 (1), the data I10 subroutine (107) for importing the deviation correction data to the memory output shown in FIG. A subroutine (108) performs interpolation processing in the 7-column direction on the data taken in. When the interpolation processing is completed, it is determined whether the count value of the REGI loop counter is 4 or not in a judgment (109). However, if the number has not reached 4, the process returns to the subroutine (107) for importing correction data. This loop is repeated four times, and registration adjustments from the first to the fourth are performed. When the four adjustments are completed, In the process (110), the memories M1 to M1 (R, /V, 几/H, B/V,
B/H).

When the above judgment (106) branches to the registration adjustment in the V direction, the same data acquisition and interpolation subroutines (107) and (108) as in the H direction are performed, and in the judgment (111), 113 GI A determination is made as to whether the loop has been performed twice. (2) With regard to directional deviation correction, since the pixel unit in the vertical direction of the screen is originally a horizontal scanning line, a nearly satisfactory adjustment result can be obtained with two registration adjustments.

Processing (110) When the contents of the memory run are transferred to the corresponding memories Ml to M1 in c, judgment (11
In step 2), it is determined whether adjustment of all four channels has been completed, and if %NO, the process returns to step 104 and adjustment of the remaining channels is started.

When the adjustment of all channels is completed, all the registration adjustment operations by the circuit of FIG. 8 are completed.

Next, FIG. 10 is a flowchart showing the details of the data I10 subroutine (107) for taking in correction data in FIG. FIG. 11t'' is a diagram showing a state of data convergence when detecting deviation correction data.

When entering the data I10 subroutine, first the control address of the memory I)-M6 corresponding to one of each split chain acid in FIG. 1 is set (process 120). The set memory address SA is the 8th in the process (121).
The input/output circuit shown in the figure (PIO) + 41) is output,
This input/output circuit (411 to Kate pulse generator (4z
sent to. In the gate pulse generator (42), a gate pulse GE representing the position of the screen division area is formed in accordance with this opening 1 address SA and an address synchronized with the scanning of the beam output from the address generator Iri. Based on this gate pulse, the detection system shown in Fig. 5 is used to detect the valley division area.
Misalignment, ■ Misalignment correction data is detected.

Next, in the judgment (122) in Fig. 10, the count value of the REGI loop counter is determined to be too low, and if it is the first registration adjustment, there will be no change in the count value of the measurement up/down counter in the CPU (b). Set the range to 8DH (16
Data 80H is loaded into the register r6 in the CPU (b) in order to erase the data (processing 126). Then, preset the initial value of the up/down counter to 808 (
Process 124). In this state, as shown in FIG. 11, the output value of the up/down counter is 80Hi, and the beep content of the image pickup tube to be adjusted is determined by the process (125) shown in FIG.
Data bus from P IJ C31! Lunch (36) is transferred through li). The output of the latch is D/
It is A-converted and added to the beam deflection system as a supplementary current.

In the next process, the data in the register r6 that stores the change in the counter is halved to 1/2 (process 126). As a result, the step width for increasing and decreasing the counter is 8On/2J.
This is set. Then, in judgment (127), the presence or absence of the vertical synchronization signal VD sent to the CPU is detected, and if detected, the output C of the comparator (2) in FIG.
The up/down information indicated by OM (instruction data in the direction of deviation correction) U/D is sent from the input/output circuit +411 in Fig. 8 to the CPU.
(b) is taken in (process 128). This up/down information is determined in a judgment (129), and if it is up, in a process (130) the up/down counter is set to "6 (=8DH/
The count increases by 2).

Also, if the up-down information is down, the process (131
), the count value of the counter decreases by r6. It is determined in step 132 whether or not the step width r6 of the counter has reached 1 bit. If the determination (132) is NO, the process returns to step (125) and the contents of the counter are transferred to the latch. This rice feeding, for example, as shown in FIG.
(+r3/2) is given. Thereafter, as described above, the step width r3 is halved to 1/2 for each correction.
The count value of the counter is increased or decreased by r6 in accordance with the U/D data. This up/down counter increase/decrease loop is repeated until r3 becomes 1 bit, and the correction data of the counter output is 10r3/2 and 10r3/4%- for each VD as shown in FIG. r6/8. -r5/16・
...and converges to the target value S.

When r6=1 is reached, VD detection (size @127') is performed in the same way as described above, with the step width of the counter set to 1 bit.
, including U/D data (processing 129'), up/down determination (judgment 129'), increasing or decreasing the counter by r6 (processing 160', 131'), and transferring the counter contents to the latch (processing 125'). Data processing is performed. Then, when this 1-bit increase/decrease is repeated four times as shown in Figure 11, this is detected in judgment (133),
It is assumed that the correction data has almost converged to the target value.

Next, in step m (143), it is determined whether the registration loop counter at the time of detecting the H deviation correction data has reached the number of visits, and if it is the first time (first) or 4 (g1th (last)), At (134), the data of the contents of the counter is stored in the corresponding control address of the memory station.

This completes the first registration adjustment for one of the divided areas shown in FIG.
In step 5), the control address in the memory is increased by one, and registration adjustment for the next divided area begins. And't
The processing loop from ■ to ■ in FIG. 10 is repeated until the completion of adjustment for all addresses is detected in 'll disconnection (136).

The first registration 'A alignment IK for all (49) of the 49 divided areas in Figure 1 is completed.
Once the correction data required for the adjustment has been written to all addresses in the memo IJ-M3, the average value data before and after it is written to the address corresponding to the horizontal blanking section (1-BLK) in Figure 1. (processing 167). This completes the first data I10 subroutine (107) and returns to the main program shown in FIG. In the main program, the data interpolation subroutine (108
) is performed, this interpolated data is put into memory 1, and this memo! The beam polarization system is controlled based on the read data of j-M2, and registration adjustment is performed.

When the 11th registration adjustment is completed, the RE
The G and I loop counters are incremented by one, and as shown in the main program of FIG. 9, the process returns to the data 10 subroutine (107) and begins the second registration adjustment. In the second registration adjustment, the 10th
The judgment (122) in the figure branches to the process (158), and the first correction data is read out to the CPU (b) from the corresponding control address in the memory, and the first -1 (I disconnection (159)
), it is determined whether the correction data S1 is positive or negative (the magnitude relative to the non-adjustment data) when the non-adjusted data (80H) is set to zero, and if it is positive, the correction data S1 is subtracted from Pk''H in a process (140). Ru.

However, the result of the subtraction shows that the counter is being varied until it overflows when the pH reaches 11 pH (all 1). The subtraction result FFH-8, is written to the register r6 as the OJi width r3/ of the up/down counter. If it is negative, the correction data is written to r6 in process (141) as the counter is being changed. In the case of negative data, the data itself is representative of possible changes until the counter decrements and underflows (OOF).

Thereafter, the same data processing as the first time is performed, and as shown in FIG. 11, starting from data 80H, r6/2 (1/2 of possible changes), r3/4, etc. r3/8・・・・・・
The up/down counter is incremented/decreased with a step width of . Since most of the registration 1 difference is corrected in the first 6M4 adjustment, the target count value S of the counter is small, so the step width of the counter may also be small.

When the step width of the counter reaches 1 bit and the increase/decrease of 1 bit is repeated 4 times and convergence of the data is confirmed in the judgment (135) of FIG. 10, it is the second or subsequent registration adjustment. After branching to judgment (143), judgment (144) detects whether or not the data S exceeds a certain value (for example, ±5 bits in the count value of a counter. If it exceeds, process (145) Let the data S be α
Multiply (for example, 1.5 times) and use this as data. In other words, the secondary correction data corresponding to the slight adjustment that could not be corrected in the previous (first) registration adjustment is
If it exceeds the predetermined reference value, it can be predicted that the influence of the integral action when applying the primary correction data to the deflection coil of the image pickup tube is large, so the secondary correction data should be set to 1.5.
Add weight by multiplying.

In other words, perform the 6th registration adjustment based on the %22nd order correction data and integrate the deflection system divided by 9 (signal distortion).
Correct the data taking this into account in advance.

This further accelerates the convergence speed of the correction data through the registration John adjustment multiple times.

Highly accurate correction data can be obtained in a short time or with fewer registration adjustments. Note that the weighting coefficient α can be appropriately determined depending on the integration time constant of the deflection system. Similarly, for the 6th correction data of the 6th registration adjustment, if it exceeds the standard value, α times 1 - positive is applied, but in the 4th (final)
Naturally, this forecast correction is not performed for the data.

Second registration fA due to increase/decrease in the counter count! When step II is performed and the data is predictively corrected and the secondary correction data is written in the entire area of memory l)-M5, the process returns to the main program in Figure 9 and interpolation calculations in the V column direction are performed again. It will be done.

FIG. 12 shows a flowchart of the interpolation subroutine (107) in FIG. 9, and FIG. 16 is a diagram of a data string in the ■ direction for explaining the interpolation calculation method.

In Figure 12, judgment (11:10) and (181)
So, when the registration adjustment related to the misalignment (■) is performed, the telezi loop counter is 11! l! If it is the lth or fourth time (if it has been completed), it branches to process (150) and returns to A7' in Figure 2.
%! , 7 dots representing one of each region of I-fVI3
, <N (0 to 55) are set. Next, a note on Figure 4! / M20J 7 )" v x r3. r4 is set in correspondence with N (process 151). Memory M3 is a one-dimensional memory with an address area of 0 to 55, but memory 1v2 is as shown in FIG. It is expanded into a two-dimensional memory in the V column direction and 1]1 column direction.Next, in process (152), the data at the address corresponding to the memory pigeon in the memory history is read out and added to the pigeon. In the registration adjustment, M2 contains data 80H.In addition, in the second registration adjustment, the pigeon contains interpolated data of the primary correction data required in the previous 1@ adjustment.At this time, The crime contains secondary correction data that is a correction to the first primary correction data.

Therefore, the absolute amount of correction data is written in the memo v-M5 by the process (152).

Next, in process (153), the data at address N of the memory M3 is read out to the register r1 of the CPU, and further the data at address N18 is read out to the register r2 of the CPU. This N
The data at address and address N+8 are adjacent data in the V column direction of the screen division area, as shown in FIG. then rl
The interpolation data 11. and r2 are divided into 56 equal parts as shown in FIG. I2... is calculated by linear approximation (process 155). The calculation results are temporarily stored in the temporary storage area 'of the address (0-35) provided in the memory M3. In the interpolation calculation formula, the value of % is changed from 0 to 35, and the calculation result is written to the corresponding address of output. Note that the numeral 18 in this calculation formula is added for rounding. As a result,
As shown in FIG. 16, for example, a set of data D16. Data corresponding to 65 scan lines between D24 are obtained by calculation.

Next, in judgment (156), the address data N(
0 to 55), the upper end (0 to 7), middle (8 to 47), and lower end (48 to 55) of the screen division area are classified. In the case of the upper end and the lower end, extended interpolation branched into A and B, which will be described later, is performed. In the intermediate case, Banko branches to C,
In the process (157), the interpolated memory M3'o)
The contents of address N (0 to 35) or r6. Transferred to address r4. Then, address N in the memory is increased by 1 (process 158) and tV? corresponding to the increased N? , 4' address area, r4, is incremented by 1 (process 159). and 1 judgment to perform the next interpolation its (
The process returns to process (152) via branch 160). When the memory height address N reaches 55 and interpolation for almost the entire screen is completed, this is determined in step 160 and the process returns to the main flow shown in FIG.

2nd and 6th registration adjustment regarding H deviation
In the second case, the process branches from judgment l#I (181) in FIG. 12 to processing (182), and the data in each area of the memory station shown in FIG. 2 is compared with the data in the previous adjacent area. will be held. For example, for area 20, area 19
This is done for all areas. If the % difference as a result of comparison is greater than a certain value (for example, ±5 bits), this is detected in judgment (183) and processing (184) is performed.
Then, the current address is stored. When the above comparison is completed for all addresses of M3 (determination 185), the process (
186), the data at the corresponding address is multiplied by β and stored in the station again.

β may be, for example, 1.5 times the degree of correlation, and by this processing, the data of each divided region is analyzed, and weight is given to those whose difference from the previous neighboring region is greater than a certain value. That is, the second (
8) Correction data that changes greatly on the split chain plate (changes relatively rapidly in time, therefore, the frequency is relatively still, and when given as a correction signal to the 1#ii direction system) (those subject to many integral actions) are modified in advance,
The amount of correction in the next registration 11j adjustment is made to be smaller. This corresponds to adding in advance, by differentiation or difference, an amount corresponding to the rounding of the correction signal due to the integral action in the deviation system.

Through this data processing, data with a higher degree of precision can be quickly obtained, similar to the weighting process based on the comparison with the data of the previous registration adjustment described above.

Further, as described above, this processing is not performed except for the first and final registration adjustments, but weighting processing may be performed on the correction data obtained at the first time. Note that the desired effect can be obtained by performing weighting based on either the comparison with the previous correction data or the comparison with the previous adjacent correction data, but it is more preferable to perform both.

FIG. 14 is a flowchart showing the extension interpolation of the upper end of the screen performed at branch A of +till (156) in FIG. 12, and FIG. 15 is a diagram showing the extension interpolation method.

In Fig. 14, first, note in the process (161)! J-
Calculation memo inside M3! Address of j-M3' (
0 to 17) are set, and further processing (162
), the address of the JII location (66 to 56) of the memory output is set. Akira's % land (0-17) is the 12th
In the process (155) shown in the figure, interpolated data calculated from the upper end data (K=0) toward the inside of the screen has already been written. Further, the 5th location of M6' is a storage location for extended interpolated data.

Next, in the process (163), the 0 position (K=0) of memory pigeon'
is loaded into register r1 of the CPU. The data at this 0 point corresponds to the data at the upper end of FIG. 2, 0.1, 2, . . . . Furthermore, in the process (164), the address of the pigeon is changed to C.
Load into register r2 of PU. When extended interpolation is performed by linear approximation, as shown in FIG. 15, interpolated data r2 and data r2' obtained by extended interpolation are at points symmetrical positions with respect to data r1 at the upper end. Therefore, r2-r1=ri-r2'.

r2'=riX2-r2 Extended interpolation data can be obtained using the calculation formula.

In the process (165), the calculation result of the above formula is stored in the register r again.
I am writing in 2. The calculation result is checked for overflow in judgment (166), and if there is no overflow, it is memoed in process (168). / - Transferred to the 5th location of M3'. Note that if the data in r2 is one location in Mro', then address J in M6' corresponds to 52 locations.

If the calculated value overflows, the contents of register r2 are changed to FFH (all 1) or 00H in processing (167).
(all 0).

When one extension interpolation calculation is completed, the J address is decreased by 1 (process 169), and the address is increased by 1 (process 169).
Process 170). and n1 18 times until J reaches 66
The calculation is repeated, and when it is detected in judgment (171) that all of J has been completed, tAf, the memo obtained by Long Sleeve! The data of the 5 locations (66 to 56) of j-M6' are transferred to the corresponding memory address ■ (process 172).

When the above-mentioned extension interpolation process is completed for one of the data at the upper end, it is returned to the 0 point in FIG. 12.

Next, FIG. 16 is a flowchart of the extension interpolation of the lower end of the screen division area, which is performed in branch B of judgment (156) in FIG. 12. This flowchart is almost the same as that shown in FIG. 14, and is obtained by interpolating the data at the bottom of the screen upwards on the screen in the process (155) of FIG. The difference from FIG. 14 is that extended interpolation data below the lower end data is calculated based on the data in 56).

As described above, the memory area in Figure 4 (256 x 8)
Interpolated data is calculated for all of the 9th
Note as explained in the diagram! j-M2 to the corresponding memories Mi to M1''. Note that N'I'S
In the C method, the number of running lines in one field screen is 262, 5.
If the screen is divided into 7 equal parts and 66 lines are allocated to each section as shown in Figure 1, 6 x 66 interpolated data will be created in the middle of the screen, and at the top and bottom of the screen. 18 extended interpolation data are created in each section. Therefore, the address in the V direction of -M2 and M1 to M1'' is 1 necessary for the data in the vertical blanking section V-BLK.
In addition, 36x7+1=255 addresses are required. That is, data for one channel can be stored in 2 bytes of memory. Regarding the correspondence between directional addresses and scanning lines in this memory, 66x7 addresses are allocated to 66x7 scanning lines, and the remaining 1 address is allocated to 11 scanning lines as a vertical blanking interval. . In other words, 36x7+11=26
A memory address is assigned to each of the five lines.

One address in the ■ direction of the memory for 11 lines of the blanking section contains the topmost data obtained by extension interpolation at the top of the screen and the bottommost data obtained by extension interpolation at the bottom of the screen. The average value of the data is written.

This average value data is multiplied between the above 11 lines.

Read out. The reason why the blanking interval (11 lines) in the addresses of memories M1 to M1 and scanning is made shorter than the blanking interval of the actual video signal is because the camera tube scans a wide range up to the blanking interval of the video. This is because, by performing registration adjustment even during the blanking period, it is possible to improve the accuracy of correction to the periphery of the screen. Note that the area surrounded by the solid line U in the memory area in Figure 4 is N.
An effective screen for the TSC method is shown.

When applying the embodiment of the present invention to a PAL television system, the correction data necessary for registration adjustment is extracted in the same manner as described above, but note! j-M
By changing the correspondence between the 1-direction addresses of M1"' and M2 and the scanning lines that form the screen, we aim to standardize the hardware and software between the NTSC system and the PAL system. In other words, PAL In the system, the number of scanning lines in one field is 312.5, so the li!ii plane is divided into seven equal parts, and 42 lines are allocated to one section.
If the vertical blanking period is 15 lines, the required ■
The direction address is 42x7+1+4=299, and the number of scanning lines is 42x7+15=509. Therefore, the shortfall for the scanning line 312.5 of one field is 4 lines, and for these 4 lines, interpolation data is created by extending downwardly and interpolating the section at the edge of the screen during interpolation calculation. I can do it.

However, as in the case of the NTSC system, if one address is assigned to one line, 2 x 9 addresses are required as described above, and data for one channel cannot be stored in 2 bytes. Increasing the memory capacity is not desirable in terms of cost and power consumption.

For this reason, in this embodiment, 66 addresses are assigned to 42 lines when using the PA, L method, and the address increment is stopped once every 6 steps, so that the number of correction data read from the memory is The number of 2 inches is almost the same. Through this process, the PAL
The effective screen area of the system is approximately the same in memory space as the effective screen area (solid line V) of the NTSC system.

FIG. 17 is a circuit diagram of an address generator (g) that generates an address for reading out the correction data stored in the memories M1 to M1'' in synchronization with the beam scanning of the image pickup tube.

FIGS. 18 and 19 are time charts for explaining the operation.

A in FIG. 18 shows the horizontal blanking section H-BLK. MagB indicates a horizontal synchronizing signal HD used in this television camera. This horizontal synchronizing signal is applied to the H phase adjustment circuit section of FIG. 17, and after phase adjustment as shown in FIG. 18C, is supplied to the PLL circuit (g). Furthermore, since the gate No. 1M Gn is generated in the gate pulse generation circuit (42) based on the address generated by this address generator (G), horizontal synchronization is performed so that this gate signal is symmetrical within the effective screen. An H phase adjustment circuit (621) is provided for the purpose of adjusting the phase of the signal HD.

A clock pulse 16FH multiplied by 16 as shown in FIG. 18F is obtained from the PLL circuit power.

The clock pulse is supplied to the 4-pit H counter (6 clock inputs CK), and the clock pulse of this counter is
The output FH (horizontal frequency, Fig. 18E) is connected to the inverter (b
5+, it is fed back to the PLL circuit (63) as a phase comparison signal as shown in Figure 18. From the most significant bit of the counter (6·υ), the clock pulse 81i' shown in Figure 18G is
H is obtained. This clock pulse [H-j is used as a clock for creating an atome when reading out correction data from the memory. The upper 6 bits of the ti counter become the H-axis read addresses VMAQ to VMA2 of the V deviation correction data memory. This address is incremented from 0 to 7 within a horizontal period as shown in FIG. 18H.

Next, FIG. 19B shows the vertical synchronizing signal VD used in this television camera, and A shows the vertical blanking interval V.
- Indicates HLK. In addition, FIG. 19C shows the horizontal synchronizing signal 1-(D.
is provided for the same purpose as the H-phase branch circuit. This V
The V timing signal VD1 shown in Figure 19 is obtained from the phase adjustment circuit hook, and this timing 100 is preset to the blanking (V-BLK) counter (671) for setting the V blanking section of the read address. Also, the V timing signal VD2 (Fig. 19E) generated by the V phase adjustment circuit (66) is given as a set signal to the flip-flop track for creating a blanking signal. Pu (68
1 is provided to control a v counter (69aX69b) which will be described later.

V-BLK counter (6η is V as shown in Figure 19F)
The count value is preset to 4 by the timing signal VDi. This preset value is determined by the preset data PS given to this counter and the level signal obtained from the NTSC/PAL changeover switch (70).

The count value of the V-BLK counter (6η is the count value of the H counter (f
The clock pulse given from i41 via the buffer (7]) increases every H (horizontal frequency), and the count value is 1.
5, a carry pulse 15CA shown in FIG. 19G is generated. Note that the lock pulse FH is given to the enable input of the counter (6η), and the clock pulse 16F multiplied by 16 is
H is applied to the clock input via buffer Cl7J.

The carry pulse 15cAi of the counter (67) is given as a clear pulse to the flip-flop (fi131), so the
A blanking pulse BLK having a width of 11H as shown in FIG. H is obtained in synchronization with the clock PH.

This blanking pulse is
), the V counter receives the blanking pulse B as shown in Figure 19 (■).
After LK (H in FIG. 19) returns to high level, the count increases in H periods. The V counters (69aX69b) each have 4 bits and are connected in series. And the clock pulse is 16FH, but the counter (69
Since another enable input TE clock F'l is given, it generates a count output of 0 to 256 that steps in H periods.This count output is Memory chain acid V-axis address VMA in the figure
3 to VMA10 (8 bits).

As described above, the H counter and V counter (69a
X69b) T type H sale fc V 7 Tov S VMA
O to VMA10 are applied to the memories M1 and Ml'' in FIG. 8, respectively, and the V deviation correction data of the %R tube and the B tube are read out.The V address is given to the memories M1 and Ml'' in FIG. ), and is sent out as an H address at the rising timing of clock 3PH (G in Figure 18).
Axis component) It shows the step change of IMA O to HMA2.

As shown in FIGS. 18H and I, the read addresses HMAO to HMA10 of the H deviation correction data are 8 to the read addresses VMAO to VMA1Q of the deviation correction data.
It is created with a phase delayed by half a cycle of the FH clock. −
Read f′, that is, correction data from memory L te D /
A When converting and applying it to the @same system via a low-pass filter, the delay (time constant) of the low-pass filter is different between the vertical polarization system and the horizontal polarization system. Adjustments are being made.

In addition to detecting correction data, FIG. 18J shows the above-mentioned read address VMA or HMA and the screen division area (0
, 1, 2, . . . ), and a portion (6 and O) of the gate signal G13 generated by the gate pulse generator (421) of FIG. 8 is shown. Registration V@ based on the correction data as described above
When performing the adjustment, it is necessary to take into account the delay of the low-pass filter during D/A conversion. Therefore, the read addresses VMA and HMA are created with a lead phase than the sampling gate signal On at the time of data extraction.

Next, a case will be described in which the television camera of this embodiment is operated in a PAL system. Figure 19 J is PAL
It shows the vertical blanking section of the signal. As described above, when applied to the FAI system, the 15H section within the blanking section is assigned to the blanking section when reading the memory. For this reason, connect the selector switch (70J in Fig. 17) to the PAL contact side to form a low-level preset signal and change the preset data of the V-BLK counter.As a result, the V-BLK counter output is 1st at timing 100 VDI (Fig. 19D)
As shown in FIG. 9K, the count value is preset to 0, and then counts up to 15 at the horizontal frequency.

Therefore, the Q output of the flip-flop f6al is calculated from the timing signal VD2 by the carry output 15 of the counter (6η).
The level becomes low in the 15H section up to cA, and this 15I
In the section of (69aX69b), the V counter (69aX69b) is cleared and its counting operation is prohibited. Then, when the flip-flop is reset by the carry output 15CA,
■The counters (69a) (69b) are cleared.

Counting from 1 to 255 is performed as shown in the 19th diagram.

On the other hand, the low level output of the selector switch is connected to the inverter (7
6) to the enable input TB of the 4-bit 6/7 counter (77), thereby causing the counter σ
η becomes operational. This counter C1η clocks clock pulse 16FH, clock pulse FH,
Since the B count is enabled manually (Pg), the counting operation is performed at the horizontal frequency. 9 is given as the preset data PS, and as shown in FIG. 19M, the count is counted from 10 to 15 after the blanking interval of 15H ends, and when the count is 15, the carry output CA is generated by the generator. The carry output of this counter is fed back to the clear input CLR via the inverter σ and the negative logic OR gate σ9, so the
The count value is again preset to 9 in synchronization with the horizontal synchronizing pulse PH after clearing. Therefore, counter σ71 operates as a hexadecimal counter.

The carry output CA of the counter ση is inverted by the inverter σ and then applied to the enable input Phi of the (2) counter (69a), so that when the count value is 15, the counting operation of this (2) counter (69a) is interrupted.

The output of the inverter (Dai) is also applied to the AND gate ■, and therefore, the clock PH, which is being viewed through the gate ■ and enabling the counter (69b), is cut off, and when the count value is 15, the V counter ( 69b) is interrupted.As a result, as shown in Figure 19, the increment of the counting output of the counter (698x69) is 7.
Paused once in H, ■Address VMA5 to VMA109
5.6.6.7... Songs 11, 12゜12.16...
. . . Every 6 increments, 11 identical addresses are duplicated.

Therefore, in application to a PAL system, memories M1 to M
The contents of No. 11 are read out for one line out of seven lines, overlapping with the previous line. As a result, memories Ml to M1
As shown in Figure 4, 42 scan lines are allocated for 62 addresses on the v-axis of the NT8e system.
The effective screen of the L system can be covered.

Next, FIG. 20 is a circuit diagram of the vertical deflection system of the television camera of this embodiment, and FIG. 21 is a circuit diagram of the horizontal deflection system.

Addresses VMAO to VMAI for reading 7jV deviation correction data created by the address generator (g) in FIG. 17
Q B 71 Mo! J-Ml (R/V), Mi
'(B/V), and the addresses HMAO to HMAIO for reading the H deviation correction data are in the memory Mi.
'(R/H), Ml'' (B/H), and the correction data is read out in synchronization with the beam water erosion.Output i of Ml and M1#; (D/A converter (40aX40c) and the terminal (8) in Figure 20 via a low-pass filter (not shown).
1aX81 c). Also Ml, Ml
The output is sent to the terminals (81b x 81
d) given.

As shown in Figure 20, ■The deflection system consists of G tube (4), B tube (
3) and B tube (2) ■ Deflection coil (820082R8
82B), and each is equipped with a class A or class 8 amplifier (
86G) (85FLX83B). %
A resistor (840084R084B) is connected in series to the deflection coil, and their terminal voltage is connected to the amplifier (83GX83
By feeding back to f(X83B), a current equal to the amplifier input voltage divided by the resistance values of these resistors flows through each coil. The amplifier (85G) that drives the reference G tube coil (82G) receives a vertical scanning sawtooth wave signal V -8AVV generated in synchronization with the vertical synchronization signal VD in the sawtooth wave generation circuit □□□. Given. Further, the sawtooth wave signal is applied to the B tube and the amplifier (86x83B) driving the B tube via adder circuits (86a) and (86b).

These adder circuits (86aX86b) have terminals (818
A registration signal is given from X81 C), which causes R? i? and V direction register of B tube)
L/- John adjustment is performed. Valley vertical deflection coil (82
G) (82RX82B) has frequency characteristics, so the high frequency range of the registration adjustment signal for V shift correction, which has a component several times the horizontal frequency, may deteriorate. However, as described above, this deterioration can be compensated for by re-regulating M (registration 0).

In the horizontal deflection system shown in FIG. 21, a horizontally periodic sawtooth wave current is applied to the horizontal deflection coil (890
089R889B). Note that the transistor (
The capacitor (1) connected in parallel with C) is for integration, and the diode (9υ) connected in parallel through the flyback transformer is for damper. Also, each horizontal deflection coil (89
A secondary winding of a correction transformer is inserted in series through a capacitor θ2 to the deflection current supply line to the deflection current (0X89R889B). This correction transformer (the 9-moat primary winding has a horizontal synchronization signal in the sawtooth wave generation circuit)
11) A sawtooth wave with a horizontal period formed in synchronization with) 1-
8 AW is provided through a gain adjuster (95)% amplifier (96), which provides horizontal deflection linearity compensation.

Horizontal deflection coil (89G089B) (89B) It is the part that adjusts its inductance (89G'089R'
889B'), and by adjusting these, it is possible to roughly adjust the size and center position of the output image of each image pickup tube. Further, variable resistors (97G) (97R097B) are inserted in series with each horizontal deflection coil, and by adjusting these, the approximate center position of the output of the container can be adjusted. In addition, the B tube and BIg variable resistor (978097B) are made into a variable impedance circuit,
The center positions of the B tube and B"ff0) images may be aligned with Gw as a reference using the automatic centering circuit described above.

Horizontal registration noise adjustment of the B tube (3) and Bp # (2) is achieved by the auxiliary coil (98a) (98
This is done by applying a correction current to B). These auxiliary coils (98B) (98B) are connected to the R channel and B channel read out from the memories M1/ and M1#', respectively.
Amplifier (99) that receives channel H deviation correction signal as input
R099B). By providing such a correction coil, the main deflection coil (89RX89B
) can be driven by a switching method, and there is no need to use a class A or class 8 amplifier to flow the deflection current, resulting in lower power consumption.

In addition, since the deflection current flowing through the main deflection coil can be roughly adjusted in advance for each image pickup tube's linearity, image size, and center position, the auxiliary coil (988898
The correction amount for registration 1 by B) is more than /J
Therefore, the drive amplifier (99FLX99
The output capacitance of B) may be small.

In addition, in the horizontal scanning section, the main deflection coil (89FLX89B
) are short-terminated by the switching drive circuit, the energy being supplied to the auxiliary coil (98R098B) will leak through the main deflection coil to the low-impedance drive circuit, reducing the magnetic flux of the correction coil. will be affected. In particular, the high frequency component of the magnetic flux of the correction coil is reduced by the integral action. However, as mentioned above, 2nd % 6th %
By repeating the readjustment of the fourth-order registration, it is possible to create a correction signal that compensates for this attenuation.
This problem can be completely resolved. Note that such an auxiliary coil for registration adjustment may be provided in the vertical deflection system as well.

Note that in the above embodiment, the correction data v for each scanning line is
Interpolation in the column direction was performed using linear approximation (first order), but second order, 6
The following interpolation can be employed.

Although interpolation in the H column direction is not performed, the memory area may be expanded to perform interpolation in the H direction. In addition, the misregistration is generally large at the periphery of the screen, so
The screen division shown in FIG. 1 can be made finely unequal at the periphery to improve adjustment accuracy. As for the number of screen divisions, it is desirable to divide the screen into an odd number as in the embodiment (7x7). In odd number division, a divided area is created at the center of 5 screens, so as mentioned above, if you apply a DC bias to the king deviation coil in advance to perform centering adjustment for this center divided area, and then perform registration adjustment, the auxiliary coil can be used to adjust the centering. Less correction is required.

As described above, the present invention detects the registration error with respect to the reference image pickup tube regarding the valley divided area of the screen divided into a plurality of parts, stores it in the memory, and sends a correction signal according to the memory output to the deflection system of the image pickup tube. is applied to control the beam deflection, and this adjustment process is repeated a plurality of times (for example, four times) to obtain a target registration adjustment amount. Also, at least in the middle of multiple adjustment processes (
For example, in the second and sixth times), the deviation between the beam deflection control amount by the correction signal and the necessary adjustment amount to the target (for example, signal distortion due to the integral action of the deflection system) is stored in the memory. The prediction is made based on the corrected data.
m to add distortion to the correction data based on the prediction result.
accomplished. Therefore, it is possible to correct the correction data so that it approaches the target value by considering in advance the distortion of the correction signal due to the integral action of the deflection system, so more accurate data can be obtained quickly with fewer adjustment steps. can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a screen for explaining the automatic registration adjustment method according to an embodiment of the present invention; FIG. 2 is a diagram showing memory areas for storing misalignment correction data in each of the screen division areas of FIG. 1; FIG. 6 is a diagram for explaining the process of interpolating the middle part of vertically adjacent data in the memory area of FIG. 2, and FIG. 4 is a memory that stores registration adjustment data formed by interpolation. A line diagram showing the area, FIG. 5 is a block circuit diagram showing an example of a detection circuit for horizontal and vertical direction deviation correction information, and FIG. 6 is a principle example of the control circuit of the registration adjustment section in the fifth section 7 is a waveform diagram showing the operation of FIG. 5, FIG. 8 is a detection of correction data for H deviation and V deviation,
*A block circuit diagram of a control circuit that executes interpolation and registration adjustment valley control% Figure 9 is a flowchart summarizing the registration adjustment operation of Figure 8.
0 is a flowchart showing the details of the data I10 subroutine in FIG. 9, FIG. 11 is a diagram showing the data convergence state when detecting deviation correction data, and FIG. 12 is a flowchart of the interpolation subroutine in FIG. Figure 13 is a diagram of the direction data string showing the interpolation calculation method, Figure 14 is a flowchart showing extension interpolation at the top of the screen, Figure 15 is a diagram showing the extension interpolation method, and Figure 16 is the bottom of the screen. Flowchart showing extended interpolation in Figure 17 is a memo') -Ml~M
1. FIG. 18 and FIG. 19 are time charts for explaining the operation of FIG. 17, respectively. FIG. 20 is a vertical deflection system of the television camera of the embodiment. FIG. 21 is a circuit diagram of the horizontal adjustment system. In addition, in the symbols used in the drawings, (1)...
......Screen f2X3X4)...
......Image tube t5X61...Curved 1HM wire extension (b)......Subtractor (121
・・River・・・・・−Multiplier α average・・・・・・・
・・・・・・・・・Subtractor (16)・・・・・・・・・
...Sample and hold circuit (2]) ...
......Control circuit (22) (c)...
・・・・・・Deflection device (261・・・・・・・・・・
...Comparator (2η...
...Up-down counter (b)...
......CPU (40a) ~ (401) ......D/A converter 66)
・・・・・・・・・・・・Address generator (64J
・・・・・・・・・・・・・・・H counter <69a>
<69b)---V,/;l run pσQ...
.........Choice switch ση...
・・・・・・・・・ 6/7 counter (820X82
RX82B) ・・・・・・・・・・・・・・・ V deflection coil (89
UX89RX89Ll) ・・・・・・・・・・・・・・・Horizontal deflection coil (98
aX98B)...Auxiliary coil M6......First memory M
2・・・・・・・・・・・・Second memory M1
~M1... Memory. Agent Masaru Saturn〃 Yoshio Tsuneko〃 Toshiki Sugiura Figure 9 Japanese Patent Publication No. 58-131882 (23) Figure 14 1N Publication No. 58-131882 (25)

Claims (1)

[Scope of Claims] 1. A circuit that divides an effective screen portion into a number of parts and detects a registration error of the output signal of another image pickup tube with respect to the output signal of a reference image pickup tube for each divided area, and A memory has a memory area corresponding to the area, and stores the detected registration error, and a correction signal corresponding to the correction data stored in this memory is applied to the deflection system of the other image pickup tube to convert the beam. The control means for controlling the deflection and the adjustment process from the detection of the registration error to the control of the beam deflection are performed multiple times, and the fine adjustment data for the correction data input by the samurai in the previous Ryōtei process is stored in the memory. a system control means that asymptotically approaches the target value of registration adjustment by cumulative loss; and at least in the middle of the plurality of adjustment processes, the beam deflection is controlled by the correction signal until the beam deflection reaches the target value. A multi-function device comprising means for predicting the deviation from the necessary adjustment amount based on the correction data stored in the memory, and data correction means for adding weight to the data in the memory based on the prediction result. Registration adjustment circuit for a color camera. 2. The prediction means detects a difference between two pieces of corrected data obtained at the same position in each divided region temporally by the adjustment process, and the detected difference is predetermined. and means for discriminating whether the data is equal to or greater than a certain value, and based on the result of this discrimination, the data correction means multiplies the corrected data by a constant of 1 or more. Registration adjustment circuit for a multi-tube color camera described in . 6 The prediction means detects a difference between two pieces of data corresponding to regions located before and after the beam scanning direction on the screen divided into each region, and the detected difference is determined in advance. and means for discriminating whether the data is equal to or greater than a certain value, and based on the result of this discrimination, the data correction means multiplies the corrected data by a constant of 1 or more. Registration adjustment circuit for multi-tube color camera.