JPS589497A - Registration control circuit of multitube color camera - Google Patents

Abstract

PURPOSE:To calculate in a short time the data about a registration error having a small number of samples with the comparatively rough division of a screen, by making areas produced by the plural division of an effective screen part as approaching the circumferential part of the screen. CONSTITUTION:An effective screen part is divided into plural regions so as to reduce the area of each divided region as approaching the circumferential part of the screen. An error signal ER of the horizontal and vertical shifts of the output signals R0 and B0 of the R and B tubes 3 and 2 to the output signal G' of a G tube 4, i.e., a reference image pickup tube is stored in the 1st memory of a control circuit 21. Then the interpolation data is formed on the basis of the data of the 1st memory written into the 2nd memory having a memory region extended in the vertical direction of the screen. The beam polarizing devices 22 and 23 are controlled in accordance with the data stored in the 2nd memory. Thus the registration is controlled for the tubes 2 and 3.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a registration adjustment port li! for a multi-tube color camera equipped with a plurality of imaging means such as a three-tube type (B, 几, and G) or a two-tube type (brightness and chroma). In particular, the present invention relates to a registration adjustment circuit that divides an imaging screen into a plurality of parts and performs registration adjustment for each husband.

In a multi-tube color television camera, registration (alignment of each color) of each image pickup tube requires extremely complicated adjustment.Generally, the center position of the output image of each image pickup tube is adjusted Although the beam deflection current is corrected,
Angle of view (rotation of the image about the axis), distortion at the periphery of the screen [
It is difficult to correct color shifts caused by differences between image pickup tubes such as trapezoidal distortion, pin distortion, etc.], image size, scanning nonlinearity, skew distortion, and the like. Conventionally, various correction signals are created to correct these distortions that cause color shift, the gains of these signals are adjusted for each image pickup tube, and the adjusted signals are used to control the six tubes. Registration adjustment was performed by controlling the beam deflection current. Therefore, the control circuit is extremely complicated, and since each cause of color misregistration is an independent phenomenon, there is an inconvenience that even if alignment is made in one part of the screen, it will not match in other parts. It has been difficult to achieve uniform registration across the entire screen.

The present invention solves this problem and provides a registration adjustment circuit for a multi-tube color camera that can particularly improve the adjustment accuracy.

A specific embodiment of the registration adjustment circuit for a multi-tube color camera according to the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of a screen for explaining an automatic registration method according to an embodiment of the present invention. As shown in Figure 1, [this is an example? f The image capture screen (1) by a three-tube type (B, JG) color television camera is on the right side of the vertical view, bottom II
It is divided into seven parts at the division ratio shown in I (1:1:3:4:321:1). This (7x7 = 49 areas (this screen ())
1) is divided into unequal parts. In each of the divided regions, registration adjustment is performed, for example, using the image pickup tube (G tube) that obtains the green signal G as a reference and targeting the other R tube (red signal) and B tube (green signal). When adjusting the registration, as shown in Figure 1, the center position of each divided area (the pattern board with the "+" character written on it or the subject is imaged. The pattern chip may be configured to be inserted into the imaging optical path by an operation such as a built-in chip inside the television camera or an external force for registration adjustment.

In each divided area number, the G tube is the reference (R tube, B tube
Information for correcting the misalignment of the tube in the H direction and V direction (V misalignment, H misalignment) is detected as described later, digitized, and temporarily stored in a memory area as shown in FIG. The memory area is 8 columns in the H direction and 7 columns in the ■ direction (8x7
), and each memory element stores correction information for H deviation and ■ deviation corresponding to each divided area. The extra column in the H direction of the memory area in Fig. 2 that does not correspond to the divided area (7x7) of screen (1) is used to store correction data for H deviation and ■ deviation in the horizontal blanking section H-BLKg. This is provided. The data in this blanking section may be the average value of the last data of the sample data string arranged in the H direction and the first data of the next sample data string. For example, data D18 in the memory area in FIG. 2 and data D14 in the next column (row)
The average value (D18+D 14 )/2 is calculated and this is set as data D15. Insertion of correction data for this horizontal blanking interval (because of this, the correction provided by the horizontal and vertical deflection currents becomes smoother).

Note that a memory column for storing average value data may be provided for the vertical blanking section V-BLK as well, similarly to the horizontal blanking section.

Next, with respect to the sample data stored in the memory area of FIG. 2, the data are interpolated in the V column direction, and the intermediate portion between the data is interpolated to create data for each scanning line by approximate calculation. Regarding #H column direction number, substantial interpolation is performed between data by analog processing (low-pass filter).

If the number of screen divisions for extracting deviation correction data is too small, the degree of registration adjustment will be poor, and if it is too large, it will take too much time to detect deviation data.

In the embodiment, as described above, the screen is divided into 7×7 unequal divisions in which the divided area becomes smaller as the number of peripheral parts increases. Therefore, in the case of the NTSC system, f is 18.18.56 in the order of husband and husband with the above division ratio for the seven divisions in the ■ direction.
．． 72.56.18.18 lines are allocated.

For example, as shown in FIG.
Between 16 and D24, 62 interpolated data 11 to I6
2 is calculated using a straight line approximation method. In this case, it is assumed that the detected deviation correction data corresponds to the center line l of each divided area. Interpolation calculations are performed for both the (1) and H (deviation) correction data in the seven column directions, but the time required for the calculation is much shorter than the time required to detect the deviation. Therefore, highly accurate registration adjustment data can be obtained in a short time with a small number of samples.

V column interpolation 1 Registration adjustment data corresponding to each line of the entire screen is created, and this data is stored in an expanded memory area as shown in FIG. The memory for this adjustment data is in the H direction (8 columns,
It has a size of 256 columns (8×256) in the direction, and two data of V deviation correction and H deviation correction are stored in one memory address area.

The registration adjustment data stored in the expanded memory area of FIG. 4 is read out and converted into an analog correction signal ζ, and the horizontal and vertical deflection currents are controlled based on this correction signal. As a result, correction of the screen size, deflection linearity, skew distortion, etc. of each image pickup tube and trapezoidal distortion, which is complicated in terms of circuitry, can be simultaneously processed. It is also easy to automate detection and adjustment.

51-1 is a block diagram showing an example of a detection circuit for horizontal and vertical direction deviation correction information, and FIG. 6 is a block diagram showing an example of the principle of the control circuit of the registration adjustment section in FIG. It is a diagram. Further, FIG. 7 is a waveform diagram illustrating the operation of FIG. 5.

As shown in FIG. 5, the color television camera of this embodiment has three image pickup tubes (2++
31 (4J (B pipe, B pipe, G ministry)).

The output α of the O tube (4), which is the reference for registration adjustment, is higher than the output of the other B tubes (3) and B tubes (2).
The deflection system is adjusted in advance so that the phase is advanced by T (H horizontal scanning period, T = 150 nS).

FIG. 7A shows a part of the cross pattern image (1o) in one of the screen division areas shown in FIG. 7th
The output of the G tube (4) on the horizontal scanning line Lnl in Figure A has the waveform shown in Figure 7Bj. The way α of the G tube (4) is 1
It passes through the H delay line (5) and the T delay line (7) and is delayed by H0T as shown in FIG.
This is derived. When the registration is correct, this main line signal is sent to the other image pickup tube (2+ (31 output Ro
%B, and is in phase with respect to the horizontal and vertical directions.

The output of the T delay line (7) is delayed by another T delay line (8), and the delayed output DLα (FIG. 7C) and the input of the T delay line are subtracted by a subtracter (9). Accordingly, Fig. 7 D+
An image like this (edge No. 41 EDG representing the horizontal edge of 101) is obtained. This edge signal is
This is a signal that has positive polarity when the video signal rises and negative polarity when it falls. This edge signal EDG is sent to the multiplier (1) through the H contact of the changeover switch 0υ, and is also supplied to the edge detector (I), where a sampling gate signal 8G corresponding to the edge signal position is sent. (7th
Figure E) is formed.

On the other hand, the other B tube (3) or the output Ro of B tube (2) or the selected one (7th
The signal G) is applied to the subtracter 05), where the difference between the G tube output and the main signal Go is determined. The outputs RBG of the six subtractors are the reference image [against B
The positional deviation signal RiD () (Fig. 7H) is representative of the horizontal deviation Δ1 of the output image of the tube or B tube.This positional deviation signal is given to the other input of the multiplier (121) and Multiplication with the signal EDG is performed.The multiplication result is an error signal ER representative of the amount and direction of the horizontal shift as shown in FIG. , a DC sample-and-hold voltage 8 sampled in the section of the sampling gate signal SG mentioned above and representing its level and polarity.
H (FIG. 7 J) is obtained. Note that the sample and hold circuit (capacitor 07 coupled to the output terminal of 161) is a bold capacitor.

The sampling gate signal SG is sent to the sample and hold circuit (tet) via the AND gate Q8. This AND gate is opened by the gate signal GE supplied from the terminal Q9 via the buffer wire. Gate signals are formed corresponding to each divided area in FIG. 1, as will be described later.

Output Ro, Bo of B tube (3) or B tube (2), or the 7th
As shown in Figure G, when the main signal Got of the G tube output is delayed (shifted to the right by Δ1), the sample-and-hold voltage SH in Figure 7 J has positive polarity and shows a level corresponding to Δ1.Rv Or, if the output of the B tube is ahead of the main signal (shifted to the left by Δ2) as shown in Fig. 7K, the position deviation signal BEG is as shown in Fig. 7, but opposite to Fig. 7H. The error signal representing the amount and direction of deviation by changing the polarity is the seventh signal.
As shown in Figure M, it has negative polarity. Therefore, the sample and hold voltage SH has a negative polarity as shown in FIG. Beam deflection device for the corresponding B tube (2) or B tube (3) as appropriate.
(c) is controlled. As a result, the output of the B tube (2) or B tube (3) is adjusted so as to almost match the main signal Go of the output of the G tube (4) as shown in Fig. 7. are not equal to each other, so even if the image positions by the respective outputs match, the level of the positional deviation signal does not exceed zero as shown in FIG.
As shown in FIG. 7Q, the error signal ER of the output 1 has opposite polarity at the rising and falling edges of the video signal, so the sample and hold voltage becomes zero.

The control circuit basically consists of a comparator (26), an up/down (U/D) counter (27), and a D/A converter as shown in FIG. The output S I-I of sample hold circuit (10 is sent to comparator 06) and compared with the ground potential (OV), and the polarity of the positional deviation information (in the horizontal direction, the right side with respect to the output image of G tube (4) or left) is detected. The detection output COM which becomes high level or low level corresponding to the polarity f is the up/down control human power U/of the up/down counter (5).
The counter (27) performs counting increment or decrement operation depending on the high level or low level of the detection signal COM.

The output of the counter (5) is given to the D/A converter (c), converted to an analog control voltage, and then added to the sawtooth wave signal 8AW for deflection in the adder circuit (21) as a DC bias voltage. The output of the adder circuit is given to the drive amplifier 001, and the B tube (2
) or the deflection current is passed through the deflection coil Oυ of the B tube (3).

Sample and hold circuit (Displays the positional deviation information of lfil) If the sample and hold voltage 8H is positive polarity,
The output COM of the comparator 06) becomes high level, the count value of the counter (5) decreases, and this causes the coil 0
The bias current of υ decreases, and the deviation from the output image of the G tube (4) becomes smaller so that the B tube (2)! or B tube (3
) is moved to the left.

Conversely, if the sample and hold voltage SH has negative polarity, the count value of the G counter ρη increases, and the horizontal scanning position is shifted to the right, causing a position shift to the left with respect to the output image of the G tube (4). The output image of the B tube (2) or B tube (3) that was previously displayed is moved to the right.

(121 In this way, by repeating the detection of deviation information and the change of the DC bias amount of the deflection current according to the detection result, the positional deviation of the output image of each image pickup tube gradually becomes smaller by f, and the horizontal registration The up/down counter (27) is stopped at the end of the adjustment by determining whether the reduction in positional deviation has converged.

Vertical registration adjustment is also performed in the same manner as described above. In FIG. 5, the image edge signal in the vertical direction is the output α of the G tube (4) and the output α delayed by 1H i! i! +5) (61ζ thus 2H
The edge signal of the output of the subtractor C4J is formed by subtracting the difference between the signal and the signal delayed by the reference G
T delay IWG for phase matching with the main line signal Go of the output of the tube (4)! 51 and is sent from the ■ (vertical) contact side of the changeover switch aυ to the multiplier a. The operation for detecting (2) deviation information by the circuit after the multiplier Q21 is the same as the operation for detecting H deviation information.

Registration adjustment based on the detection of the above-mentioned correction data for H deviation and V deviation is performed in the screen division area (7 x 7
) for both the B pipe (2) and the R pipe (3). As mentioned above, the deviation correction data obtained by dividing each divided area is temporarily stored in the memory area as shown in FIG. Written to the expanded memory area as shown.

FIG. 8 is a block diagram showing a specific example of the control circuit shown in FIG. 5 for performing this series of data processing.

The circuit shown in Figure 8 is mainly based on the microcomputer C.
Consists of PU and memory (ROM, RAM),
The functions corresponding to @'s up/down counter (27>, etc.) are achieved by a microcomputer program.

In FIG. 8, a counter corresponding to the up/down counter (27) in FIG. 6 is constructed by an arithmetic unit of a CPU (central processing unit) C34) and a register. The output data of this counter passes through the data bus (c), latch circuit (7), full adder G7), latch circuit (to), and is further processed via buffers (39a) to (39d) and D/A. The beam deflection device (221 or (c) (Fig. 5) of the B tube (2) or R tube (3) is given as a registration adjustment signal.The image position obtained from the comparator 2 of Fig. 6 The detection signal COM indicating the direction of deviation is given to the CPU (34) via the input/output circuit (10 ports) (41), and the high and low levels of this detection signal (accordingly, the counter in the CPU (34) The clock pulse of this counter may be the vertical synchronization signal VD used in the television camera, and this clock pulse VD is sent from the clock generator (47) of FIG. 8 to the CPUQ4). It will be done.

Then, as described above, the beam deflection current is changed by increasing or decreasing the count value of the ζ counter, and furthermore, the direction of image position deviation after the change is detected by the detection system shown in FIG. By repeating this (thereby, the amount of positional deviation of the image is gradually reduced, a predetermined 115 (bundle) registration matching point (corresponding correction data) is obtained from the counter.

This correction data is stored in random access memory (RAM)
It is stored in the corresponding address of M3.

The memory M3 has an area (7×8) shown in FIG. 2, and correction data for registration adjustment obtained for each of the screen division areas in FIG. 1 is written to the corresponding address. The control address corresponding to FIG. 2 of memory M6 is supplied by the CPU 34) via the address bus (45). Further, gate pulses GE specifying each of the divided regions in FIG. 1 are generated by a gate pulse generator (421) and sent from terminal 4 to an AND gate (II) in FIG.

When data detection for one channel (■ deviation or H deviation of B tube (2) or R tube (3)) is completed, the memo IJ
- The contents of M3 are transferred to CP one after another through data bus c351.
UC34) is sent, and interpolation calculation is performed to interpolate between the data in the seven column directions. Interpolation calculation (The necessary programs and the program to control the entire system are written in a read-only memory (ROM) M4t. Also, a part M3' of the memo IJ-M3 is used as a calculation register. Interpolation The result is data bus c151
The data is written to the memory M2f having the memory area shown in FIG. 4 through one buffer (four wings).

Next, the correction data for one channel corresponding to the entire screen stored in the memo IJ-M2 is read out in synchronization with the beam scanning of the image pickup tube, passes through the full adder 07), the latch circuit (to), and then further The signal is applied to the deflection device of the corresponding image pickup tube through a selected one of buffers (39a) to (39d) and D/A converters (40a) to (40d). In this operation, the buffer (4) is opened, and the address for memory M2 is determined by the address counter (4).
6) Given by. As a result, an image output whose registration has been adjusted based on the contents of the memory M2 is obtained, and a second registration adjustment is performed based on this image output. The writing and reading of the memo IJ-M2 is controlled based on the output of the control circuit.

The secondary correction data required for the second registration adjustment is sent from the up/down counter provided in the C'PUC'14) to the data bus 08 and the latch circuit (to) to the full adder as in the first time. 07), where it is added to the previous correction data from memo IJ-M2, and then subjected to D/A conversion as described above and applied to the deflection device of the corresponding image pickup tube. The count increase/decrease of the up/down counter (the secondary correction data thus detected is stored in the corresponding address of the memory IJ-M3).

This secondary correction data is the fine adjustment for the first adjustment valve.

When the second registration adjustment for each of the screen division areas shown in FIG. 1 is completed, the contents of the memory M3 and the contents of the memory M2 are added in the CPUC 34) and stored in the memo IJ-M3 again. Next, the correction data in the memory IJ-M3 is interpolated in the direction of seven columns in the CPUQa), and the interpolated data is written in the memory M2G.

Regarding the above registration adjustment or misalignment of each of the B tube (2) and R tube (3), as mentioned above, twice,
Also, regarding H-shifted eggs, 4. It will be held twice. By repeating such readjustment based on the previous registration adjustment result, extremely accurate correction data can be obtained. Especially the first
In the screen division area shown in the figure, correction data is statically detected by applying a bias in each direction, but if the detected primary correction data is read out by synchronizing beam scanning and applied to the deflection device of each image pickup tube. , the frequency characteristics (dynamic characteristics) of the deflection device (because of this influence, the beam cannot be controlled according to the correction value. Therefore, an adjustment error occurs that cannot be corrected with just one registration adjustment. However, as mentioned above, registration By readjusting, it is possible to bring the adjustment error closer to zero within a detectable range.

Furthermore, when the correction data obtained in the first registration adjustment is read out in synchronization with beam scanning and given to the deflection device as a correction signal, this correction signal must be a high-frequency signal having a frequency at least four times the horizontal scanning frequency. However, this high-frequency credit card causes distortion due to the frequency characteristics due to the inknictance of the deflection system of the image pickup tube. However, in detecting correction data during registration adjustment, a DC signal determined according to the increase or decrease in the count of an up-down counter in the CPU'<34) is applied to each deflection device as a correction signal for each screen division area. Therefore, this correction signal is not affected by the frequency characteristics of the deflection system at all. Therefore, extremely accurate correction data can be obtained.

In addition, in the second and subsequent registration adjustments, the primary correction data output from the memo IJ-M2 and the DC secondary correction data created by the CPU Q4 are added in the full adder 0 shown in Fig. 8. Therefore, the addition result may overflow. Therefore, the carry output of the full adder C37) is detected by the overflow detection circuit (50), and when an overflow occurs, predetermined bias data is sent from the detection circuit (501) to the data bus via the latch circuit 15, and the overflow is detected. The state is being reset.

The correction data detected and interpolated as described above and stored in the memo IJ-M2 is processed through the full adder 07), the latch (to), and the selected one of the buffers (39a) to (39d). Note II-M1 to M1/// This memory M1~M1''' is the memory IJ
- has the same area as M2 (Fig. 4), and Ml is R tube (3)
M1' is the H channel of the R tube (3),
M1'' is assigned to the V channel of the B tube (2), and M1'' is assigned to the H channel of the B tube (2). The buffers (39a) to (39d) are connected to each channel (R/V) by a control signal given from the B/S (buffer select) decoder 6 through the game 1-631.

R/H%B/V, B/H).

Furthermore, the memories M1 to M1'' are selected corresponding to each channel by a control signal applied from a C/S (chip select) decoder 64) through a gate 6ω. It operates based on a control signal supplied through an output circuit (41).

The contents of the memories M1 to M1'' are read out in synchronization with the beam deflection operation according to an address signal applied from the address generator 6e through the address bus 67), and are read out from the corresponding D/A converters (40a) to (40d) to the deflection device t (221e3) of each image pickup tube (21(3)).

As a result, registration adjustments are made in the ■ and H directions of the B tube (21) and R tube (3), respectively, using the G tube (4) as a reference, and video output without color shift is obtained from the television camera. The writing and reading of each of the memories M1 to M1'' is controlled in response to a control signal 1 supplied from the write/read control signal generator (60) through the gate I!58). The control signal generator No. 0) forms write/read control signals based on the outputs of the control circuit (48J) and the clock generator ('+9).

Next, FIG. 9 is a flowchart summarizing the above-mentioned registration adjustment operation. First, the adjustment operation is started by operating the camera's adjustment start button, and in process (100), 1 preset data is loaded into the memory M2M, and the process (
101), the preset data of M2 is saved in the memo IJ-Ml~
M1''.

This preset data may be, for example, 80H (hexadecimal representation), and in this case, the D/A converters (40a) to (40H)
0d) is zero, and the amount of correction of the beam deflection current of each image pickup tube is zero.

Next, in judgment (102), the presence or absence of a start signal is detected. This start signal may be, for example, a signal generated by passing the G tube (4) to a reference number and moving the center position of the screen of the B tube (2) and the R tube (3). This automatic centering circuit may have the same circuit configuration as shown in Figures 5 and 6. Prior to automatic registration adjustment, the image centers of the six tubes are aligned in advance and the amount of registration correction is determined. It is designed to be as small as possible. Note that when the centering is performed manually, the configuration is such that a start button is operated to generate a start signal when the manual adjustment operation is completed.

Next, in process (103), one of the four channels (V deviation, H deviation of B tube and R tube) is specified, and preset data is written to memo IJ-M2 in process (104). This preset data writing is carried out in order to reset the contents of the memo IJ-M2 before starting the registration adjustment of each channel, and the preset data is data 80H (corresponding to the non-adjustment amount). (Hexadecimal display).Priscella in C)? Therefore, during the previous registration adjustment process, the memory M
The data recorded for 2t is erased. Next-this processing (1
05) to change the number of registration adjustments (primary adjustment, 2
A counter (REGI loop counter) that counts the next adjustment......] is preset.

The next process (103) determines whether the specified channel is H or V in judgment (106), and if it is H, the blur correction data is loaded into the memory M3 in Figure 8. The data I10 subroutine (107) is executed, and the memo Q-M3! 7 for this imported data.
Interpolation processing in the column direction is performed in a subroutine (108). When the interpolation process is completed, it is determined whether the count value of the REGI loop counter is 4 or not in judgment (109). If it has not reached 4, the correction data import subroutine (
107) Go back. This loop is repeated four times to perform first to fourth registration adjustments. When the four adjustments are completed, the memo IJ-M is processed in step (110).
2 data or the corresponding memories M1 to M1”' (R/
V, R/H.

B/V, B/H).

If the above judgment (106) branches to the registration adjustment in the ■ direction, the same data acquisition and interpolation subroutine (107X108) as in the H direction is performed.
In judgment (111), it is determined whether or not the RBGI loop has been performed twice. ■ Regarding direction deviation correction, since the pixel unit in the vertical direction of the screen is originally a horizontal scanning line,
Almost satisfactory adjustment results can be obtained with just one registration adjustment.

Processing (110) #When the contents of memo IJ-M2 are transferred to the corresponding memories M1 to M1/// #, it is determined in step (112) whether or not the adjustment of all four channels has been completed. A determination is made, and if NO, it is processed (
104) Go back and start adjusting the remaining channels. Once all channels have been adjusted, all of the registration adjustment operations performed by circuit G in FIG. 8 are completed.

Next, FIG. 10 is a flowchart showing details of the data I10 subroutine (107) for taking in correction data in FIG. FIG. 11 is a diagram showing a data convergence state when detecting deviation correction data.

When entering the data "10 Safroutine (107), the control address of the memory IJ-M3 corresponding to each divided area in FIG. 1 is set (processing 120). The control address SA of the set memory M3 is (121) and the 8th
Output to the input/output circuit (PIO) (41) shown in the figure,
This input/output circuit (41) is connected to a gate pulse generator (42).
(This is sent to the gate pulse generator (4). In step 4, the control address SA and the scanning of the beam output from the address generator (56) are synchronized with the address and the gate representing the position of the screen division area. A pulse GE is formed, and based on this gate pulse, the detection system shown in FIG. 5 detects correction data for the ■ deviation and H deviation for each divided region.

Next, in the judgment (122) in FIG. 10, it is determined whether it is the count value of the REGI loop counter, and if it is the first registration adjustment, the possible change range of the count increase/decrease of the measurement up/down counter in the CPU (34). 8DH (1
register r in the CPU (hexadecimal)
This data 80H is loaded (process 123). Then, the initial value of the up/down counter is preset to 80H [processing 124].

In this state, as shown in FIG. 11, the output value of the up/down counter becomes 80H, and the amount of correction for the beam deflection f of the image pickup tube to be adjusted is zero.

Further, the step width r3 for increasing and decreasing the count of the counter is 80H. The contents of the counter are transferred to latch 06) through the CPU (34i to data bus 05) in FIG. 8 in process (125). The output of latch 06) is D/A
This is converted into a beam deflection system (this is added as a correction current).

In the next process, the data in the register r3 that stores the changes in the counter is halved by %ζ (process 126λ).Thus, the step width for increasing and decreasing the counter is set to 80H/21. Then, judgment (127 ) and CPU (
34) The presence or absence of the vertical synchronizing signal VD sent to the terminal is detected, and if detected, the up/down information (instruction data in the direction of deviation correction) U/D indicated by the output COM of the comparator (26) in FIG. However, the input/output circuit in Figure 8 (from 4υ to C
PU (Foundation) cloud is taken in [Processing 128]. This up/down information is determined in a judgment (129), and if it is up, an up/down counter is set to r3 (=8) in a process (130).
The count increases by 0H/2). Further, if the up/down information is down, the count value of the counter is decreased by r3 in a process (131).

Next, judgment (132) determines whether the step width r3 of the counter has reached 1 bit (1 bit). Judgment (132)
) or NO, the process returns to step (125) and the contents of the counter are latched and transferred. As a result, a correction amount (+r3/2) corresponding to the increment of the counter is given to the beam deflection system, as shown in FIG. 11, for example. Thereafter, in the same way as described above, the step width r3 is halved to % for each correction, and the count value of the counter is increased or decreased by r3 in response to the U/D data l. This up/down counter increase/decrease loop is repeated until r3 exceeds 1 bit, and the correction data of the counter output becomes +r3/2, +r3/4, +r3/4, -r6
/8, -r6/16, etc., and the target value S1 converges.

When r3=1 is reached, VD detection is performed in the same way as described above (judgment 127') with the step width of the counter exceeded by 1 bit i.
), U/D data capture (processing 128'), up/down determination (judgment 129'), increasing or decreasing the counter by r3 (processing 130', 13 pieces), and transferring the counter contents to the latch (processing 125') data processing is performed. Then, when this 1-bit increase/decrease is repeated four times as shown in Fig. 11, this is detected in judgment (133),
It is assumed that the correction data has almost converged to the target value, and processing (
At step 134), the data of the contents of the counter is stored in the corresponding control address of the memory IJ-M3. This completes the first registration adjustment for one of the divided areas in FIG. 1, and then in the process (135)
- The control address of M3 is incremented by one, and registration adjustment for the next divided area begins. and judgment (136)
In the thorns, the end of adjustment is detected when all addresses are stuck.
The processing loop of ■→■ in FIG. 10 is repeated.

The first registration adjustment for all m (7!19) of the 49 divided areas in Figure 1 has been completed, and the correction data required for the adjustment has been applied to all addresses of the memo IJ-M3. When this is written, the average value data before and after the address of M3 corresponding to the horizontal blanking interval I-I-BLKf in Fig. 1 is written (processing 1).
67). This completes the first data I10 subroutine (107) and returns to the main program shown in FIG. In the main program, as described above, the data interpolation subroutine (10B) is executed, this interpolated data is stored in the memory IJ-M2, and the beam deflection system is controlled based on the read data of this memory M2, and the register is ration adjustments are made.

When the first registration adjustment is completed, the RE
When the GI loop counter has been incremented by one, the data I10 subroutine (1
07) and begin the second registration adjustment. In the second registration adjustment, C go, the judgment shown in Figure 10, branching from (122) to processing (138), memo! The first correction data (CPU (34)) is read from the corresponding control address of J-M3, and the next judgment (13
9) is the size of the unadjusted data (80H) relative to the regular data)
is determined, and if it is positive, the correction data S1 is subtracted from FFH in a process (140).

The result of the subtraction is written into register r6I as variable r3/ of the up/down counter. If it is negative, conversely, in process (141), correction data is written to r3 as the counter is being varied.

After that, the same data processing as the first time is performed, and as shown in Fig. 11, starting from data 80H, +r3/2 (% of possible change), -r3/4, +r3/8...
The count of the up/down counter is increased/decreased with a step width of . Since most of the registration errors have been corrected in the first adjustment, the target count value S of the counter is small, so the step width of the counter may also be small.

A second registration adjustment is performed by increasing or decreasing the count of the counter, and once the secondary correction data has been written to the entire area of memo IJ-M3, the process returns to the main program shown in Figure 9 and interpolation calculations are again performed in the direction of the 7th column. will be held.

FIG. 12 shows a flowchart of the interpolation subroutine,
FIG. 13 is a diagram of a data string in the {circle around (2)} direction for explaining the interpolation calculation method.

In FIG. 12, first set the address N (0 to 55) of the memo +3-M3 to area in FIG. Set (process 151).Note that memory M3
Is it a one-dimensional memory with an address area of 0 to 55?
Memo IJ-M2 is in the direction of 7 rows of fleas and H as shown in Figure 4.
It has been expanded to two-dimensional memory in the column direction. Then process (
152), the data at the address corresponding to memory M3 of memo IJ-M2 is read out and added to M3. Note that in the first registration adjustment, M2 contains data 80H. Furthermore, in the second registration adjustment, M2 contains interpolated data of the primary correction data required in the previous adjustment. At this time, M6 contains secondary correction data for corrections to the first primary correction data. Therefore, the memo is processed (152)! The absolute amount of correction data is written in J-M3.

In the next process (153), the data at address N of memory 1-M3 is read out to register r1 of the CPU, and then the data at address N+8 of M3 is read out.
The data at the address is read into register r2 of the CPU. The data at addresses N and N+8 are shown in Figure 2 (
This data is adjacent in the seven column direction of the screen division area. In the next G process (154)', the interpolation number I corresponding to Nf is set. This is due to the unequal division as mentioned above. For example, if N is 16, the number of interpolations between the data of rl and r2 is 62. Next, the number of interpolations between the data of rl and r2 is 62. For example, if N is 16, divide it into 66 equal parts and
Interpolated data 11, I2 as shown in the figure...
. . , by linear approximation to a total of 3!1-T (process 155). The calculation result is stored at the address (0 to I-1) provided in Memo 1-M3.
) is temporarily stored in the temporary area M3'.

The interpolation calculation formula is as follows: (1) The value of K is increased sequentially from 0 until (I-k)=i, and the calculation result is written to the corresponding address of M3'.

Note that 1 is added to I/2 in this calculation formula for rounding. As a result, as shown in FIG.
62 between a set of data D16.924 adjacent in the column direction
The data corresponding to the scan lines of the book are calculated (thus obtained).

Next, judgment (156) is made regarding the address data N (0 to 55) of M3 at the upper end of the screen division area (0 to 7
), the middle (8 to 47), and the bottom (48 to 55).In the case of the top and bottom ends, the number is branched to A and B, and extended interpolation described later is performed.In the case of the middle, the cloud is C. (This is branched, and in the process (157), the interpolated memo IJ
-M Note the contents of address (0 to I-1) in 3'!
Addresses r3 and r4 of J-M2 are transferred. Then, the address N of memory M6 is increased by one (process 158),
Also, addresses r3 and r4 of M2 corresponding to the increased N
can be calculated (process 159).

Then, in order to perform the next interpolation calculation, the process branches to decision (160) and returns to process (152). Memo! When the process advances to address N55 of J-M5 and the interpolation for almost the entire screen is completed, this is determined at step 160 and the process returns to the main flow shown in FIG.

FIG. 14 is a flowchart showing the extension interpolation of the upper end of the screen performed in branch A of judgment (156) in FIG.
FIG. 5 is a T diagram showing the extended interpolation method.

In FIG. 14, first, in the process (161), the memo IJ
The addresses (0 to 8) are set in M3 (the calculation memory M, 3' provided here), and further processing (1
62), the address of address 5 (18-26) of the memo II-M3' is set. The address (D~89) of M3/ is the interpolated data calculated in the process (155) of FIG. 12 from the data at the upper end toward the inside of the screen. Address 5 is the storage location for the extended interpolated data.

Next, in the process (163), address 0 (K=
0) is loaded into the register r1f of the CPU. This 0
The address data is at the top of Figure 2 0.1.2...
This corresponds to data obtained with each divided area as the center of the screen. Further, in step (164), the address of M3' is loaded into the register r2 of the CPU. When extended interpolation is performed by linear approximation, as shown in FIG. 15, interpolated data r2 and data r2/ obtained by extended interpolation are at points symmetrical positions with respect to data r1 at the upper end. Therefore, since r 2 - r l = r i - r 2', extended interpolation data can be obtained using the formula r 2' = r 1x 2 - r 2 .

In the process (165), the calculation result of the above formula is stored in the register "
I am writing in 2. The calculation result is checked for overflow in judgment (166), and if there is no overflow, in process (168) 5 of memory M3' is
forwarded to the address. Note that if the data of r2 is the 1st address of M3', then the 5th address of M6' corresponds to the 25th address. If the calculated value overflows, the contents of register r2 are changed to PPH (all 1s) or 0O)I in processing (157).
(all 0).

When one extension interpolation calculation is completed T, the address 5 is decreased by one (process 169), and the address is increased by one (process 170).Then, the calculation is repeated eight times until J reaches 18#. When it is detected in judgment (171) that all of J has been completed, the memo IJ -M obtained by extension interpolation ζ
The data at addresses 5 (18 to 26) of 3' are transferred to address t of the corresponding memo!J-M2 (process 172).

When the above-mentioned extension interpolation process is completed for one of the data at the upper end, the point is returned to the 6 points in FIG. 12.

Next, FIG. 16 is a flowchart of the extension interpolation of the lower end of the screen division area, which is performed in branch B of judgment (156) in FIG. 12. This flowchart is almost the same as that shown in FIG. 14, and the address (9 ~17) Based on the data,
The difference from FIG. 14 is that extended interpolation data below the lower end data is calculated.

As described above, the memory area shown in Figure 4 (256 x 8
) are calculated, and the calculation results are transferred from the memory area to the corresponding memories M1 to M1'' as explained in FIG.

In the NTSC system, the number of scanning lines in one field screen is 262.5, and as shown in Figure 1, the screen is divided vertically (divided into 7 and each section is divided into 1 section) (18.18. 5
4. Assigning lines 72.54.18.18 results in 25
Two pieces of interpolated data (including the measured original data) correspond to each line. Therefore, Memo IJ-M2 and M
256 addresses in the ■ direction from 1 to M1″′ are required, including one address required for the data in the vertical blanking interval V-BLK.In other words, 2 bytes of memory can store data for one channel. One address for accommodating the data of the vertical blanking interval is assigned to 11 lines within the vertical blanking interval.

One address in the V direction of the memory for 11 lines of the blanking section contains the data at the top of the data obtained by extension interpolation at the top of the screen, and the data obtained by extension interpolation at the bottom of the screen. The average value with the lowest data is written.

This average value data is read out overlappingly between the 11 lines. The reason why the memories M1 to M1'' and M2 are made shorter than the blanking period of the actual video signal is because scanning is performed over a wide area in the image pickup tube up to the blanking period of the video. This is because by adjusting the registration even within the periphery of the screen, it is possible to increase the accuracy of correction to the periphery of the screen.The area surrounded by the caustic line u in the memory area in Figure 4 is N
An effective screen for the TSC method is shown.

When the embodiment of the present invention is applied to a PAL television system, the correction data necessary for registration adjustment is extracted in the same way as described above (but in the V direction of memories M1 to M1'' and M2). By changing the correspondence between addresses and lines that form the screen, NTSC and PAL
We are working to standardize the hardware and software with the other systems. In other words, in the PAL system, the scanning number in one field is 312.5 lines, so the screen division is divided into 7 lines.
For example, in order (21.21.63.84.63.
21.If you allocate 21 (lines) lines, set the vertical blanking period to 15 lines, and allocate one address,
The required ■direction address is 294+1=295,
The number of lines is 42×7+15=309. Therefore, the shortfall for scanning 9312.5 of one field is 4 lines, and if these 4 lines get stuck, four more addresses are assigned to the section at the bottom of the screen during interpolation calculation. You can create interpolated data by doing this. However, as in the case of the NTSC system, if one address is assigned to one line, ζ299 addresses are required as described above, and data for one channel cannot be stored in 2 bytes. Increasing the capacity of the memo IJ- is undesirable in terms of cost and power consumption.

For this reason, in this embodiment, when using the PAL system, 6 addresses are assigned to 7 lines, and the address increments are stopped by 6 steps (this step is stopped once, and the number of correction data read from the memory is The number of lines is almost the same.

By this process, the point Hvt in FIG.
The effective screen area of the L system is approximately the same as the effective screen area (causal line u) of the NTSC system in the memory space.

FIG. 17 is a circuit diagram of an address generator 56) that generates an address for reading out the correction data stored in the memos IJ-M1 to Mi"' in synchronization with the beam scanning of the image pickup tube.
This figure and FIG. 19 are time charts 1 for explaining the operation.

A in FIG. 18 shows the horizontal blanking section HBLK. Further, B indicates the horizontal synchronizing signal HD% used in this television camera. This horizontal synchronizing signal is applied to the H phase adjustment circuit shown in FIG. 17, and after phase adjustment as shown in FIG. 18C, is supplied to the PLL circuit. In addition, since the gate signal GE is formed in the gate pulse generator circuit (420) based on the address (based on the address generated by the address generator (c)), horizontal synchronization is performed so that this gate signal is symmetrical within the effective screen. An H phase adjustment circuit %I3 is provided for the purpose of adjusting the phase of the signal HD.

From the output of the PLL circuit, a clock pulse 32FH, which is multiplied by T32 as shown in FIG. 18, is obtained.

This clock pulse is frequency-divided by % by the divider (6]) I and sent to the clock input (CK) of the 4-bit H counter (64).
) and the carry output of this counter FH(
Horizontal frequency, Figure 18E) or inverter (Figure 18 with 6
As shown in the figure, the PLL circuit (63)) is fed back as a phase comparison signal. A clock pulse 8FH shown in FIG. 18Gf is obtained from the least significant bit of the counter (64).

This clock pulse is used as a clock for creating an address when reading H deviation correction data from the memory. Further, the least significant bit output 8FH of the counter @a and its upper bit output are applied to the non-uniformly spaced address converter I4yζ to obtain the H-axis read address (2) MAQ to VMA2 of the deviation correction data memory. As shown in FIG. 18H, this address increments from 0 to 7 at a period corresponding to the unequal division within this horizontal period.

Next (FIG. 19B shows the vertical synchronizing signal VD used in this television camera, A shows the vertical blanking interval V-BLK, and FIG. 19C shows the horizontal synchronizing signal HD. The timing signal v1) 1 shown in Figure 19 is obtained from this phase tl adjustment circuit (6G), and this timing signal sets the blanking section of the read address. The blanking (V-BLK) counter (6η) for Flip-flops for creating (6
This flip-flop (mark 6 is a V counter (69a) (69b) described later)
It is provided to control the

The V-BLK counter (67) is as shown in FIG. 19F (
② Timing signal VD l Therefore, the count value 4 is preset. This preset value is determined by preset data PS given to this counter and a high level signal obtained from the NT'SC/PAL changeover switch σ0). The count value of the V-BLK counter (6'0) increases every clock pulse FH (horizontal frequency) given from the H counter (64) via the buffer (7]), and when the count value is 15, the count value of FIG. Carry pulse 1 shown in G
Generates 5cA. The lock pulse FH is applied to the enable input (PE) of the counter (67), and the clock pulse 16FH multiplied by 16 is applied to the clock input via the buffer a21+.

Since the carry pulse 150A of the counter Qliη is given as a clear pulse to the flip-flop (61), a blanking pulse BLK having a width of 11H as shown in FIG. 19H is synchronized with the clock FH from the Q output of the flip-flop. This blanking pulse is given as a clear signal to each of the counters (69a) and (69b), so the V counter can be obtained as shown in FIG.
As shown in Figure 1, the blanking pulse BLK (jR19
After H] returns to high level by 1, the count increases in H cycles. Note that the V counters (69aX69b) are 4 each.
The bits are connected in series with each other. The clock pulse is 16FH, but since the clock FH is applied to the enable input (TB) of the counter (69a), it generates a count output of 0 to 256 that increments in H cycles. This count output is the address V MA of the V axis of the memory area in Figure 4 for reading out the deviation correction data.
3 to VMA10 (8 bits).

As described above, the H count is increased and the V counter (69
aX69b) formed by 7. m V 7 dress VM
AO~VMA 10 Hough 48 Figure (7) Memo! J-M
1 and Hi M 1” given to husband, B pipe (2) and R
■ Misalignment correction data of tube (3) is read out. Also, the address is given to a latch circuit (75a) (75b) consisting of 11 D flip-flops, and the clock s F
It is sent as 11 address at the rising timing of I-I (FIG. 18G).

Figure 18 I shows the H address ■ (axis component HM A Q,
The progressive change of HMA2 is shown.

As shown in FIG. 18, H and Iζ are read addresses HMA[] to I-IMA, 10 are read addresses VMAQ to VMA'lQ for the misalignment correction data.
half period of 8FH clock (1/1 of horizontal period)
6) is created with the delayed phase. In other words, when the correction data is read from the memory, D/A converted, and applied to the deflection system via the low-pass filter, the delay of the low-pass filter including the deflection coil between the vertical deflection system and the horizontal deflection system (
Since the time constants are different, this delay is adjusted using a phase difference of half a clock.

FIG. 18J shows the above-mentioned read address VMA or HMA and the screen division area (
0,1,2・・・・・・・・・・・・・・・〕
A part of the gate signal GE generated by the gate pulse generator (421) in FIG. 8 is shown based on the address 8A representative of , it is necessary to take into account the delay of the low-pass filter during D/A conversion and the delay due to the integral effect of the inductance of the deflection system.Therefore, the read addresses VMA and HM A are set to the sampling gate signal GB at the time of data extraction. In other words, the read address VMA of (1) deviation correction data is read out with an advanced phase of about H/8.

Next, a case in which the television camera of this embodiment is operated in a FAT system will be explained. FIG. 19J shows the vertical blanking section of the PAL signal. When applied to the PAL system as described above, the section 1511 within the blanking section is assigned to the blanking section when reading the memory. For this reason, the selector switch σ0) shown in Fig. 17 is connected to the PAL contact side to form a low-level preset signal, and the V-BLK counter (67)
Change the preset data. As a result, V-BLK
Counter (67) LtV time 7ri'M No. VD 1
(iiR19F'ID) Figure 19K (As shown in the figure, the count value is preset to 0, and then the horizontal frequency is set to 15.
Count up to.

Therefore, the Q output of the flip-flop (decoy) is
! It becomes a low level in the 15H interval, and in this 15H interval ■Cow7'l (69aX69b) is cleared and its counting operation is prohibited. Then, the clearing of the flip-flop (when the 6th barrel is reset, V counter C69a)<69b) is canceled by the carry output 15CA, and counting from 1 to 255 is performed as shown in Figure 19.

In part, the low level output of the selector switch CO) is given to the enable input (TE) of the 4-bit 6/7 counter ση via the inverter σ, thereby causing the counter ση
or becomes operational. This counter (7711 uses clock pulse 16FH as a clock and clock pulse FH
is used as the count enable input (PR), so the counting operation is performed at the horizontal frequency.

9 is given as the preset data P8, and as shown in FIG.
When the count is 15, a carry output CA is generated. This counter 6? )'s carry output is fed back to the load input (LD) via the inverter σ sand and the negative logic OR game 1-ff9), so as shown in FIG. The count value is again preset to 9. Therefore, the counter (if?) operates as a heptad counter.

The carry output CA of the counter 6η is inverted by the inverter (7 excitation) and then given to the enable input (PE) of the V counter (69a), so when the count value is 15, the counting operation of this V counter C69a is interrupted. be done. In addition, the output of the inverter 2 is also given to the AND gate 2, so it is passed through the gate 1- (80) to the ■ counter (6
The clock FH applied to the enable input (pE) 9b) is cut off, and when the divisor value is 15, the counting operation of the V counter (69 times) is interrupted.

As a result, the V counter (6
9a) (69b) Stepwise huff Il (ko1) of counting output
Rotation stop, V7 F+/SVMA3~VMA 10G
:J5.6.6.7・・・・・・・・・11.1
2, 12, 13, . . . , the same address is generated twice every six times.

Therefore, when applied to a PAL system, Memo IJ-M1~
The contents of M1''' are read out in one of the seven lines, overlapping with the previous line.As a result, the contents of memory M1
~18 addresses on the v-axis of M1'' (21 scanning lines are assigned to this address, as shown in Figure 4).
, Same capacity memory as NTSC system (256x8)
This makes it possible to cover the effective screen of the PAL system.

Next, FIG. 20 is a circuit diagram of the vertical deflection system of the television camera of this embodiment, and FIG. 21 is a circuit diagram of the horizontal deflection system.

■Addresses VMAQ to VMA1 for reading deviation correction data created by the address generator 5G in FIG. 17
0&-1M+=Lee M1(R/V), Ml”(B/■
), and the addresses HMAQ to HMAIO for reading the H deviation correction data are given to the memory M1' (R/
H), Ml"'(B/H)f are given, and the correction data is read out in synchronization with beam scanning (Ml and M1").
The output is passed through the D/A converter (40a) (40) and a low-pass filter (not shown) to the terminal (81a) (
81 is given. ! The output of r, = M1', M1'' is sent to the terminal (81b x 81d) in Fig. 21 via a D/A converter (40b x 40d) and a low-pass filter (not shown).
f is given.

As shown in FIG.
83B) (83R) #Thus driven. Each deflection coil number has resistors (84G) (84B) (84R) connected in series, and their terminal voltages are connected to an amplifier (830883B).
) (83R), a current equal to the amplifier input voltage divided by the resistance values of these resistors is passed through each coil. The amplifier (83G) that drives the coil (82G) of the reference G tube (4) is equipped with a sawtooth wave generation circuit @5).
At I, a vertical scanning sawtooth wave signal V-8AW formed in synchronization with the vertical synchronizing signal VD is applied. Also, the amplifier (86J3) that drives the B tube (2) and R tube (3) (
At 861'L, the sawtooth wave signal is added to the adder circuit (86a
X86b).

These adder circuits (86a) (86b) are connected to terminals (86a) and (86b).
A registration adjustment signal is given from the 18X81C), and this causes the
Directional registration adjustment is performed. Each vertical deflection coil (82G) (82B882R) has frequency characteristics, so it can detect components several times the horizontal frequency.
The high frequency range of the registration adjustment signal for misalignment correction may deteriorate. However, this deterioration can be compensated for by readjusting the registration as described above.

In the horizontal deflection system shown in Fig. 21, a horizontally periodic sawtooth wave current is transmitted to six horizontal deflection coils (8) by switching and driving a transistor (C) using a horizontal synchronizing signal HD.
9B889R) (89G) is flowing. Note that the capacitor @η connected in parallel with the transistor (c) is for integration, and the diode (91) connected in parallel via the flyback transformer (90) is for damper. In addition, a correction transformer (9th floor secondary winding) is inserted in series through a capacitor 61 in the deflection current supply line to each horizontal deflection coil (89B) (89R) (89G). The primary winding of the transformer trowel is equipped with a sawtooth wave generation circuit (9
4)! Here, the horizontal periodic sawtooth wave H-8AW formed in synchronization with the horizontal synchronization signal HD or the gain adjuster (E)
, an amplifier (96), which provides horizontal deflection linearity compensation.

The horizontal deflection coil (89BX89R) (89G) has a part (89B)'(891S'
(89G)', and by adjusting these, it is possible to roughly adjust the size and center position of the output image of each image pickup tube. Also, variable resistors (97B) (97R897G) are inserted in series with each horizontal deflection coil, and by adjusting these, the approximate center position of the output of the six tubes can be aligned. Naori tube (2) and R tube (3)
By making the variable resistor (97BX97R) into a variable impedance circuit and using the automatic centering circuit described above, G
The center positions of the images of the B tube (2) and the R tube (3) may be aligned with respect to the tube (4).

Horizontal registration adjustment of the B tube (2) and R tube (3) is performed by applying a correction current to the auxiliary coil (98B898L) inserted in the form of the secondary winding of the main horizontal deflection coil (89B) (89R). This is done by flowing. These auxiliary coils (98B
) is driven by. Providing such a correction coil (from this, the main deflection coil (89B) (8911,)
Since the deflection current can be driven by a switching method and there is no need to use a class A or class 8 amplifier, power consumption can be lower.

'f, main deflection coil
)(98R)ζThe correction amount for registration adjustment due to
9 liters) may have a small output capacity.

In addition, in the horizontal scanning section, the main deflection coil (89B) (89"
) is short-circuited, so the energy supplied by the auxiliary coil (98B) (9si+) will leak through the main deflection coil to the low-impedance drive circuit. This affects the magnetic flux of the correction coil.The high frequency component of the magnetic flux of the correction coil is attenuated by the integral action.However, as mentioned above, readjustment of the 2nd, 6th, and 4th order registration is repeated. By doing so, it is possible to create a correction signal that compensates for this reduction in frequency, and this problem can be completely resolved.In addition, even in the vertical deflection system, even if an auxiliary coil like this for registration adjustment is provided, good.

Note that in the above embodiment, 7 of the correction data for each scanning line
Column direction interpolation was performed using @line approximation (first order), but second order, third order
The following interpolation can be employed.

Although interpolation in the 8-column direction is not performed, the memory area may be expanded to perform interpolation in the H direction. When it comes to the number of screen divisions, it is preferable to divide the screen into an odd number as in the embodiment (7×7). In the case of odd-number division, a divided area is created at the center of the screen, so as mentioned above, if you apply a DC bias to the main deflection coil in advance to perform centering adjustment around this central divided area, then perform registration adjustment. Less correction by auxiliary coils is required.

The present invention divides an effective screen portion into a plurality of areas (for example, 7 x 7), and registers the output signal of another image pickup tube (Bv or R tube) with respect to the output signal of a reference image pickup tube (G tube) for each divided area. ration error (positional shift of output image of 6 tubes)
is detected and stored in the first memo IJ-(M3), and the second memo IJ- has a memory area (e.g. 256×8) expanded at least in the vertical direction of the screen with respect to the divided area of the screen. (M2)! The interpolation data calculated based on the first memory area is loaded, and a correction signal corresponding to the output of the second memory is applied to the beam deflection control means of the other image pickup tube. Furthermore, the effective screen portion is divided into a plurality of areas so that the area of the division is so small that the peripheral area is obscured.

Therefore, by using relatively sparse screen divisions (for example, 7 x 7), registration error data with a smaller number of samples can be detected in a short time, and data can be interpolated between sampled data. Since data is created that corresponds to horizontal scanning lines, more precise registration adjustments can be made.

Furthermore, by making the divided area smaller in the peripheral area where the registration deviation is larger, it is possible to improve the adjustment accuracy without increasing the number of samples, that is, without increasing the detection time.

[Brief explanation of the drawing]

Fig. 1 is a plan view of a screen for explaining the automatic registration adjustment method according to the embodiment of the present invention, and Fig. 2 shows a memory area for storing misalignment correction data in each of the screen division areas (Fig. 1). 6 is a diagram for explaining the operation of interpolating the middle part of vertically adjacent data in the memory area of FIG. 2, and FIG. 4 is a diagram showing the registration adjustment data formed by interpolation. 5 is a diagram showing a memory area for storage, FIG. 5 is a block circuit diagram showing an example of a detection circuit for horizontal and vertical deviation correction information, and FIG.
7 is a waveform diagram showing the operation of FIG. 5, and FIG. 8 is a detection and storage of correction data for H and V deviations. , interpolation, and registration adjustment control; FIG. 9 is a flowchart summarizing the registration adjustment operations in FIG. 8; FIG. 10 is a detailed diagram of the data I10 subroutine in FIG. 9. Fig. 11 is a diagram showing the data convergence state when detecting deviation correction data, Fig. 12 is a flow chart of the interpolation subroutine in Fig. 9, and Fig. 16 is a diagram showing the interpolation calculation method. Figure 14 is a flowchart showing extended interpolation at the top of the screen, Figure 15 is a diagram showing the extended interpolation method, Figure 16 is a flowchart showing extended interpolation at the bottom of the screen, and Figure 17 is a memo. IJ-M1~M
1'' is a circuit diagram of an address generator for generating an address to be given to 1''; FIGS. 18 and 19 are time charts for explaining the operation of FIG. 17, and FIG. 20 is a vertical diagram of the television camera of the embodiment. The similar circuit diagram, Figure 21, is a circuit diagram of the horizontal deflection system.In the symbols used in the drawings, (1)...
・・・・・・・・・Screen (2 to 3×41...
・・・・・・Image tube (5X61・・・・・・・・・・・・
1H delay line (9)・・・・・・・・・・・・・・・Subtractor (1ri・・・・・・・・・・・・Multiplier 0 phrase
・・・・・・・・・・・・・・・Subtractor (L6)・・・・
......Sample and hold circuit Cυ...
・・・・・・・・・・・・Control circuit (22) CI! 3
)・・・・・・・・・・・・・・・・・・・Deflection device (26)・・・・・・・・・・・・・・・・・・・
・・・Comparator (27)・・・・・・・・・・・・
・・・・・・・・・・・・Up/down counter 04
)・・・・・・・・・・・・・・・・・・・・・
CPU (40a) ~C40d)=-・-・-D/
A K Exchanger 1!56)・・・・・・・・・・・・・・・
・・・4・・・・・・Address generator (64a)・
・・・・・・・・・・・・・・・・・・H counter (69
aX69b)・・・・・・・・・V counter (70)・
・・・・・・・・・・・・・・・・・・・・・・・・Changing switch υη・・・・・・・・・・・・・・・・・・・・・
...6/7 counter (82BX82 assistant (82G)
・・■ Deflection coil (89B) (89R) (89G)・・
Horizontal deflection coil (98BX98R)・・・・・・・・・
Auxiliary coil M3 ・・・・・・・・・・・・・・・・・・
...First memory M2 ......
......Second memory M1~M1'''・
・・・・・・・・・・・・Memory. Agent Masaru Saturn〃 Yoshio Tsunekako〃 Toshiki Sugiura 1987-949 Figure JP-A-58-9497 (27)

Claims (1)

[Claims] Means for detecting the registration error of the output signal of another image pickup tube with respect to the output signal of the reference image pickup tube in each divided area in which the effective screen portion is divided into a plurality of areas such that the area becomes smaller toward the periphery; a first memory having a storage area corresponding to the divided area and storing the registration error; and a second memory having a storage area expanded at least in the vertical direction of the screen with respect to the divided area of the screen. , interpolation means for creating interpolation data to fill the second memory based on the data stored first in the first memory, and writing this into the second memory, The beam deflection of the other image pickup tube is controlled according to the data stored in the second memory, and the registration of the output image of the reference image pickup tube (in contrast, the registration of the output image of the other image pickup tube is adjusted). A registration adjustment circuit for a multi-tube color camera configured to