SU1317687A2 - Device for generating signal for correcting distortions of television picture - Google Patents

Abstract

Invention m. used in broadcast and applied television in the composition of television systems automatic. real-time image distortion correction with feedback. The purpose of the invention is to improve the accuracy of image distortion correction. The device contains a video signal sensor 1, test table 2, synchronizer 3, r-4 of the reference signal, r-r 5 of the weight signal, r-r 6 of the orthogonal signals, processor 7, memory block 8, weight sum block 9, block subtraction, shaper 11 signal module, trans (L 00 d O5 oo 14)

Description

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multiplier 12, integrator 13, coordinate block 17, block 22 for specifying a threshold. The ADC 14, the memory register 15, the digital subtraction unit 16, the comparator 18, the address memory block 19, the memory register block 20, the gating unit 21, the D / A converter 23, the Unit recorded in the memory cell of the block 19, reiterate the need for correction and the address of this cell is about the coordinate of the area to be corrected on the television raster "After filling in block 19 with information about the areas to be corrected, include

one

The invention relates to television and can be used in mainstream and applied television as part of television systems for automatically correcting distortions of images with feedback, in real time.

The purpose of the invention is to increase the accuracy of the distortion correction of a television image.

FIG. Figure 1 shows a structural electrical circuit of a signal shaping device for correcting distortions of a television image on FIG. 2, a block electrical circuit of an address memory block. .

A signal conditioning device for correcting distortions of a television image includes a video signal sensor 1, test table 2, a synchronizer 3, a reference signal generator 4, a weight signal generator 5, orthogonal signal generator 6. The processor 7, the memory block 8, the weight summation block 9, the consecutively connected subtracting unit 10, the shaper 11 of the signal module, the multiplier 12 and the integrator 13, the analog-to-digital converter 14, the memory register 15, the digital subtracting unit 16, the coordinate unit 17, comparator 18, address memory block 19, memory register block 20, gating block 21, threshold setting block 22, digital-to-analog converter 23, the sensor signal output

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Cessor 7 for the execution of the Korrektsi P. program. On the data bus, the code of the first test action is recorded at the first address in one of the blocks 19. Similarly, an assessment by the integral criterion of quality occurs, the minimization program is carried out. Then the processor 7 determines the optimal code of the second adjustment parameter, etc. for all parameters. Further, the address is incremented by one and the search for optimal control codes for the other correction area is performed. 2 yl

five

five

0

five

0

the video signal is connected to the first input of the subtraction unit 10, the sensor output T is connected to the synchronous inputs of the generator 5, generator 4, synchronizer 3, generator 6 and the counting input of the coordinate unit 17, the first, second and third outputs of the synchronizer 3 are connected, respectively, to the synchronous input of the processor 7 - the ling input of the generator 5 and the generator 6 and the installation input of the integrator 13, the output of which is connected to the data input of the processor 7 and the input of the analog-digital converter 14, the output of which is connected to the input of the register 15 and first the input of the digital subtraction unit 16, the second input of which is connected to the output of the register 15, and the output to the first input of the comparator 18, the second input of which is connected to the output of the block 22, and the output to the first input of the memory block 19, synchronous output unit 17 is connected to sync inputs of analog-digital converter 14 and register 15, and the address output is with the second input of memory block 19, the first output of memory block 19 is connected to the first input of register block 20, and the second output is connected with control input 21 Gating, output of block 20 registers a first input gating unit 21, whose output is connected to the input of the digital to analog converter 23, whose output is connected to the correction input of the sensor 1, the output of the generator 4 is connected to. the first input of the subtraction unit 10, and the output of the generator 5 with the second input of the intermixer 12, the first and second outputs of the processor 7 are connected to the corresponding first and second inputs of the memory block 8 and the second and third inputs of the register unit 20, the output of the 8 pa1 1 unit is connected with the first entrance

block 9 weight summation, the second for black and white areas in the vertical

the input of which is connected to the output of the generator 6, and the output to the control input of the sensor 1. The output of the sensor 1 is connected to the second input of the subtraction unit 10, the output of which over the form-15 forms a distorted signal. For

the globalizer 11 is with the second input of the multiplier 12, the output of which is connected to the input of the integrator 13. In addition, the block 19 of the address memory contains

a memory block 24, a pulse counter 25, 20, etc.) of sensor 1 are given signals for

register 26, end decoder 27, field end decoder 28, digital switch 29, field selection block 30, AND 31 element, OR 32 element, keys 33 and 34, common bus 35 and power supply bus 36, with digital input the switch 29 is the first input of the memory block 19, the second input of the digital switch 29 is connected to the common bus 35, the control input to the first input of the OR 32 element and the output of the block 30, the first input of which is connected via the key 34 to the common bus 35, and the second input is connected to the output of the decoder 28 and the first input of the register 26, the second input of which connected to the first output of the decoder 27, the second output of which is connected to the first input of the counter 25, the setup inputs of which are connected to the outputs of the register 26, and the outputs are connected to the installation inputs of the register 26 and are the first output of the block 19. The additional output of the counter 25 is connected to the first 45 data bus in the form of binary codes on

The input of the memory block 24 is the second output of the block 19, the second input of the memory block 24 is connected to the output of the AND 31 element, the first input of which is connected to the output of the OR 32 element, the second input of which is connected via key 33 to the bus 36. The inputs of the decoders 27, 28, the memory block 24 and the second input of the And 31 element are the second input of the memory block 19, the control input of the memory block 24 is connected to the digital switch 29.

A signal conditioning device for correcting distortion of a television image works as follows.

Sensor 1 deploys an optical reference image from test table 2. Test table 2 is a black-and-white optical test, in which alternating

and the horizontal direction, with the length of these sections varying randomly. At the signal output of sensor 1

correction of distortion at the control input (focusing-deflection system, video amplifier, y-corrector, cathode-ray tube electrodes

five

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distortion correction from the outputs of the weight summing block 9. Each individual signal for the correction of distortion represents a weighted sum of the orthogonal signals defined in the raster field and synchronous with the television scan. Therefore, to generate correction signals, a set of orthogonal signals from the generator 6 output is fed to the second input of the weight summing unit 9, and the weight control signals of the orthogonal signals in the form of weight data of the orthogonal signals are fed to the first input of the weight summing unit 9 binary codes. Before starting the generation of signals, the initial values of the signals for each of the formed corrections of signals are set at the second output of the processor 7 to correct the distortions of the television image. These initial values of the control signals are given by

0

the information inputs of the memory block 8 are written into its corresponding registers at the address received via the address bus in the form of a binary code from the first output of the processor 7 to the recording input of the memory block 8. As a consequence, the output of the weight summation unit 9 produces signals for correcting the distortions of the television image in the form of initially weighted sums of orthogonal signals. These signals affect the control circuits of the sensor 1, at the signal output of which an initially corrected signal from the optical reference image is formed. Next, the video signal is fed to the second input of the subtraction unit 10, and to the first input is a signal from the output of the generator 4. At the output of the subtraction unit 10, a differential signal is generated, which is fed to the input of the imaging unit 11. The output signal of the latter produces an error signal the current values of the originally corrected video signal and the electrical reference signal. The error signal characterizes the distribution in the raster field of all types of television distortions in the originally corrected video signal, and consequently, the accuracy of the formation of the originally generated signal to correct the distortion i The error signal from the output of the former 11 is fed to the first input of the multiplier 12 to another input the weight signal comes from the output of the generator 5, the shape of the weight signal is chosen so as to ensure the required correction accuracy in the raster field. In the code of the multiplier 12, an error signal is weighted over the raster field, which is fed to the first input of the integrator 13, to the installation input of which a reset pulse is applied to the third output of the synchronizer 3 via one television sweep field at the end of the frame damping pulse. The integrator 13 forms, at the end of the forward stroke of the vertical sweep, an integral estimate that uniquely determines the quality of the video signal distortion correction and, consequently, the accuracy of the signal generation for the correction. The integral estimate is fed to the data input of the processor 7, where it is converted into a binary code, which is the evaluation count, which is written to the corresponding memory cell of its storage device at the moment the synchronous input pulse arrives from the first output of the synchronizer 3. After that, the processor 7 changes according to a given program, at its second output, the values of the control signals of the weighting coefficients of the orthogonal signals with respect to their previous values. These changes are applied to the first input of the weight addition unit 9, the output of which

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modified signals are formed to correct the distortion of the television image that is fed to the control input of sensor 1. As a result, a new integral assessment of the quality of correction is received at the data input of processor 7 from the output of integrator 13 A similar cycle is repeated several times over a set of numerical estimates of the integral quality assessment, using one of the numerical minimization algorithms, the optics are computed. The minimum value of the control signal of the weighting factors of the orthogonal signals and the result of the calculation are recorded in the cells of the memory block 8, and the output of the weight sum block 9 finally generates a correction signal. Other correction signals are also formed in a similar way, which, by acting on the corresponding sensor control circuit 1, corrects the distortion of the television image. They enter the counting input of the coordinate block 17

20

25

kf

pp

Where

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pulses with the following frequency: fcT-p - line frequency; k is the number of correction zones stacked along the line, and pulses with a frequency ff-m from the sensor stroke 1 ..kf

page - synchrony - Pulses with frequency

page goes to the counting input of one counter, and pulses with a frequency f (; .p - to the counting input of another counter. One counter, having a split div k, divides the line into k sections, the other divides the personnel direction into h sections Thus, across the raster field, kh sections are organized, each of which

0, one of the possible conditions that two counters can receive is assigned. In order to synchronize the analog-digital converter 14 and the memory register 15, at the syncro output of the coordinate block 17, differentiated pulses of the kfcrp frequency are received. Analog-digital converter 14 is synchronized to the digital input signal of the analog signal received at its input . The digital signal from its output goes to the D-inputs of the register 15 and the second input of the digital subtraction unit 16.

5 Writing to register 15 occurs at the same frequency as - and synchronizing analog-to-digital converter 1 s. If a digital signal appears at the output of analog-digital converter 14

1st transform, then in register 15 a digital signal (i-1) -ro transform is recorded. Therefore, a digital signal i-ro conversion appears at the second input of the digital subtractor 16, and (i-l) -ro at the first input. The positions of the switches in the threshold setting unit 22 determine the threshold code, which is compared with the difference code i-ro and (i-1) -ro of the conversion cycle. If the difference code arriving at the first input of the comparator 18 turns out to be greater than the threshold code arriving at the second input of the comparator 18. A high logic potential appears at the output of the last, if it is less, a low potential. Memory unit 19 (FIG. 2) has several modes of operation. In the first mode, it is prepared for operation, for which the key 33 is closed, as a result of which one of the inputs of the OR element 32 is fed

20 of this cell is about the coordinate of the area to be corrected on the television raster. Across the field, the entire raster is scanned, and the necessary memory cells are filled with units.

a high logical potential, which enters the input of the element And 31, at 25 The third mode of operation begins - the second input of which receives the impulse of information recorded in the passes with a frequency These pulses are passed through the block 19 in real scale And 31 and the time arrives synchronously with the TV input. Writing and reading the block 24 is turned on. Each raster section, memory, initiating the recording mode in this 30 lying correction, you need to select a block. To the information input of the block, pour a section of memory in block 20 of the .24 memory from the output of the digital commutator in which the code of the | Torus 29 is low logic response. In addition, this code must level, and to the address input The change of the signal appears synchronously with the scanned synchronously with the television image in the required place. For the coil, the code generated by the counter 25 addressing the memory plots in block 20 of memory block 19. As a result, zero frames are written in the cell of the memory block 24 (and there are as many as the splitting zones in the coordinate block 17). After opening the key 33, the recording process stops, since the recording pulses are removed by AND 31. The second mode of operation is the key 34 is triggered, and a block 30 is initiated, which generates a pulse of duration into the television field. This pulse switches the digital switch 29, connecting the information input of the memory block 24 to the output of the comparator 18. The same potential at the second input element and OR 32 connects to the input recording pulses recording-reading unit 24

the registers use a counter 25, which counts the number of units recorded in memory block 19. But one

The 40th row of the memory block 19 is scanned as many times as the image lines form the correction portion of the frame. In order to exclude an extra count when repeating, a register 26 is used, which, at the limit of one line of memory block 19, increments the counter 25 to the initial phase at the beginning of each line of the television raster. For this at the end

50 of the last television line forming the boundary of the correction section over the frame, the decoder 27 forms a pulse located in a lower-case damping pulse, which is rewritten. Now in the cells of the block 24, pa- 55 the state of the counter 25 in the register

The data can be written as logical zeros as well as ones depending on the input signal of the comparator 18. Since the analog-to-digital converter 14, together with the register 15 and the digital subtractor 16, calculates the first difference of the integral quality criterion on the elementary raster region specified by the coordinate by block 17, and the magnitude of this difference is proportional to the distortions in this area, the level of the logical unit at the output

O of comparator 18 indicates that the specified distortion of the video signal in the raster section is exceeded, which indicates - with the counters of the coordinate block 17. Therefore, the level of logical units in

The 5 cells of the memory block 19 record those areas, the correction of which is necessary. Thus, the unit recorded in the memory cell indicates the need for correction, and the address

0 of this cell is about the coordinate of the area to be corrected on the television raster. Across the field, the entire raster is scanned, and the necessary memory cells are filled with units.

5 The third mode of operation begins - reading the information recorded in the memory of block 19 in real time synchronously with the TV scan. Each section of the raster subject to correction must be allocated a section of memory in the block of 20 registers In which is the correction code. In addition, this code should appear synchronously with the scan 5 of the image in the required location. For addressing plots in block 20

25 Begins the third mode of operation - reading the information recorded in the memory of block 19 in real time synchronously with the TV scan. Each section of the raster subject to correction needs to be allocated a section of memory in the block of 20 registers In which is the correction code. In addition, this code should appear synchronously with the scan 5 of the image in the required location. For addressing plots in block 20

the registers use a counter 25, which counts the number of units recorded in memory block 19. But one

The 40th row of the memory block 19 is scanned as many times as the image lines form the correction portion of the frame. In order to eliminate the extra counting with repeats, a register 26 is used, which, within the limits of one line of memory block 19, increments the counter 25 to the initial phase at the beginning of each line of the television raster. For this at the end

0, of the last television line forming the boundary of the correction section over the frame, the decoder 27 forms a pulse located in the horizontal damping pulse, which is rewritten 26. The decoder of the 27 end of the line also forms a second pulse, somewhat delayed relative to the first, but located in each dim line.

A pulse that rewrites the state of register 26 into counter 25. At the end of the television field, decoder 28 generates a pulse that resets register 26. Register register 20, through digital switch 29, perceives the state of counter 25 located in memory block 19 as the address memory cells, which is read. Moreover, reading occurs in parallel from several memory blocks united by address inputs. Memory block 24 forms eight memory cells that allow reading byte by byte. The number of blocks is determined by the number of television signal parameters that need to be corrected. Each cell can contain one byte of information. The parallelized digital stream is fed to the first input of the gating unit 21, to the control input of which a logical signal is sent that determines the need for correction at a given time. In the digital-to-analog converter 23, the digital control signals are converted to analog, and from the output of the digital-to-analog converter 23 are fed to the correction input of the sensor 1, each acting on its own parameter. The set of corrective signals is as follows.

After filling the memory block 19 with the Information about the areas to be corrected, the processor 7 is turned on to execute the Correcting P program. According to this program, the first processor 7 disconnects the memory block 19 from the address system of the register unit 20 and sets the address of the first cell memory After that, the data bus is produced at the first address in one of the memory blocks 19 / for writing the first test action code. Similarly to the described occur, its evaluation by the integral criterion

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quality, the minimization program is executed, then the processor 7 determines the optimal code of the second parameter pe-. beating, etc. for all parameters Next, the address is incremented by one and the search for optimal control codes for another correction area, etc., is carried out until a correction signal is found for all

W plots recorded in block 19 of memory.

Claims (1)

Invention Formula 15 A signal shaping device for correcting the distortion of a television image according to avt.S. No. 1109945, characterized in that, for the purpose of correction accuracy 20 distortions; an analog-digital converter, a memory register, a digital subtraction unit, a comparator, an address memory block, a register block are entered into it. 25 memory, a gating unit and a digital-to-analog converter, the output of which is connected to the correcting input of the video signal sensor, the coordinate unit, the counting input of which 30 is connected to the sync sensor of the video signal sensor, and the address output is connected to the second input of the address memory unit, and the threshold setting unit, the output of which is connected to the second comparator input, the synchronous output of the coordinate block is connected to the analogue digital converter synchronous inputs and memory register, the integrator output connected to the input of an analogue-digital conversion body, the output of which is connected to the second input of the digital subtraction unit, the information and control outputs of the processor are connected respectively to the information and control m vhoda45 E register block memory and the second output block of the memory addresses is coupled to control input gating unit. ffmo / au / xff / ff / 7e / uomi wb / xff /  fff Editor E „Kopcha Compiler H, Clean Cove Tehred V. Kadar Proofreader G. Reshetnik Order 2437/56 Circulation 638. Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 m., - .- - ".-; - -...-. 1-. - .- .- .. - --- i-- ---- - - - - Production and Printing Enterprise, Uzhgorod, ul. Project, 4 , ff My / 7e / e A / T 3B: b-0-a  fff fpcie.2