JPH0524714B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an input signal processing circuit for a digital recording type electronic still camera.

(Background of the Invention) After the video signal output from the solid-state image sensor is AD converted for one screen, it is stored digitally in a digital memory such as a semiconductor memory, or via it is converted into a magnetic memory with a larger capacity. 2. Description of the Related Art Electronic still cameras that record on tape, magnetic bubbles, and the like are well known.

For such electronic cameras, for example, U.S. Patent No.
As shown in No. 4,131,919, AD-converted data is once held in a latch circuit for a predetermined period of time, and written into a digital memory while being held.

FIG. 1 shows an example of such a conventional digital recording electronic still camera. 1st
In the figure, 1 is an imaging lens, 2 is an aperture, 3 is a half mirror or quick return mirror for guiding a light beam to a finder, 4 is an optical low-pass filter, and 5 is an image pickup device, for example, a CCD.
Although FIG. 1 shows the shutter function obtained by driving the image sensor 5, a separate shutter device may of course be provided. In this case, for example, a mechanical shutter such as a lens shutter or a focal plane shutter, or an electro-optical element such as an electrochromic or liquid crystal device may be used. The CCD 5 outputs a video signal when receiving drive pulses in a certain sequence from the CCD drive circuit 6. The amplifier 7 includes a preamplifier, a process amplifier, or a color signal separation circuit when capturing color images.

The video signal output from the amplifier 7 is quantized by a sample and bold 8 and an A/D converter 9, held in a latch 10, and then written into a digital memory 11. Delay circuits 12 and 13 take into account the delay time from sampling and holding to A/D conversion and latching. If a fully parallel A/D converter called a flash A/D converter is used, sample-and-hold is not necessary.

The digital memory 11 is usually a digital frame memory having a memory capacity for one screen. To store a plurality of sheets, a recording device 14 using a larger capacity storage medium such as a magnetic bubble, a digital magnetic disk, or a digital cathode tape is used. Reference numeral 15 indicates a relay switch during still photography, and when this switch is connected, the flip-flop 16 is set and the timing control circuit 17 starts the photography sequence. When the timing control circuit 17 starts
After the CCD drive circuit 6 operates and accumulates the required signal charge in the CCD 5, one screen of video signals is taken out from the CCD 5.

This video signal is immediately A/D converted at regular sampling intervals and stored in the digital memory 11.

The image data stored in the digital memory 11 is mainly transferred to the mass memory 14. Between the two memories 11 and 14, a data compression means such as a DPCM encoder or a code error detection/correction code addition circuit may be provided.

When these sequences are completed, the timing control circuit 17 outputs a reset pulse to the flip-flop 16, and the photographing is completed. During continuous shooting, if you hold down the release switch, the flip-flop 16 will take priority over setting.
A similar sequence can be repeated again.
It is also possible to start accumulating signal electricity in a new image sensor before the recording sequence is completely completed, thereby increasing the continuous shooting speed. The drawbacks of such a digital recording type electronic camera will be explained using FIG. 2. The video signal output from the imaging system is superimposed on two main types: random noise and fixed pattern noise. Random noise is, for example, preamplifier noise, and fixed pattern noise is switching noise or in-plane inclination of the dark current of a CCD. Fixed pattern noise can in principle be eliminated if the cause and manner of its occurrence are clarified. However, it is difficult to remove random noise. Also, the normal video signal
When considering the signal-to-noise ratio, a method is adopted in which the peak-to-peak value is used for signals, and the root mean square (RMS) value is used for noise. However, this is true when the noise is random and signal charges are accumulated repeatedly, as in a video camera, and a visual smoothing effect can be expected, but when signal charges are accumulated only once, as in a digital recording type electronic camera, this is true. This cannot be adopted in a system that can only read data. Here, the solid line in FIG. 2a shows a case where random noise is superimposed on a slowly changing video signal (indicated by a broken line). (b) is a sample-and-hold sampling pulse, and the voltage at the time of its fall is held and A/D converted. In (c), the dotted line indicates the desired value of the video signal, and the black dots indicate sample values affected by actual noise, and the black dots are stored.

Once random noise has been fixed and stored in this way, it has been difficult to remove it. Of course, this noise can be suppressed to some extent on the screen by performing digital smoothing processing after it is stored in the memory 11, but this will lead to a deterioration of the resolution, and this is not a method that provides a satisfactory effect. I couldn't say yes.

(Object of the Invention) The present invention solves these drawbacks, improves the SN ratio without increasing the storage capacity of the digital memory, and provides a digital recording electronic still camera that can obtain still images of good image quality. The purpose is to

(Summary of the Invention) In the digital recording electronic still camera of the present invention, unlike conventional methods, multiple pieces of sampling data are used and calculations such as averaging are performed on the data to obtain one pixel data in the memory. The technical point is to improve the signal-to-noise ratio and then store it in digital memory.

(Example) FIG. 3 shows a first example of the simplest configuration of the present invention, and the optical system is omitted for simplicity. In FIG. 3, 21 is a CCD, 22 is a CCD drive circuit, 23 is an amplifier, 24 is a sample and hold circuit, 25 is an A/D converter, 26 is a latch, 27 and 28 are delay circuits, 29 is a relay switch, and 30 31 is a flip-flop; 31 is a timing control circuit;
9, 10, 11, 12, 13, 15, and 17. Further, 32 is a digital memory, and the first
This corresponds to 11 in the figure. Note that the large capacity memory 14 and optical systems 1 to 4 corresponding to FIG. 1 are omitted in FIG. 3. Also, the large-capacity memory and optical system are omitted in FIGS. 4 and 6 as well.

The basic difference between Figures 1 and 3 is that when the clock frequency of the latch immediately before being stored in the digital memory is fs, the sampling frequency in Figure 1 was also fs; In No. 3, when the clock of latch 33 corresponding to No. 10 is fs, twice the frequency 2fs is used as the sampling frequency.

In addition, in FIG. 3, the latch 34 is connected to the latch 26 so that data of two successive sample points can be obtained simultaneously, and their average value is sent to the average value circuit 35.
and sends it to the input latch 33 of the memory 32. The 1/2 frequency divider 36 is for determining fs from 2fs, and is, for example, a toggle flip-flop. As a result, digital memory 3
1 data stored in 2 is the average value of data obtained by sampling twice. Therefore,
If the conditions are good, the noise will be 1/√2 of the input video signal.
improved to a certain degree.

FIG. 4 shows a second embodiment of the invention. Components in FIG. 4 that have exactly the same or almost the same functions as those in FIG. 3 are given common numbers.

Figure 4 is a more generalized version of Figure 3, and the sampling clock frequency in Figure 3 is 2fs,
A two-stage shift register with latches 26 and 34,
In FIG. 4, the average value circuit 35 and 1/2 frequency divider 36 are respectively replaced by digital filters 40 and 1/2 consisting of N·Fs, M-stage shift register 41 and average value circuit 42.
It can be obtained by replacing it with the N frequency divider circuit 44.

As a result of this configuration, one pixel in the digital memory 32 is obtained by digitally performing a filtering operation on M sample points centered on the N sample points.

FIG. 5 shows an example of a nonlinear digital filter that can be used in the second embodiment, and has a pipeline configuration. Here M=4, N=
It is 2. In FIG. 5, approximately 8 bits of data output from the A/D converter is input to a shift register circuit 51 consisting of four stages of latches.
Sample point data is output in parallel. 52 is an edge detection section, which detects 3 points in a range of 4 sample points.
Differences are found between adjacent pixels on the street, and whether they are greater or less than a constant value T is determined, and if even one is greater than T, a logic 1 is given as an output. 53 is an average value circuit, which calculates the average value in two ranges,
This circuit selects and outputs one of them, and calculates the average value of the entire output of the four stages of shift registers and the average value of the two central stages.If logic 1 is given to the output of the edge detector 52, When it is determined that the average value of the two stages is selected and output, the logic
When is given, there are no edges, so the average value over all four stages is output. Therefore, the average is taken over a narrow range in edge areas and over a wide range in flat areas, an effect consistent with the nature of visual perception, that is, noise in edge areas is not very noticeable, but is noticeable in flat areas. This makes it possible to suppress noise. In FIG. 5, 54, 55, 56 are subtracters for calculating the difference between adjacent pixels; 57, 58,
59 is an adder for average calculation, 60, 61, 6
2 is a digital comparator, 63 is an OR gate that outputs logic 1 when one of these outputs becomes logic 1, and 64 and 65 are symbols indicating that binary division by simple bit shifting is performed. Further, 66 is a selector, which is used to select one of two average values. 67-7
The latch and flip-flop 74 at No. 3 is a synchronous storage means for performing operations over multiple clock cycles, ie, pipeline processing. Here, we have shown a one-dimensional digital filter in the horizontal direction, but it is of course easy to extend this to two dimensions.For example, it is widely known as a local parallel processing technique by cutting out a window region using multiple 1H digital delay lines. As such, it will not be explained in detail here.

In the above embodiments, explanations have mainly been made regarding monochrome images, that is, images of one channel. If this is to be applied to color, it is sufficient to simply connect two or three channels of this circuit after the A/D converter. FIG. 6 shows an example in which the present invention is applied to a solid-state image pickup device having a single-plate color filter with sequential green checkered, red, and blue lines and a color filter with sequential white checkered, cyan, and yellow lines as shown in FIGS. 7a and 7b. For example, when looking at each scanning line in FIG. 7A, a green signal appears on every line, a red (blue) signal appears on every other line, and color signals are alternately output on every other pixel.

The operation of the circuit shown in FIG. 6 will be explained below using the timing chart shown in FIG.

In FIG. 6, 80 is a single-plate color CCD image pickup device, 81 is its drive circuit, 82 is an amplifier, 83 is a sample-and-hold circuit, 84 is an A/D converter, and 85 and 86 are delay circuits used for timing adjustment. . 98 is a relay switch, 99 is a flip-flop, and 100 is a timing control circuit. In this embodiment, the sampling clock frequency for A/D conversion is 4 fs. This is shown in Figure 8a. The output clock of the delay circuit 86 is divided by two AND gates 87, 88 and an inverter 89 into a clock as shown in FIGS. The gate signal for this purpose has a frequency fs/2 as shown in Figure 8b.
A clock is used, which is a 1/8 frequency divider circuit 92.
This is the output of The color imaging signal that is the output of the amplifier 82 is given the output of one filter color every half period of fs/2 as shown in Fig. 8c, and in the figure, a line with green G and red R filters is given. The scanned output is shown. As a result, in this line scanning, green signal data is always input to the shift register 90, and red signal data is always input to the shift register 91. These data are processed in groups of four by average value circuits 93 and 94, respectively, and the processing results are temporarily stored in latches 95 and 96 and written into digital memory 97.

The process is exactly the same for the next line scan with green and blue filters.

As a result of the above, color signals corresponding to the color filter arrangement are written in the digital memory 97 with a good S/N ratio, so when playing back, the RGB three primary color signals necessary for display, or the luminance,
All you have to do is synthesize the color difference signals and create an NTSC signal.

In this example, one color filter corresponds to four sample points, but the present invention is not limited to this, and may be implemented using more sample points between adjacent pixels of the same color. It goes without saying that it is possible.

(Effects of the Invention) As described above, according to the present invention, when a video signal containing noise obtained from an image sensor is A/D converted and stored in a digital memory, the stored data is processed to eliminate noise. Rather than removing the noise, the noise is removed after sampling the input signal multiple times per unit pixel data of the digital memory and performing A/D conversion, and then storing it, which reduces noise without increasing the storage capacity. This has the advantage that it is possible to obtain good image quality. Furthermore, when processing the data sampled multiple times to remove noise, it is possible to use not only simple average value processing but also nonlinear filtering processing, as shown in FIG. 5, for example. Therefore, it is possible to improve the signal-to-noise ratio by a large amount without deteriorating the resolution.

In addition, the number of analog signals that is an integral multiple of 2 or more of the number of digital signals stored in the storage means is sampled, and the image signals obtained by the sampling are averaged, that is, the image signal used for averaging. Because it only takes one time to capture the image and read out the image signal from the image sensor array, it is possible to improve the S/N ratio not only for stationary subjects but also for moving subjects without losing the original information. I can,
Moreover, the time required to read out the image signal can be shortened.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of a conventional digital recording electronic still camera, Fig. 2 is a conceptual diagram showing the disadvantages thereof, Fig. 3 is an embodiment of the present invention, and Fig. 4 is a more general version of the present invention. FIG. 5 is a block diagram showing the circuit configuration of a nonlinear digital filter used in the embodiment of FIG. 4, FIG. 6 is an embodiment in which the present invention is applied to color imaging, and FIG. FIG. 6 is an example of color filter color arrangement used in the image sensor, and FIG. 8 is a timing chart for explaining the operation of FIG. 6. (Explanation of symbols of main parts), 21, 80...
CCD, 24, 83...sample hold circuit,
25, 84...AD conversion circuit, 26, 33, 3
4,43,67,68,69,70,71,7
2, 73, 95, 96...Latch circuit, 35, 4
2, 53, 93, 94...average value circuit, 40...
Digital filter, 41, 51, 90, 91...
...shift register.

Claims (1)

[Scope of Claims] 1. A plurality of elements in the image sensor array, each of which outputs an image signal, and one element extending between the plurality of elements using the image signals output from the plurality of elements. An analog signal forming means for forming an analog image signal; a timing means for generating a sampling frequency for sampling the output of the analog signal forming means at a constant frequency; and converting the analog signal sampled by the timing means into a digital signal. Analog to convert to
A digital recording electronic still camera comprising digital conversion means and storage means for storing digital signals obtained from the analog-to-digital conversion means, wherein the timing means controls the number of digital signals stored in the storage means. The sampling frequency is determined such that a number of analog signals that are an integer multiple of 2 or more are sampled, and the camera further samples digital signals that are an integer multiple of 2 or more obtained by the analog-to-digital conversion means. 1. A digital recording electronic still camera, comprising processing means for respectively averaging a plurality of digital signals that are close to each other so as to reduce the number of digital signals to the number stored in the storage means.