JPS59221188A - Digital recording electronic still camera - Google Patents

Abstract

PURPOSE:To obtain a still picture of excellent picture quality and improved S/N ratio by using plural sampling data to obtain one picture element data of a memory and obtaining this data with operation such as averaging. CONSTITUTION:An image pickup signal obtained from a CCD21 is applied to a digital filter 40 via a sample-and-hold circuit 24 and an A/D converting circuit 25. A latch 34 is connected to a latch 26 to obtain data of two succeeding sampling points at the same time, its average value is obtained by an averaging circuit 35 and applied to an input latch 33 of a digital memory 32. As a result, one data stored in the digital memory 32 becomes an average value of the data obtained by two samplings and noise is improved to nearly 1/1.4 of an input video signal if the condition is good.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an input signal processing circuit for a digital recording type electronic still camera.

(Background of the Invention) After AD converting the t''L video signal output from the solid-state image sensor for one screen, it is digitally stored in a digital memory such as a semiconductor memory, or via it is stored in a larger capacity memory. Electronic still cameras that record on magnetic tape, magnetic bubbles, or the like are known.

For such an electronic camera, for example, US Pat. No. 4131
As shown in No. 919, AD-converted data is once held in a latch circuit for a predetermined period of time, and written into a digital memory while being held.

FIG. 1 shows an example of such a conventional digital recording electronic still camera. In Figure 1, (
1) is an imaging lens, (2) is a diaphragm, (3) is a half mirror or quick return mirror that guides the light beam to the finder, (4) is an optical low-pass filter, and (5)
is an image sensor, for example a COD. Although FIGS. 1A and 1B show the shutter function obtained by driving the image sensor (5), a separate shutter device may of course be provided. In this case, for example, a mechanical shutter such as a lens shutter or a focal plane shutter, or an electro-optical element such as an electrochromic liquid crystal may be used.

The CCD 4 outputs a center image signal when receiving drive pulses in a certain sequence from the CCI drive circuit (6). The amplifier (7) includes a preamplifier, a process amplifier, or a color signal separation circuit for color imaging.

The video signal output from the amplifier (7) is quantized by a sample and hold (8) and a converter (9), held in a latch (10), and then stored in a digital memory (1).
1). (12) and (13) are delay circuits that take into account the delay time from sampling and holding to A//D conversion and latching. When using a fully parallel single converter called a Komude Furano Seal Phrase converter, sample-and-hold is not necessary.

As the digital memo 11), a digital frame memory having a memory capacity equivalent to one screen is usually used. To store a plurality of sheets, a recording device (14) using a larger capacity storage medium such as a magnetic bubble, a digital magnetic disk, or a digital cassette tape is used. (1
5) shows the release switch when shooting stills,
By connecting this switch, the flip-flop (16) is set and the timing control circuit (17) starts the photographing sequence.

When the timing control circuit (17) starts, the CCD
After the drive circuit (6) operates and the required signal charge is accumulated in the COD (5), a video signal for one screen is taken out from the CC, D (5).

This video signal is immediately processed at a fixed sampling interval.
It is converted and stored in the digital memo') (11).

Digital memo! The image data stored in J(11) is mainly large-capacity memo! Transferred to J (14). Between the two memories (11) and (14), a data compression means such as a DPCM encoder or a code error detection/correction code addition circuit may be provided.

When these sequences are completed, the timing control circuit (17) outputs a reset pulse to the flip-flop (16), and imaging is completed. If you keep the release switch pressed during continuous shooting, the flip-flop (16)
The same sequence can be repeated again since it has set priority. It is also possible to start accumulating a new signal charge in a new image sensor before the recording sequence is completely completed, thereby increasing the continuous shooting speed. The drawbacks of such a digital recording type electronic camera will be explained using FIG. 2.

The video signal output from the imaging system is superimposed on two main types: random noise and fixed pattern noise. Random noise is, for example, preamplifier noise, and fixed pattern noise is switching noise, in-plane nonuniformity of dark current, etc.

Fixed pattern noise can in principle be eliminated if the cause and manner of its occurrence are clarified. However, it is difficult to remove random noise.

Also, a method using the SN ratio of the normal video signal is adopted. However, this is true when the noise is random and signal charges are accumulated repeatedly, as in a video camera, and a visual smoothing effect can be expected, but when signal charges are accumulated only once, as in a digital recording electronic camera, this is true. A system that can only read data cannot be used at all. Here, the solid line in FIG. 2(a) shows the case where M random noises are added to a gradually changing video signal (indicated by a broken line). (b) is a sampling pulse of sample-and-hold, and the voltage at the fall of the pulse is held and A/D converted. In (C), the dashed line indicates the value of the desired video signal, and the black dots indicate sample values affected by actual noise, and the black dots are stored.

Once random noise has been fixed and stored in this way, it has been difficult to remove it. Memo of course! It is possible to suppress this noise on the screen to some extent by digitally smoothing or other processing after it is stored in (11), but this leads to a deterioration of the resolution, and there is no method that can achieve a satisfactory effect. Tohait, A
won.

(Objective of the Invention) The present invention solves these drawbacks, improves the S/N ratio without increasing the storage capacity of the digital memory, and provides digital recording τ that allows still images of good quality to be obtained.
The purpose is to obtain an L child still camera.

(Summary of the Invention) In the digital recording electronic still camera of the present invention, unlike conventional methods, multiple pieces of sampling data are used and calculations such as averaging are performed on the data to obtain one pixel data in the memory. Improve the SN ratio1. The technical weakness is to store the data in digital memory.

(Example) FIG. 3 shows a first example of the simplest configuration of the present invention, and the optical system is omitted for simplicity. In Figure 3, (21) is a COD, (22) is a COD drive circuit,
(23> is an amplifier, (24) is a sample and hold circuit, (25) is a 1~/D converter, (26) is a latch,
(27) and (28) are delay circuits, (29) is a V-lead switch, (30) is a flip-flop, and (31) is a timing control circuit, respectively (5), (6) in FIG.
(7), (8), (9), (10), (12), (13
), (15), and (17). Further, (32) is a digital memory, which corresponds to (11) in FIG. However, the large-capacity memo bar 14) and optical systems (1) to (4) corresponding to FIG. 1 are omitted in FIG. Also, in FIGS. 4 and 6, the large-capacity memory and optical system are omitted.

The basic difference between Figures 1 and 3 is that the clock frequency of the launch immediately before being stored in the digital memory is fs.
When starting, the sampling frequency was also fs in Fig. 1, whereas in Fig. 3 the latch (10) corresponding to
The point is that when the clock of 33) is fs, twice the frequency 2fs is used as the sampling frequency.

In addition, in FIG. 3, the latch (34) is connected to the latch (26) so that data of two successive sample points can be obtained simultaneously, and their average value is determined by the average value circuit (35). 32) to the input latch (33). The 1/2 frequency divider (36) is for determining 2fsj and fs, and is specifically a toggle flip-flop, for example. As a result, the J data stored in the digital memory (32) becomes the average value of the data obtained by sampling twice. Therefore, if the conditions are good, the noise can be improved to about 1/β of the input video signal.

FIG. 4 shows a second embodiment of the invention.

Components in FIG. 4 that have exactly the same or almost the same functions as those in FIG. 3 are given common numbers.

FIG. 4 is a more generalized version of FIG. 3, and the sampling clock frequency in FIG. 3 is 2 fs.

A two-stage shift register with latches (26) and (34), an average value circuit (35), and a 1/2 frequency divider circuit (36) are shown in Figure 4, respectively. fs, M-stage shift register (41), and average value A digital filter (40) consisting of a circuit (42)
) can be obtained by replacing it with a 1-bar frequency divider circuit (44).

As a result of this configuration, Digital Memo 17 (3
One pixel in 2) is obtained by digitally performing a filtering operation on M sample points centered on the N sample points.

FIG. 5 shows an example of a nonlinear digital filter that can be used in the second embodiment, and has a pipeline configuration. Here h4. =4, N=2.

In Figure 5, the 8bi output from the A/I) converter
Data of about t is input to a shift register circuit (51) consisting of four stages of latches, and data of four sample points are simultaneously output in parallel. (52) is an edge detection section,
Differences are found between three types of adjacent pixels within the range of four sample points, and whether they are larger or smaller than a constant value T is determined, and if even one is thicker than T, logic 1 is given as an output. (53
) is an average value circuit that calculates the average value in two ranges and selects and outputs one of them. If a logic 1 is given to the output of the edge detection section (52), it is determined that it is an edge part, and the average value of the two stages at t''LL is selected and output, and a logic 0 is given. Since there are no edges at the time, the average value for the entire four stages is output.Therefore, the average value is calculated over a narrow range for the edge part and a wide range for the flat part. This makes it possible to effectively suppress the noise, which is consistent with the fact that the noise in the area is not so noticeable, but is noticeable in flat areas.In Figure 5, (54), (55), and (56) are adjacent Subtractor that calculates the difference between pixels, (57), (58)
, (59) is a useless adder for average calculation, (60), (6
1) and (62) are digital comparators, (63) is an OR gate that outputs logic 1 when one of these outputs becomes logic 1, and (64) and (65) are binary comparators by simple bit shifting. This symbol indicates that division is being performed. Further, (66) is a selector, which is used to select one of the two average values. (67) ~ (73
The launch and flip-flop (74) of ) is a synchronous storage means for performing the operation q in multiple clock cycles, ie, for pipeline processing. Here, we have shown a one-dimensional digital filter in the horizontal direction, but
Of course, this can be easily extended to two dimensions, and is widely known as a local parallel processing technique by cutting out a window region using a plurality of 1H digital delay lines, for example, so it will not be described in detail here.

In the embodiments described above, monochrome images, that is, 1-channel images, have been mainly described. If you want to apply this to color, you can simply connect this circuit for 2 or 3 channels after the A/]) converter. FIG. 6 shows that the present invention is applied to a solid-state image pickup device having a single-plate color filter with green checkered, red, and blue lines sequentially as shown in FIGS. This is an example of application. For example, when looking at each scanning line in FIG. 7(a), a green signal is outputted every line, a red (blue) signal is outputted every other line, and color signals are alternately outputted every other pixel.

The operation of the circuit shown in FIG. 6 will be explained below using the timing chart shown in FIG.

In FIG. 6, (80) is a single-plate color CCD image sensor;
(81) is the drive circuit, (82) is the amplifier, (83)
is a sample and hold circuit, (84) is an A/D converter, and (85) and (86) are delay circuits used for timing adjustment.

Then, the sample clock frequency of A/D conversion is 4f.
Let s be 90, which is shown in Figure 8(a). Delay circuit (86
) output Chronoku Gen, two AND gates (87), (
Shift register (9o) with inverter (88) and inverter (89)
, (91) as shown in FIG. 8(d) and (e). As the gate signal for this purpose, a clock having a frequency fs shown in FIG. 8(b) is used, and this is the output of the 1/4 frequency divider circuit (92). As shown in Figure 8 (C), the color video signal that is the output of the amplifier (82) is given one color output to one filter every half cycle of fs, and in the figure, green O) and red (I ( ) shows the scanning output of a line with a filter.As a result, in this line scanning, the shift register (9
o) always has green signal data, shift register (9J)
Red light data is always input. These data are 1. = average value circuit (93), (94) respectively
The processing results are temporarily stored in latches (95) and (96) and written to digital memory (97).

The process is exactly the same for the next line scan with green and blue filters.

As a result of the above, the color signals corresponding to the color filter arrangement IV are written in the Digicle Memo IJ (97) with a good signal-to-noise ratio, so when playing back, the three primary color signals necessary for display are RGB, luminance, and color difference. It is sufficient to combine the signals to create the N'l'SC signal.

In this example, four sample points are associated with one color filter, but the present invention is not limited to this, and more sample points are used between adjacent pixels of the same color.
Needless to say, it is possible to implement it.

(Effects of the Invention) As described above, according to the present invention, when a video signal including noise generated by an image sensor is A//D converted and stored in a titanium/tal memory, the stored take is processed. Rather than removing noise by decoding, the noise is removed after sampling the hexagonal signal multiple times and A7D conversion, which is similar to the unit pixel data in digital memory, and then storing it.
It has the advantage that good image quality with less noise can be obtained without increasing storage capacity. Furthermore, when processing the data sampled multiple times to remove noise, it is possible to use not only simple average value processing but also nonlinear filtering processing, as shown in Figure 5, which reduces resolution deterioration. It is possible to improve the signal-to-noise ratio by a large amount without causing any problems.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional digital recording electronic still camera, Figure 2 is a conceptual diagram showing the inconveniences, and Figure 3 is a diagram showing the configuration of a conventional digital recording electronic still camera.
The figure shows one embodiment of the present invention, FIG. 4 shows a more general embodiment of the present invention, FIG. 5 is a block diagram showing the circuit configuration of a nonlinear digital filter used in the embodiment of FIG. 4, and FIG. The figure shows an example of applying the present invention to color imaging, FIG. 7 is an example of color arrangement of color filters used in the image sensor of FIG. 6, and FIG. 8 is a timing chart for explaining the operation of FIG. 6. It is. (Explanation of symbols of main parts) 21. 80...CCD 24, 83...Sample hold circuit 25, 84
. . . AD conversion circuit 35, 42.53.93.94 . . . Average value circuit 40 . . . Digital filter 4.1. , 51.90.91...Shift register applicant Takashi Watanabe, agent of Nippon Kogaku Kogyo Co., Ltd.

Claims (1)

[Claims] An image sensor, a sample hold means for sampling and holding at a frequency that is an integral multiple of 2 or more of the sampling frequency to obtain a fixed number of sample image signals from the image signal from the image sensor, and an analog signal from the sample hold means. an analog-to-digital converter for digitally converting a sample image signal output; a digital filter for processing the digital sample image signal output from the analog-to-digital converter to obtain the predetermined number of digital sample image signals; 1. A digital recording electronic still camera, comprising: storage means for storing digital sample image signals from a filter and having a storage capacity corresponding to the predetermined number of sample image signals.