FR2487124B1 - Procede de fabrication de plusieurs composants sur un seul corps semi-conducteur et objets manufactures formes par sa mise en oeuvre - Google Patents
Procede de fabrication de plusieurs composants sur un seul corps semi-conducteur et objets manufactures formes par sa mise en oeuvreInfo
- Publication number
- FR2487124B1 FR2487124B1 FR8114108A FR8114108A FR2487124B1 FR 2487124 B1 FR2487124 B1 FR 2487124B1 FR 8114108 A FR8114108 A FR 8114108A FR 8114108 A FR8114108 A FR 8114108A FR 2487124 B1 FR2487124 B1 FR 2487124B1
- Authority
- FR
- France
- Prior art keywords
- semiconductor body
- multiple components
- single semiconductor
- objects formed
- manufacturing multiple
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
- Local Oxidation Of Silicon (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17090780A | 1980-07-21 | 1980-07-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2487124A1 FR2487124A1 (fr) | 1982-01-22 |
FR2487124B1 true FR2487124B1 (fr) | 1986-01-10 |
Family
ID=22621766
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR8114108A Expired FR2487124B1 (fr) | 1980-07-21 | 1981-07-20 | Procede de fabrication de plusieurs composants sur un seul corps semi-conducteur et objets manufactures formes par sa mise en oeuvre |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS5787152A (fr) |
DE (1) | DE3128621A1 (fr) |
FR (1) | FR2487124B1 (fr) |
GB (1) | GB2081506B (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5943545A (ja) * | 1982-09-06 | 1984-03-10 | Hitachi Ltd | 半導体集積回路装置 |
JPH073858B2 (ja) * | 1984-04-11 | 1995-01-18 | 株式会社日立製作所 | 半導体装置の製造方法 |
US4541168A (en) * | 1984-10-29 | 1985-09-17 | International Business Machines Corporation | Method for making metal contact studs between first level metal and regions of a semiconductor device compatible with polyimide-filled deep trench isolation schemes |
JPH10256394A (ja) | 1997-03-12 | 1998-09-25 | Internatl Business Mach Corp <Ibm> | 半導体構造体およびデバイス |
WO2001048814A1 (fr) * | 1999-12-24 | 2001-07-05 | Koninklijke Philips Electronics N.V. | Procede de fabrication d'un dispositif a semi-conducteurs comprenant des elements de semi-conducteur formes sur une couche superieure d'une tranche de silicium situee sur une couche d'isolation enterree |
US8809942B2 (en) * | 2011-09-21 | 2014-08-19 | Kabushiki Kaisha Toshiba | Semiconductor device having trench structure |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51139281A (en) * | 1975-05-28 | 1976-12-01 | Hitachi Ltd | Semi-conductor device |
JPS5423388A (en) * | 1977-07-22 | 1979-02-21 | Hitachi Ltd | Semiconductor integrated-circuit device and its manufacture |
-
1981
- 1981-07-16 GB GB8121900A patent/GB2081506B/en not_active Expired
- 1981-07-20 JP JP56113419A patent/JPS5787152A/ja active Pending
- 1981-07-20 FR FR8114108A patent/FR2487124B1/fr not_active Expired
- 1981-07-20 DE DE19813128621 patent/DE3128621A1/de not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
GB2081506A (en) | 1982-02-17 |
FR2487124A1 (fr) | 1982-01-22 |
JPS5787152A (en) | 1982-05-31 |
DE3128621A1 (de) | 1982-05-06 |
GB2081506B (en) | 1984-06-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |