GB2081506A - Resin-filled groove isolation of integrated circuit elements in a semi-conductor body - Google Patents

Resin-filled groove isolation of integrated circuit elements in a semi-conductor body Download PDF

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Publication number
GB2081506A
GB2081506A GB8121900A GB8121900A GB2081506A GB 2081506 A GB2081506 A GB 2081506A GB 8121900 A GB8121900 A GB 8121900A GB 8121900 A GB8121900 A GB 8121900A GB 2081506 A GB2081506 A GB 2081506A
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GB
United Kingdom
Prior art keywords
semi
integrated circuit
circuit elements
conductor
conductor body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8121900A
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GB2081506B (en
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EMC Corp
Original Assignee
Data General Corp
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Filing date
Publication date
Application filed by Data General Corp filed Critical Data General Corp
Publication of GB2081506A publication Critical patent/GB2081506A/en
Application granted granted Critical
Publication of GB2081506B publication Critical patent/GB2081506B/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)

Abstract

Integrated circuit elements e.g. transistors, in a semi-conductor body are electrically insulated from one another by etching a groove 8 into the semi-conductor body between said elements and back-filling the groove with an insulative resin so as to present a substantially smooth supporting surface on said semi-conductor body for application of conductive material forming electrical connections 15 between said elements. Preferably the resin provides a uniform layer 11 over the surface of the semi-conductor body and, before the resin is applied, an oxide layer 2 is formed over the walls of the groove. <IMAGE>

Description

SPECIFICATION Back-filled oxide isolation of integrated circuit elements on a semi-conductor body This invention relates to a method for manufacturing integrated circuit semiconductor products.
In the past, it has been common practice to fabricate a number of electrically active semiconductor elements on a single monocrystalline wafer of silicon or other semi-conductor material. Once fabricated, it is necessary to insulate the individual wafer regions that perform the electrical functions of these elements and to further form electrical connections from and between various regions.
Perhaps the most common way of providing electrical isolation between integrated elements on a silicon chip is by isoplanar oxide isolation as disclosed in U.S.Patent No. 3 648 125. Well known photolithographic techniques are employed to establish grooves between the active elements which are substantially filled before the electrical connections are established. Unless the grooves are filled, the latter applied electrical connections are not presented with a smooth surface and those connections travelling into the unfilled grooves are greatly weakened.
It has been attempted to fill insulating grooves with silicon dioxide by growing the oxide directly upon the semiconductor body to a thickness which would substantially fill the groove area. However, the extremely high temperatures necessary in forming such a thick oxide layer were found to be detrimental to the active semi-conductor integrated circuit components causing them to migrate.
Other attempts at isolating active elements located on a single semi-conductor body have included doping nonactive areas forming back-biased diodes. This technique suffered from the disadvantages of leakage associated with diodes and capacitance associated with the junction. Also, to approach isolation, the doped area was made large by necessity, thus reducing the number of active elements which could be packed on a single semiconductor body.
It is an object of the present invention to electrically isolate semi-conductor integrated circuit elements located upon a single semiconductor body without the disadvantages outlined above.
It is another object of the present invention to form electrical connections to semi-conductor integrated circuit components located upon a single-conductor body simply and conveniently by providing a substantially smooth substrate for the electrical connections.
Accordingly, the invention provides a method of producing a plurality of semi-conductor integrated circuit elements on a single semi-conductor body comprising forming elec- trically functionary regions forming the semiconductor integrated circuit elements, etching grooves into said semi-conductor body to a depth to substantially electrically insulate said semi-conductor integrated circuit elements, filling said grooves with an electrically insulative resin and forming electrical connections to said functionary regions.
Hereafter the invention is further described by way of example and with reference to the accompanying drawings wherein: Figure 1 is a cross-sectional view of a semiconductor body having located therein adjacent active elements making up adjacent transistor structures; Figure 2 is a cross-sectional view of the elements shown in Fig. 1 having been electrically isolated by the cutting of a groove; Figure 3 is the device of Fig. 2 having an oxide layer grown thereon; Figure 4 is a cross-sectional view of the structure shown in Fig. 3 having the groove filled with a resin according to the present invention; Figure 5 is a cross-sectional view of the structure shown in Fig. 4 having openings cut from the resin and oxide layers; and Figure 6 shows the structure of Fig. 5 having an electrical connection bridging the filled groove according to the present invention.
The present invention is concerned with a method of producing a plurality of semi-conductor integrated circuit elements on a single semi-conductor body comprising forming elec- trically functionary regions within the semiconductor body and electrically insulating the various semi-conductor integrated circuit elements from one another by etching grooves into the semi-conductor body and filling the grooves with an electrically insulative resin.
The resin acts to form a substantially smooth surface allowing for the convenient formation of electrical connections over the grooves areas.
Turning to Fig. 1, adjacent transistor structures are shown within a single semi-conductor body made up of substrate 7, a P type diffusion region which lies beneath epitaxial layer 1, an N type region. At their interface, N + type regions 3, 3A act as collectors. Near the surface of region 1 are the remaining elements of the transistors comprising emitters 6, 6A comprising N + + type regions sur rounded by 5, 5A base or P type regions.
Adjacent to the aforesaid areas, regions 4, 4A represent N + type collectors. Overlying the entire structure is dun oxide layer 2 which acts as an insulative barrier formed substantially over the entire semi-conductor body.
Turning to Fig. 2, the first step in isolating the active components is to etch opening 8 defined by sidewalls 10 to a depth preferably below the epitaxial layer 7 shown at 9. This etching operation can be carried out by stan dard photoresist techniques notoriously well known in the art. The exact width and depth of groove 8 is not critical noting that it is merely intended to electrically insulate the active components from one another. It will be appreciated that a more complete insulation occurs when groove 8 is cut completely through epitaxial layer 1 as shown in the appended drawings. By way of illustration only, wafers approach 600cm while the epitaxial layer extends generally up to approximately 5#L.
As shown in Fig. 3, the next step in the process generally comprises the formation of oxide layer 2 over side walls 10 of groove 8.
It is the oxide layer which performs the primary function of insulating the active elements once groove 8 is filled. As stated previously, prior art techniques have included the buildup of an oxide layer to completely filled groove 8. This technique, although providing excellent electrical insulation, suffered from the necessity of high temperatures in forming any thick oxide structure. High temperature fabrication has caused migration of the variously doped regions which could cause serious damage to the active components. This oxide layer 2 of the present invention grown to approximately 5000 forms at several hundred degrees C and, thus, its formation does not contribute to migration.
The next step in the fabrication process is shown in Fig. 4 wherein groove 8 is completely filled with an insulative resin. Various resins were selected for use in the present invention, the only requirements being that each resin by usable at low temperatures (several hundred degrees C), be electrically insulating, be reasonably free of pin hole defects when cured, be of a proper viscosity to fill the rather small grooves and present a relatively smooth surface upon curing. Among the resins which possess the above-recited properties, the most preferable was found to be polyimide type thermosetting resins. The polyimide resins are well known in the art and have a chemical formula shown by:
wherein R, and R2 represent radicals of a tetravalent aromatic group and of a divalent aromatic group, respectively, and n is a positive integer.This polyimide resin is prepared by synthesizing an aromatic diamine and an aromatic acid dianhydride, and is usually formed by utilizing Pyre-ML (trade name of E.
I. du Pont de Nemours and Co.) or Torayniece (trade name of Toray Kabushikikaisha), for example. The polyimide resin including its process of manufacture is described in detail in U.S. Patent No. 3,179,634 assigned to E.
I. du Pont de Nemours and Co. and its use in semi-conductor devices is described in U.S.
Patent No. 3,700,497 assigned to RCA Corporation.
Fig. 4 and the remaining figures show the application of the insulating resin 11 not only within groove 4 but also as a coating over the entire semi-conductor body. It should also be pointed out, however, that the insulative resin need not be applied beyond groove 8 as long as the top surface of the resin 11 is substan- tially flush with the remaining wafer structure, in this case, as established by the surface of oxide layer 2.
The next steps in the fabrication process, i.e., the establishment of electrical connections, is shown in Figs. 5 and 6 wherein openings are first established in resin layer 11 and oxide layer 2 shown as openings 12 and 1 3 above collector 4 and base 5A. Openings in these layers can be made by standard photographic techniques although various methods for making openings through polyimide resins are described in U.S. Patent No.
3,700,497 and in U.S. Patent No.
3,395,057, the latter assigned to V. D.
Schjeldahl Co.
Once openings 12 and 13 are established, the formation of metal layer 15 can be made by any well known technique such as by sputtering metal through a mask or by applying a uniform conductive layer and selectively etching away unwanted areas. The specific configuration of conductive element 15 was made in Fig. 7 to depict how resin 11 can act as a bridge to present a smooth surface to an electrical connection over an insulating groove. Without the insulative resin, rather sophisticated techniques would have been required to insure adequate electrical integrity such as the need for beam lead metal techniques which are expensive and complicated to manufacture.

Claims (13)

1. A method of producing a plurality of semi-conductor integrated circuit elements O#v a single semiconductor body comprising forming electrically functionary regions forming the semi-conductor integrated circuit elements, etching grooves into said semi conduc tor body to a depth to substantially electrically insulate said semiconductor integrated circuit elements, filling said grooves with an electrically insulative resin and forming electrical connections to said functionary regions.
2. A method of electrically insulating semiconductor integrated circuit elements located upon a single semiconductor body comprising etching grooves into said semi conductor body between said semi-conductor integrated circuit elements to a depth to substantially electrically insulate said elements filling said grooves with an electrically insulative resin and forming electrical connections to said elements.
3. A method according to Claim 1 or Claim 2 wherein said insulative resin is a polyimide resin.
4. A method according to any of Claims 1 to 3 wherein a layer of silicon dioxide is formed between the semi-conductor body and insulative resin.
5. A method according to Claim 4 wherein the silicon dioxide and insulative resin are selectively removed from the semi-conductor body before forming the electrical connections.
6. A method according to any preceding Claim wherein the surface of the insulative resin is substantially smooth.
7. A method according to any preceding claim wherein said insulative resin is applied to not only fill the grooves but also to coat the surrounding surface of the semin-conductor body.
8. An article of manufacture comprising: a. a semi-conductor body; b. a plurality of integrated circuit elements located within the semi-conductor body; c. grooves located in the semi-conductor body between the integrated circuit elements formed to a depth to substantially electrically insulate the integrated circuit elements; d. an insulative resin which substantially fills said grooves; and e. electrical connections to functionary regions of the integrated circuit elements.
9. An article according to Claim 8 wherein said insulative resin is a polyimide resin.
10. An article according to Claim 8 or Claim 9 wherein a layer of silicon dioxide is located between the semi-conductor body and the insulative resin.
11. An article according to any of Claims 8 to 10 wherein the surface of the insulative resin is substantially smooth.
12. An article according to any of Claims 8 to 11 wherein the insulative resin not only substantially fills the grooves but also coats the surrounding surface of the semi-conductor body.
13. An article substantially as described herein with reference to Figs. 1 to 6.
1 4. A method of producing a plurality of semi-conductor integrated circuit elements in accordance with Claim 1 and substantially as described herein.
GB8121900A 1980-07-21 1981-07-16 Resin-filled groove isolation of integrated circuit elements in a semi-conductor body Expired GB2081506B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US17090780A 1980-07-21 1980-07-21

Publications (2)

Publication Number Publication Date
GB2081506A true GB2081506A (en) 1982-02-17
GB2081506B GB2081506B (en) 1984-06-06

Family

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GB8121900A Expired GB2081506B (en) 1980-07-21 1981-07-16 Resin-filled groove isolation of integrated circuit elements in a semi-conductor body

Country Status (4)

Country Link
JP (1) JPS5787152A (en)
DE (1) DE3128621A1 (en)
FR (1) FR2487124B1 (en)
GB (1) GB2081506B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0182998A1 (en) * 1984-10-29 1986-06-04 International Business Machines Corporation Method for making metal contact studs between first level metal and regions of a semiconductor device compatible with polyimide-filled deep trench isolation schemes
US4746963A (en) * 1982-09-06 1988-05-24 Hitachi, Ltd. Isolation regions formed by locos followed with groove etch and refill
US6228745B1 (en) 1997-03-12 2001-05-08 International Business Machines Corporation Selective reduction of sidewall slope on isolation edge
WO2001048814A1 (en) * 1999-12-24 2001-07-05 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device comprising semiconductor elements formed in a top layer of a silicon wafer situated on a buried insulating layer

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH073858B2 (en) * 1984-04-11 1995-01-18 株式会社日立製作所 Method for manufacturing semiconductor device
US8809942B2 (en) * 2011-09-21 2014-08-19 Kabushiki Kaisha Toshiba Semiconductor device having trench structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51139281A (en) * 1975-05-28 1976-12-01 Hitachi Ltd Semi-conductor device
JPS5423388A (en) * 1977-07-22 1979-02-21 Hitachi Ltd Semiconductor integrated-circuit device and its manufacture

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4746963A (en) * 1982-09-06 1988-05-24 Hitachi, Ltd. Isolation regions formed by locos followed with groove etch and refill
EP0182998A1 (en) * 1984-10-29 1986-06-04 International Business Machines Corporation Method for making metal contact studs between first level metal and regions of a semiconductor device compatible with polyimide-filled deep trench isolation schemes
US6228745B1 (en) 1997-03-12 2001-05-08 International Business Machines Corporation Selective reduction of sidewall slope on isolation edge
WO2001048814A1 (en) * 1999-12-24 2001-07-05 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device comprising semiconductor elements formed in a top layer of a silicon wafer situated on a buried insulating layer
US6562694B2 (en) 1999-12-24 2003-05-13 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device comprising semiconductor elements formed in a toplayer of a silicon wafer situated on a buried insulating layer
CN100382277C (en) * 1999-12-24 2008-04-16 Nxp有限公司 Method of manufacturing a semiconductor device comprising semiconductor elements formed in a top layer of a silicon wafer situated on a buried insulating layer

Also Published As

Publication number Publication date
JPS5787152A (en) 1982-05-31
FR2487124A1 (en) 1982-01-22
DE3128621A1 (en) 1982-05-06
GB2081506B (en) 1984-06-06
FR2487124B1 (en) 1986-01-10

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Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19940716