FR2458902B1 - - Google Patents

Info

Publication number
FR2458902B1
FR2458902B1 FR8012613A FR8012613A FR2458902B1 FR 2458902 B1 FR2458902 B1 FR 2458902B1 FR 8012613 A FR8012613 A FR 8012613A FR 8012613 A FR8012613 A FR 8012613A FR 2458902 B1 FR2458902 B1 FR 2458902B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8012613A
Other languages
French (fr)
Other versions
FR2458902A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of FR2458902A1 publication Critical patent/FR2458902A1/fr
Application granted granted Critical
Publication of FR2458902B1 publication Critical patent/FR2458902B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H10P30/204—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10P30/212—
    • H10P76/40—
FR8012613A 1979-06-13 1980-06-06 Procede pour fabriquer des circuits mos integres avec et sans transistors de memoire mnos selon la technologie des grilles en silicium Granted FR2458902A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2923995A DE2923995C2 (de) 1979-06-13 1979-06-13 Verfahren zum Herstellen von integrierten MOS-Schaltungen mit MOS-Transistoren und MNOS-Speichertransistoren in Silizium-Gate-Technologie

Publications (2)

Publication Number Publication Date
FR2458902A1 FR2458902A1 (fr) 1981-01-02
FR2458902B1 true FR2458902B1 (enExample) 1983-01-21

Family

ID=6073175

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8012613A Granted FR2458902A1 (fr) 1979-06-13 1980-06-06 Procede pour fabriquer des circuits mos integres avec et sans transistors de memoire mnos selon la technologie des grilles en silicium

Country Status (6)

Country Link
US (1) US4306353A (enExample)
JP (1) JPS562652A (enExample)
CA (1) CA1141868A (enExample)
DE (1) DE2923995C2 (enExample)
FR (1) FR2458902A1 (enExample)
GB (1) GB2053565B (enExample)

Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2506076A1 (fr) * 1981-05-12 1982-11-19 Efcis Procede de fabrication de circuits integres de type mos
US4423547A (en) * 1981-06-01 1984-01-03 International Business Machines Corporation Method for forming dense multilevel interconnection metallurgy for semiconductor devices
US4517729A (en) * 1981-07-27 1985-05-21 American Microsystems, Incorporated Method for fabricating MOS device with self-aligned contacts
US4534104A (en) * 1982-02-26 1985-08-13 Ncr Corporation Mixed dielectric process and nonvolatile memory device fabricated thereby
JPS5984572A (ja) * 1982-11-08 1984-05-16 Nec Corp 半導体装置
US4575240A (en) * 1983-06-10 1986-03-11 Corning Glass Works Visible sample chamber for fluid analysis
US4488348A (en) * 1983-06-15 1984-12-18 Hewlett-Packard Company Method for making a self-aligned vertically stacked gate MOS device
NL8303268A (nl) * 1983-09-23 1985-04-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting en halfgeleiderinrichting vervaardigd door toepassing van een dergelijke werkwijze.
JPH0448244U (enExample) * 1990-08-31 1992-04-23
US5644533A (en) * 1992-11-02 1997-07-01 Nvx Corporation Flash memory system, and methods of constructing and utilizing same
JPH08507411A (ja) * 1992-11-02 1996-08-06 エヌヴィエックス コーポレーション フラッシュ・メモリー・システムとその製造方法およびその利用
US6083852A (en) 1997-05-07 2000-07-04 Applied Materials, Inc. Method for applying films using reduced deposition rates
US6127262A (en) * 1996-06-28 2000-10-03 Applied Materials, Inc. Method and apparatus for depositing an etch stop layer
US6297096B1 (en) 1997-06-11 2001-10-02 Saifun Semiconductors Ltd. NROM fabrication method
US5966603A (en) * 1997-06-11 1999-10-12 Saifun Semiconductors Ltd. NROM fabrication method with a periphery portion
IL125604A (en) 1997-07-30 2004-03-28 Saifun Semiconductors Ltd Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6430077B1 (en) 1997-12-12 2002-08-06 Saifun Semiconductors Ltd. Method for regulating read voltage level at the drain of a cell in a symmetric array
US6633499B1 (en) 1997-12-12 2003-10-14 Saifun Semiconductors Ltd. Method for reducing voltage drops in symmetric array architectures
US6633496B2 (en) 1997-12-12 2003-10-14 Saifun Semiconductors Ltd. Symmetric architecture for memory cells having widely spread metal bit lines
US6033998A (en) * 1998-03-09 2000-03-07 Lsi Logic Corporation Method of forming variable thickness gate dielectrics
US6215148B1 (en) 1998-05-20 2001-04-10 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
US6348711B1 (en) 1998-05-20 2002-02-19 Saifun Semiconductors Ltd. NROM cell with self-aligned programming and erasure areas
KR100455737B1 (ko) 1998-12-30 2005-04-19 주식회사 하이닉스반도체 반도체소자의게이트산화막형성방법
US6429063B1 (en) 1999-10-26 2002-08-06 Saifun Semiconductors Ltd. NROM cell with generally decoupled primary and secondary injection
US6214672B1 (en) * 1999-10-28 2001-04-10 United Semiconductor Corp. Method for manufacturing two-bit flash memory
US6396741B1 (en) 2000-05-04 2002-05-28 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
US6928001B2 (en) 2000-12-07 2005-08-09 Saifun Semiconductors Ltd. Programming and erasing methods for a non-volatile memory cell
US6490204B2 (en) 2000-05-04 2002-12-03 Saifun Semiconductors Ltd. Programming and erasing methods for a reference cell of an NROM array
US6614692B2 (en) 2001-01-18 2003-09-02 Saifun Semiconductors Ltd. EEPROM array and method for operation thereof
US6677805B2 (en) * 2001-04-05 2004-01-13 Saifun Semiconductors Ltd. Charge pump stage with body effect minimization
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6636440B2 (en) 2001-04-25 2003-10-21 Saifun Semiconductors Ltd. Method for operation of an EEPROM array, including refresh thereof
US6643181B2 (en) 2001-10-24 2003-11-04 Saifun Semiconductors Ltd. Method for erasing a memory cell
US7098107B2 (en) * 2001-11-19 2006-08-29 Saifun Semiconductor Ltd. Protective layer in memory device and method therefor
US6885585B2 (en) * 2001-12-20 2005-04-26 Saifun Semiconductors Ltd. NROM NOR array
US6583007B1 (en) 2001-12-20 2003-06-24 Saifun Semiconductors Ltd. Reducing secondary injection effects
US6700818B2 (en) 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US6826107B2 (en) 2002-08-01 2004-11-30 Saifun Semiconductors Ltd. High voltage insertion in flash memory cards
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US6887757B2 (en) * 2003-05-14 2005-05-03 Macronix International Co., Ltd. Method of manufacturing flash memory
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
EP1686592A3 (en) 2005-01-19 2007-04-25 Saifun Semiconductors Ltd. Partial erase verify
US8053812B2 (en) * 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
EP1746645A3 (en) 2005-07-18 2009-01-21 Saifun Semiconductors Ltd. Memory array with sub-minimum feature size word line spacing and method of fabrication
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7221138B2 (en) * 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US7352627B2 (en) 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
KR100751776B1 (ko) * 2006-02-27 2007-09-04 주식회사 케이에스티 청정강 제조용 산화몰리브덴 브리케트 및 그 제조방법
US7638835B2 (en) * 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7605579B2 (en) 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
US20080180160A1 (en) * 2007-01-31 2008-07-31 Infineon Technologies Ag High voltage dual gate cmos switching device and method
US8064255B2 (en) * 2007-12-31 2011-11-22 Cypress Semiconductor Corporation Architecture of a nvDRAM array and its sense regime
US8059458B2 (en) * 2007-12-31 2011-11-15 Cypress Semiconductor Corporation 3T high density nvDRAM cell
US8916432B1 (en) * 2014-01-21 2014-12-23 Cypress Semiconductor Corporation Methods to integrate SONOS into CMOS flow
JP2019102520A (ja) * 2017-11-29 2019-06-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3967981A (en) * 1971-01-14 1976-07-06 Shumpei Yamazaki Method for manufacturing a semiconductor field effort transistor
US3798752A (en) * 1971-03-11 1974-03-26 Nippon Electric Co Method of producing a silicon gate insulated-gate field effect transistor
US3986903A (en) * 1974-03-13 1976-10-19 Intel Corporation Mosfet transistor and method of fabrication
JPS5293278A (en) * 1976-01-30 1977-08-05 Matsushita Electronics Corp Manufacture for mos type semiconductor intergrated circuit
JPS52105784A (en) * 1976-03-01 1977-09-05 Sony Corp Mios type memory unit
US4035198A (en) * 1976-06-30 1977-07-12 International Business Machines Corporation Method of fabricating field effect transistors having self-registering electrical connections between gate electrodes and metallic interconnection lines, and fabrication of integrated circuits containing the transistors
US4179311A (en) * 1977-01-17 1979-12-18 Mostek Corporation Method of stabilizing semiconductor device by converting doped poly-Si to polyoxides
US4151021A (en) * 1977-01-26 1979-04-24 Texas Instruments Incorporated Method of making a high density floating gate electrically programmable ROM
JPS544086A (en) * 1977-06-10 1979-01-12 Fujitsu Ltd Memory circuit unit
US4224733A (en) * 1977-10-11 1980-09-30 Fujitsu Limited Ion implantation method
US4149307A (en) * 1977-12-28 1979-04-17 Hughes Aircraft Company Process for fabricating insulated-gate field-effect transistors with self-aligned contacts
US4198252A (en) * 1978-04-06 1980-04-15 Rca Corporation MNOS memory device
US4268328A (en) * 1978-04-21 1981-05-19 Mcdonnell Douglas Corporation Stripped nitride MOS/MNOS process
US4221045A (en) * 1978-06-06 1980-09-09 Rockwell International Corporation Self-aligned contacts in an ion implanted VLSI circuit
DE2832388C2 (de) * 1978-07-24 1986-08-14 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Herstellen von MNOS- und MOS-Transistoren in Silizium-Gate-Technologie auf einem Halbleitersubstrat
US4229755A (en) * 1978-08-15 1980-10-21 Rockwell International Corporation Fabrication of very large scale integrated circuits containing N-channel silicon gate nonvolatile memory elements
JPS5530846A (en) * 1978-08-28 1980-03-04 Hitachi Ltd Method for manufacturing fixed memory
US4170500A (en) * 1979-01-15 1979-10-09 Fairchild Camera And Instrument Corporation Process for forming field dielectric regions in semiconductor structures without encroaching on device regions

Also Published As

Publication number Publication date
JPH0122749B2 (enExample) 1989-04-27
GB2053565B (en) 1983-06-29
DE2923995A1 (de) 1980-12-18
CA1141868A (en) 1983-02-22
JPS562652A (en) 1981-01-12
US4306353A (en) 1981-12-22
GB2053565A (en) 1981-02-04
FR2458902A1 (fr) 1981-01-02
DE2923995C2 (de) 1985-11-07

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Legal Events

Date Code Title Description
ST Notification of lapse