FR2440123A1 - Mise sous tension conditionnelle d'un reseau logique programmable - Google Patents
Mise sous tension conditionnelle d'un reseau logique programmableInfo
- Publication number
- FR2440123A1 FR2440123A1 FR7922717A FR7922717A FR2440123A1 FR 2440123 A1 FR2440123 A1 FR 2440123A1 FR 7922717 A FR7922717 A FR 7922717A FR 7922717 A FR7922717 A FR 7922717A FR 2440123 A1 FR2440123 A1 FR 2440123A1
- Authority
- FR
- France
- Prior art keywords
- programmable logic
- matrix
- network
- logic network
- conditional power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
- H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes
Abstract
RESEAU LOGIQUE PROGRAMMABLE. CE RESEAU COMPRENANT UNE MATRICE ET 10 ET UNE MATRICE OU 24 A SA MATRICE OU ALIMENTEE PAR LA SOURCE 5V QUAND ET SEULEMENT QUAND LA COMBINAISON DE SIGNAUX FOURNIE AU RESEAU LOGIQUE PROGRAMMABLE EST UNE COMBINAISON LOGIQUEMENT UTILE. CECI EST REALISE PAR LE FAIT QUE, DANS CE CAS, LA PREMIERE LIGNE DE SORTIE 18A DU RESEAU ET EST A UN NIVEAU BAS DECLENCHANT PAR L'INTERMEDIAIRE DE L'INVERSEUR 27 LES ELEMENTS 26 DE LA PREMIERE COLONNE D'ELEMENTS DU RESEAU OU ALIMENTANT AINSI LES LIGNES DE SORTIE 28 DE LA MATRICE OU. PERMET DE REALISER UNE ECONOMIE DANS L'ALIMENTATION DES RESEAUX LOGIQUES PROGRAMMABLES ET PEUT ETRE UTILISE DANS TOUS LES TYPES DE CES RESEAUX.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/954,136 US4233667A (en) | 1978-10-23 | 1978-10-23 | Demand powered programmable logic array |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2440123A1 true FR2440123A1 (fr) | 1980-05-23 |
FR2440123B1 FR2440123B1 (fr) | 1981-10-02 |
Family
ID=25494980
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7922717A Granted FR2440123A1 (fr) | 1978-10-23 | 1979-09-04 | Mise sous tension conditionnelle d'un reseau logique programmable |
Country Status (6)
Country | Link |
---|---|
US (1) | US4233667A (fr) |
JP (1) | JPS5556733A (fr) |
DE (1) | DE2938374C2 (fr) |
FR (1) | FR2440123A1 (fr) |
GB (1) | GB2032663B (fr) |
IT (1) | IT1165344B (fr) |
Families Citing this family (68)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS558135A (en) * | 1978-07-04 | 1980-01-21 | Mamoru Tanaka | Rewritable programable logic array |
US4417233A (en) * | 1979-02-28 | 1983-11-22 | Matsushita Electric Industrial Co., Ltd. | Fully parallel threshold type analog-to-digital converter |
DE3121562A1 (de) * | 1981-05-30 | 1983-01-05 | Ibm Deutschland Gmbh, 7000 Stuttgart | Programmierbare logische hochintegrierte schaltungsanordnung |
US4467439A (en) * | 1981-06-30 | 1984-08-21 | Ibm Corporation | OR Product term function in the search array of a PLA |
US4429238A (en) * | 1981-08-14 | 1984-01-31 | Bell Telephone Laboratories, Incorporated | Structured logic array |
US4791602A (en) * | 1983-04-14 | 1988-12-13 | Control Data Corporation | Soft programmable logic array |
US4567385A (en) * | 1983-06-22 | 1986-01-28 | Harris Corporation | Power switched logic gates |
USRE34363E (en) * | 1984-03-12 | 1993-08-31 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
US4645953A (en) * | 1984-07-03 | 1987-02-24 | Monolithic Memories, Inc. | Current source which saves power in programmable logic array circuitry |
US4667337A (en) * | 1985-08-28 | 1987-05-19 | Westinghouse Electric Corp. | Integrated circuit having outputs configured for reduced state changes |
US4764691A (en) * | 1985-10-15 | 1988-08-16 | American Microsystems, Inc. | CMOS programmable logic array using NOR gates for clocking |
FR2592539B1 (fr) * | 1985-12-31 | 1988-02-12 | Philips Ind Commerciale | Reseau programmable en logique dynamique et son application. |
US4675556A (en) * | 1986-06-09 | 1987-06-23 | Intel Corporation | Binomially-encoded finite state machine |
US4697105A (en) * | 1986-07-23 | 1987-09-29 | American Telephone And Telegraph Company, At&T Bell Laboratories | CMOS programmable logic array |
JPH01109922A (ja) * | 1987-10-23 | 1989-04-26 | Mitsubishi Electric Corp | プログラマブルロジツクアレイ |
US4831285A (en) * | 1988-01-19 | 1989-05-16 | National Semiconductor Corporation | Self precharging static programmable logic array |
US5629907A (en) * | 1991-06-18 | 1997-05-13 | Dallas Semiconductor Corporation | Low power timekeeping system |
US5544078A (en) * | 1988-06-17 | 1996-08-06 | Dallas Semiconductor Corporation | Timekeeping comparison circuitry and dual storage memory cells to detect alarms |
US4959646A (en) * | 1988-06-17 | 1990-09-25 | Dallas Semiconductor Corporation | Dynamic PLA timing circuit |
US5081375A (en) * | 1989-01-19 | 1992-01-14 | National Semiconductor Corp. | Method for operating a multiple page programmable logic device |
US4942319A (en) * | 1989-01-19 | 1990-07-17 | National Semiconductor Corp. | Multiple page programmable logic architecture |
US5021689A (en) * | 1989-01-19 | 1991-06-04 | National Semiconductor Corp. | Multiple page programmable logic architecture |
JPH0378984U (fr) * | 1989-12-01 | 1991-08-12 | ||
US5055712A (en) * | 1990-04-05 | 1991-10-08 | National Semiconductor Corp. | Register file with programmable control, decode and/or data manipulation |
JP2544027B2 (ja) * | 1990-05-24 | 1996-10-16 | 株式会社東芝 | 低消費電力型プログラマブルロジックアレイおよびそれを用いた情報処理装置 |
US5189320A (en) * | 1991-09-23 | 1993-02-23 | Atmel Corporation | Programmable logic device with multiple shared logic arrays |
US5300831A (en) * | 1992-09-04 | 1994-04-05 | Pham Dac C | Logic macro and protocol for reduced power consumption during idle state |
US5311079A (en) * | 1992-12-17 | 1994-05-10 | Ditlow Gary S | Low power, high performance PLA |
US5528463A (en) * | 1993-07-16 | 1996-06-18 | Dallas Semiconductor Corp. | Low profile sockets and modules for surface mountable applications |
US5579206A (en) * | 1993-07-16 | 1996-11-26 | Dallas Semiconductor Corporation | Enhanced low profile sockets and module systems |
US5719505A (en) * | 1995-04-11 | 1998-02-17 | International Business Machines Corporation | Reduced power PLA |
US7266725B2 (en) | 2001-09-03 | 2007-09-04 | Pact Xpp Technologies Ag | Method for debugging reconfigurable architectures |
DE19651075A1 (de) | 1996-12-09 | 1998-06-10 | Pact Inf Tech Gmbh | Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen |
DE19654595A1 (de) | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen |
US5867038A (en) * | 1996-12-20 | 1999-02-02 | International Business Machines Corporation | Self-timed low power ratio-logic system having an input sensing circuit |
EP1329816B1 (fr) | 1996-12-27 | 2011-06-22 | Richter, Thomas | Procédé pour le transfert dynamique automatique de processeurs à flux de données (dfp) ainsi que de modules à deux ou plusieurs structures cellulaires programmables bidimensionnelles ou multidimensionnelles (fpga, dpga ou analogues) |
US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
US8686549B2 (en) | 2001-09-03 | 2014-04-01 | Martin Vorbach | Reconfigurable elements |
DE19861088A1 (de) | 1997-12-22 | 2000-02-10 | Pact Inf Tech Gmbh | Verfahren zur Reparatur von integrierten Schaltkreisen |
US6557092B1 (en) | 1999-03-29 | 2003-04-29 | Greg S. Callen | Programmable ALU |
JP2003505753A (ja) | 1999-06-10 | 2003-02-12 | ペーアーツェーテー インフォルマツィオーンステヒノロギー ゲゼルシャフト ミット ベシュレンクテル ハフツング | セル構造におけるシーケンス分割方法 |
JP2004506261A (ja) | 2000-06-13 | 2004-02-26 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | パイプラインctプロトコルおよびct通信 |
US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
AU2060002A (en) | 2000-10-06 | 2002-04-22 | Pact Inf Tech Gmbh | Method and device |
US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
WO2005045692A2 (fr) | 2003-08-28 | 2005-05-19 | Pact Xpp Technologies Ag | Dispositif et procede de traitement de donnees |
US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
US7844796B2 (en) | 2001-03-05 | 2010-11-30 | Martin Vorbach | Data processing device and method |
WO2002103532A2 (fr) | 2001-06-20 | 2002-12-27 | Pact Xpp Technologies Ag | Procede de traitement de donnees |
US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
US7434191B2 (en) | 2001-09-03 | 2008-10-07 | Pact Xpp Technologies Ag | Router |
US8686475B2 (en) | 2001-09-19 | 2014-04-01 | Pact Xpp Technologies Ag | Reconfigurable elements |
US7577822B2 (en) | 2001-12-14 | 2009-08-18 | Pact Xpp Technologies Ag | Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization |
US8281108B2 (en) | 2002-01-19 | 2012-10-02 | Martin Vorbach | Reconfigurable general purpose processor having time restricted configurations |
AU2003214003A1 (en) | 2002-02-18 | 2003-09-09 | Pact Xpp Technologies Ag | Bus systems and method for reconfiguration |
US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
WO2005010632A2 (fr) * | 2003-06-17 | 2005-02-03 | Pact Xpp Technologies Ag | Dispositif et procede de traitement de donnees |
US7657861B2 (en) | 2002-08-07 | 2010-02-02 | Pact Xpp Technologies Ag | Method and device for processing data |
WO2004021176A2 (fr) | 2002-08-07 | 2004-03-11 | Pact Xpp Technologies Ag | Procede et dispositif de traitement de donnees |
WO2004038599A1 (fr) | 2002-09-06 | 2004-05-06 | Pact Xpp Technologies Ag | Structure de sequenceur reconfigurable |
WO2007082730A1 (fr) | 2006-01-18 | 2007-07-26 | Pact Xpp Technologies Ag | Procédé de définition de matériels |
US7640444B2 (en) * | 2006-01-26 | 2009-12-29 | Nils Graef | Systems and methods for low power bus operation |
US7693257B2 (en) * | 2006-06-29 | 2010-04-06 | Accuray Incorporated | Treatment delivery optimization |
JP5203594B2 (ja) * | 2006-11-07 | 2013-06-05 | 株式会社東芝 | 暗号処理回路及び暗号処理方法 |
JP4851947B2 (ja) * | 2007-01-29 | 2012-01-11 | 株式会社東芝 | 論理回路 |
US20100272811A1 (en) * | 2008-07-23 | 2010-10-28 | Alkermes,Inc. | Complex of trospium and pharmaceutical compositions thereof |
US8661394B1 (en) | 2008-09-24 | 2014-02-25 | Iowa State University Research Foundation, Inc. | Depth-optimal mapping of logic chains in reconfigurable fabrics |
US8438522B1 (en) | 2008-09-24 | 2013-05-07 | Iowa State University Research Foundation, Inc. | Logic element architecture for generic logic chains in programmable devices |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3599182A (en) * | 1969-01-15 | 1971-08-10 | Ibm | Means for reducing power consumption in a memory device |
FR2286559A1 (fr) * | 1974-09-30 | 1976-04-23 | Siemens Ag | Dispositif logique integre et programmable |
US4103182A (en) * | 1976-09-01 | 1978-07-25 | Hewlett-Packard Company | Programmable transfer gate array |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2455178C2 (de) * | 1974-11-21 | 1982-12-23 | Siemens AG, 1000 Berlin und 8000 München | Integrierte, programmierbare Logikanordnung |
DE2606958A1 (de) * | 1976-02-20 | 1977-08-25 | Siemens Ag | Bausteinschaltung mit speichertransistoren |
GB1574058A (en) * | 1976-03-26 | 1980-09-03 | Tokyo Shibaura Electric Co | Power supply control in a memory system |
US4140921A (en) * | 1977-08-31 | 1979-02-20 | International Business Machines Corporation | Generalized performance power optimized PLA circuits |
-
1978
- 1978-10-23 US US05/954,136 patent/US4233667A/en not_active Expired - Lifetime
-
1979
- 1979-09-04 FR FR7922717A patent/FR2440123A1/fr active Granted
- 1979-09-07 JP JP11438279A patent/JPS5556733A/ja active Granted
- 1979-09-07 GB GB7931128A patent/GB2032663B/en not_active Expired
- 1979-09-22 DE DE2938374A patent/DE2938374C2/de not_active Expired
- 1979-09-28 IT IT26076/79A patent/IT1165344B/it active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3599182A (en) * | 1969-01-15 | 1971-08-10 | Ibm | Means for reducing power consumption in a memory device |
FR2286559A1 (fr) * | 1974-09-30 | 1976-04-23 | Siemens Ag | Dispositif logique integre et programmable |
US4103182A (en) * | 1976-09-01 | 1978-07-25 | Hewlett-Packard Company | Programmable transfer gate array |
Also Published As
Publication number | Publication date |
---|---|
IT7926076A0 (it) | 1979-09-28 |
DE2938374A1 (de) | 1980-04-24 |
DE2938374C2 (de) | 1982-10-21 |
JPS5556733A (en) | 1980-04-25 |
GB2032663A (en) | 1980-05-08 |
FR2440123B1 (fr) | 1981-10-02 |
GB2032663B (en) | 1982-12-01 |
IT1165344B (it) | 1987-04-22 |
US4233667A (en) | 1980-11-11 |
JPS6234181B2 (fr) | 1987-07-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |