FR2415838A1 - Dispositif de multiplication de vecteurs a deux termes - Google Patents
Dispositif de multiplication de vecteurs a deux termesInfo
- Publication number
- FR2415838A1 FR2415838A1 FR7902135A FR7902135A FR2415838A1 FR 2415838 A1 FR2415838 A1 FR 2415838A1 FR 7902135 A FR7902135 A FR 7902135A FR 7902135 A FR7902135 A FR 7902135A FR 2415838 A1 FR2415838 A1 FR 2415838A1
- Authority
- FR
- France
- Prior art keywords
- multiplication device
- term vector
- vector multiplication
- calculators
- calculating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/4806—Computations with complex numbers
- G06F7/4812—Complex multiplication
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Abstract
Dispositif de multiplication de vecteurs à deux termes. La présente invention concerne un dispositif de multiplication pour le calcul de AX + BY. Application aux calculatrices.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53008546A JPS6053907B2 (ja) | 1978-01-27 | 1978-01-27 | 二項ベクトル乗算回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2415838A1 true FR2415838A1 (fr) | 1979-08-24 |
FR2415838B1 FR2415838B1 (fr) | 1986-02-07 |
Family
ID=11696128
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7902135A Expired FR2415838B1 (fr) | 1978-01-27 | 1979-01-26 | Dispositif de multiplication de vecteurs a deux termes |
Country Status (5)
Country | Link |
---|---|
US (1) | US4215417A (fr) |
JP (1) | JPS6053907B2 (fr) |
DE (1) | DE2902766A1 (fr) |
FR (1) | FR2415838B1 (fr) |
GB (1) | GB2015215B (fr) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL8005506A (nl) * | 1980-10-06 | 1982-05-03 | Philips Nv | Inrichting voor het uitvoeren van een matnematische operatie en enkele toepassingen van deze inrichting. |
US5055712A (en) * | 1990-04-05 | 1991-10-08 | National Semiconductor Corp. | Register file with programmable control, decode and/or data manipulation |
US5241492A (en) * | 1991-05-06 | 1993-08-31 | Motorola, Inc. | Apparatus for performing multiply and accumulate instructions with reduced power and a method therefor |
US5402452A (en) * | 1992-08-25 | 1995-03-28 | Alcatel Network Systems, Inc. | Incremental phase smoothing desynchronizer and calculation apparatus |
FR2811168B1 (fr) * | 2000-06-30 | 2002-11-15 | Gemplus Card Int | Procede de conversion de la representation binaire d'un nombre dans une representation binaire signee |
US9459832B2 (en) | 2014-06-12 | 2016-10-04 | Bank Of America Corporation | Pipelined multiply-scan circuit |
JP2022020088A (ja) * | 2020-06-26 | 2022-02-01 | キヤノン株式会社 | 冷却装置、半導体製造装置および半導体製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB892112A (en) * | 1957-02-26 | 1962-03-21 | Emi Ltd | Improvements relating to serial digital multiplying and dividing devices |
US3079081A (en) * | 1958-12-27 | 1963-02-26 | Coste Louis Etienne | Digital computing apparatus utilizing algebraic-binary number representation |
US3737638A (en) * | 1972-07-18 | 1973-06-05 | Ibm | A series-parallel multiplication device using modified two{40 s complement arithmetic |
US3861585A (en) * | 1972-03-06 | 1975-01-21 | Inst Francais Du Petrole | Device for carrying out arithmetical and logical operations |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4020334A (en) * | 1975-09-10 | 1977-04-26 | General Electric Company | Integrated arithmetic unit for computing summed indexed products |
US4150434A (en) * | 1976-05-08 | 1979-04-17 | Tokyo Shibaura Electric Co., Ltd. | Matrix arithmetic apparatus |
PL106470B1 (pl) * | 1977-02-01 | 1979-12-31 | Inst Maszyn Matematycznych | Uklad cyfrowy do obliczania wartosci zlozonych wyrazen arytmetycznych |
-
1978
- 1978-01-27 JP JP53008546A patent/JPS6053907B2/ja not_active Expired
-
1979
- 1979-01-25 GB GB7902673A patent/GB2015215B/en not_active Expired
- 1979-01-25 DE DE19792902766 patent/DE2902766A1/de not_active Withdrawn
- 1979-01-26 US US06/006,707 patent/US4215417A/en not_active Expired - Lifetime
- 1979-01-26 FR FR7902135A patent/FR2415838B1/fr not_active Expired
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB892112A (en) * | 1957-02-26 | 1962-03-21 | Emi Ltd | Improvements relating to serial digital multiplying and dividing devices |
US3079081A (en) * | 1958-12-27 | 1963-02-26 | Coste Louis Etienne | Digital computing apparatus utilizing algebraic-binary number representation |
US3861585A (en) * | 1972-03-06 | 1975-01-21 | Inst Francais Du Petrole | Device for carrying out arithmetical and logical operations |
US3737638A (en) * | 1972-07-18 | 1973-06-05 | Ibm | A series-parallel multiplication device using modified two{40 s complement arithmetic |
Also Published As
Publication number | Publication date |
---|---|
US4215417A (en) | 1980-07-29 |
JPS54101633A (en) | 1979-08-10 |
GB2015215B (en) | 1982-03-31 |
DE2902766A1 (de) | 1979-08-02 |
JPS6053907B2 (ja) | 1985-11-27 |
GB2015215A (en) | 1979-09-05 |
FR2415838B1 (fr) | 1986-02-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |