FR2415838B1 - Dispositif de multiplication de vecteurs a deux termes - Google Patents

Dispositif de multiplication de vecteurs a deux termes

Info

Publication number
FR2415838B1
FR2415838B1 FR7902135A FR7902135A FR2415838B1 FR 2415838 B1 FR2415838 B1 FR 2415838B1 FR 7902135 A FR7902135 A FR 7902135A FR 7902135 A FR7902135 A FR 7902135A FR 2415838 B1 FR2415838 B1 FR 2415838B1
Authority
FR
France
Prior art keywords
term vector
vector multiplication
multiplication device
term
vector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7902135A
Other languages
English (en)
Other versions
FR2415838A1 (fr
Inventor
Takao Nishitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Publication of FR2415838A1 publication Critical patent/FR2415838A1/fr
Application granted granted Critical
Publication of FR2415838B1 publication Critical patent/FR2415838B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4806—Computations with complex numbers
    • G06F7/4812—Complex multiplication

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
FR7902135A 1978-01-27 1979-01-26 Dispositif de multiplication de vecteurs a deux termes Expired FR2415838B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53008546A JPS6053907B2 (ja) 1978-01-27 1978-01-27 二項ベクトル乗算回路

Publications (2)

Publication Number Publication Date
FR2415838A1 FR2415838A1 (fr) 1979-08-24
FR2415838B1 true FR2415838B1 (fr) 1986-02-07

Family

ID=11696128

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7902135A Expired FR2415838B1 (fr) 1978-01-27 1979-01-26 Dispositif de multiplication de vecteurs a deux termes

Country Status (5)

Country Link
US (1) US4215417A (fr)
JP (1) JPS6053907B2 (fr)
DE (1) DE2902766A1 (fr)
FR (1) FR2415838B1 (fr)
GB (1) GB2015215B (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8005506A (nl) * 1980-10-06 1982-05-03 Philips Nv Inrichting voor het uitvoeren van een matnematische operatie en enkele toepassingen van deze inrichting.
US5055712A (en) * 1990-04-05 1991-10-08 National Semiconductor Corp. Register file with programmable control, decode and/or data manipulation
US5241492A (en) * 1991-05-06 1993-08-31 Motorola, Inc. Apparatus for performing multiply and accumulate instructions with reduced power and a method therefor
US5402452A (en) * 1992-08-25 1995-03-28 Alcatel Network Systems, Inc. Incremental phase smoothing desynchronizer and calculation apparatus
FR2811168B1 (fr) * 2000-06-30 2002-11-15 Gemplus Card Int Procede de conversion de la representation binaire d'un nombre dans une representation binaire signee
US9459832B2 (en) 2014-06-12 2016-10-04 Bank Of America Corporation Pipelined multiply-scan circuit
JP7565716B2 (ja) * 2020-06-26 2024-10-11 キヤノン株式会社 冷却装置、半導体製造装置および半導体製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB892112A (en) * 1957-02-26 1962-03-21 Emi Ltd Improvements relating to serial digital multiplying and dividing devices
NL246808A (fr) * 1958-12-27
FR2175261A5 (fr) * 1972-03-06 1973-10-19 Inst Francais Du Petrole
US3737638A (en) * 1972-07-18 1973-06-05 Ibm A series-parallel multiplication device using modified two{40 s complement arithmetic
US4020334A (en) * 1975-09-10 1977-04-26 General Electric Company Integrated arithmetic unit for computing summed indexed products
US4150434A (en) * 1976-05-08 1979-04-17 Tokyo Shibaura Electric Co., Ltd. Matrix arithmetic apparatus
PL106470B1 (pl) * 1977-02-01 1979-12-31 Inst Maszyn Matematycznych Uklad cyfrowy do obliczania wartosci zlozonych wyrazen arytmetycznych

Also Published As

Publication number Publication date
JPS54101633A (en) 1979-08-10
JPS6053907B2 (ja) 1985-11-27
DE2902766A1 (de) 1979-08-02
FR2415838A1 (fr) 1979-08-24
US4215417A (en) 1980-07-29
GB2015215A (en) 1979-09-05
GB2015215B (en) 1982-03-31

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Legal Events

Date Code Title Description
ST Notification of lapse